Gps_Tracking_System_Project_Team3
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Macros
tm4c123gh6pm.h File Reference

Go to the source code of this file.

Macros

#define INT_GPIOA   16
 
#define INT_GPIOB   17
 
#define INT_GPIOC   18
 
#define INT_GPIOD   19
 
#define INT_GPIOE   20
 
#define INT_UART0   21
 
#define INT_UART1   22
 
#define INT_SSI0   23
 
#define INT_I2C0   24
 
#define INT_PWM0_FAULT   25
 
#define INT_PWM0_0   26
 
#define INT_PWM0_1   27
 
#define INT_PWM0_2   28
 
#define INT_QEI0   29
 
#define INT_ADC0SS0   30
 
#define INT_ADC0SS1   31
 
#define INT_ADC0SS2   32
 
#define INT_ADC0SS3   33
 
#define INT_WATCHDOG   34
 
#define INT_TIMER0A   35
 
#define INT_TIMER0B   36
 
#define INT_TIMER1A   37
 
#define INT_TIMER1B   38
 
#define INT_TIMER2A   39
 
#define INT_TIMER2B   40
 
#define INT_COMP0   41
 
#define INT_COMP1   42
 
#define INT_SYSCTL   44
 
#define INT_FLASH   45
 
#define INT_GPIOF   46
 
#define INT_UART2   49
 
#define INT_SSI1   50
 
#define INT_TIMER3A   51
 
#define INT_TIMER3B   52
 
#define INT_I2C1   53
 
#define INT_QEI1   54
 
#define INT_CAN0   55
 
#define INT_CAN1   56
 
#define INT_HIBERNATE   59
 
#define INT_USB0   60
 
#define INT_PWM0_3   61
 
#define INT_UDMA   62
 
#define INT_UDMAERR   63
 
#define INT_ADC1SS0   64
 
#define INT_ADC1SS1   65
 
#define INT_ADC1SS2   66
 
#define INT_ADC1SS3   67
 
#define INT_SSI2   73
 
#define INT_SSI3   74
 
#define INT_UART3   75
 
#define INT_UART4   76
 
#define INT_UART5   77
 
#define INT_UART6   78
 
#define INT_UART7   79
 
#define INT_I2C2   84
 
#define INT_I2C3   85
 
#define INT_TIMER4A   86
 
#define INT_TIMER4B   87
 
#define INT_TIMER5A   108
 
#define INT_TIMER5B   109
 
#define INT_WTIMER0A   110
 
#define INT_WTIMER0B   111
 
#define INT_WTIMER1A   112
 
#define INT_WTIMER1B   113
 
#define INT_WTIMER2A   114
 
#define INT_WTIMER2B   115
 
#define INT_WTIMER3A   116
 
#define INT_WTIMER3B   117
 
#define INT_WTIMER4A   118
 
#define INT_WTIMER4B   119
 
#define INT_WTIMER5A   120
 
#define INT_WTIMER5B   121
 
#define INT_SYSEXC   122
 
#define INT_PWM1_0   150
 
#define INT_PWM1_1   151
 
#define INT_PWM1_2   152
 
#define INT_PWM1_3   153
 
#define INT_PWM1_FAULT   154
 
#define WATCHDOG0_LOAD_R   (*((volatile u32 *)0x40000000))
 
#define WATCHDOG0_VALUE_R   (*((volatile u32 *)0x40000004))
 
#define WATCHDOG0_CTL_R   (*((volatile u32 *)0x40000008))
 
#define WATCHDOG0_ICR_R   (*((volatile u32 *)0x4000000C))
 
#define WATCHDOG0_RIS_R   (*((volatile u32 *)0x40000010))
 
#define WATCHDOG0_MIS_R   (*((volatile u32 *)0x40000014))
 
#define WATCHDOG0_TEST_R   (*((volatile u32 *)0x40000418))
 
#define WATCHDOG0_LOCK_R   (*((volatile u32 *)0x40000C00))
 
#define WATCHDOG1_LOAD_R   (*((volatile u32 *)0x40001000))
 
#define WATCHDOG1_VALUE_R   (*((volatile u32 *)0x40001004))
 
#define WATCHDOG1_CTL_R   (*((volatile u32 *)0x40001008))
 
#define WATCHDOG1_ICR_R   (*((volatile u32 *)0x4000100C))
 
#define WATCHDOG1_RIS_R   (*((volatile u32 *)0x40001010))
 
#define WATCHDOG1_MIS_R   (*((volatile u32 *)0x40001014))
 
#define WATCHDOG1_TEST_R   (*((volatile u32 *)0x40001418))
 
#define WATCHDOG1_LOCK_R   (*((volatile u32 *)0x40001C00))
 
#define GPIO_PORTA_DATA_BITS_R   ((volatile u32 *)0x40004000)
 
#define GPIO_PORTA_DATA_R   (*((volatile u32 *)0x400043FC))
 
#define GPIO_PORTA_DIR_R   (*((volatile u32 *)0x40004400))
 
#define GPIO_PORTA_IS_R   (*((volatile u32 *)0x40004404))
 
#define GPIO_PORTA_IBE_R   (*((volatile u32 *)0x40004408))
 
#define GPIO_PORTA_IEV_R   (*((volatile u32 *)0x4000440C))
 
#define GPIO_PORTA_IM_R   (*((volatile u32 *)0x40004410))
 
#define GPIO_PORTA_RIS_R   (*((volatile u32 *)0x40004414))
 
#define GPIO_PORTA_MIS_R   (*((volatile u32 *)0x40004418))
 
#define GPIO_PORTA_ICR_R   (*((volatile u32 *)0x4000441C))
 
#define GPIO_PORTA_AFSEL_R   (*((volatile u32 *)0x40004420))
 
#define GPIO_PORTA_DR2R_R   (*((volatile u32 *)0x40004500))
 
#define GPIO_PORTA_DR4R_R   (*((volatile u32 *)0x40004504))
 
#define GPIO_PORTA_DR8R_R   (*((volatile u32 *)0x40004508))
 
#define GPIO_PORTA_ODR_R   (*((volatile u32 *)0x4000450C))
 
#define GPIO_PORTA_PUR_R   (*((volatile u32 *)0x40004510))
 
#define GPIO_PORTA_PDR_R   (*((volatile u32 *)0x40004514))
 
#define GPIO_PORTA_SLR_R   (*((volatile u32 *)0x40004518))
 
#define GPIO_PORTA_DEN_R   (*((volatile u32 *)0x4000451C))
 
#define GPIO_PORTA_LOCK_R   (*((volatile u32 *)0x40004520))
 
#define GPIO_PORTA_CR_R   (*((volatile u32 *)0x40004524))
 
#define GPIO_PORTA_AMSEL_R   (*((volatile u32 *)0x40004528))
 
#define GPIO_PORTA_PCTL_R   (*((volatile u32 *)0x4000452C))
 
#define GPIO_PORTA_ADCCTL_R   (*((volatile u32 *)0x40004530))
 
#define GPIO_PORTA_DMACTL_R   (*((volatile u32 *)0x40004534))
 
#define GPIO_PORTB_DATA_BITS_R   ((volatile u32 *)0x40005000)
 
#define GPIO_PORTB_DATA_R   (*((volatile u32 *)0x400053FC))
 
#define GPIO_PORTB_DIR_R   (*((volatile u32 *)0x40005400))
 
#define GPIO_PORTB_IS_R   (*((volatile u32 *)0x40005404))
 
#define GPIO_PORTB_IBE_R   (*((volatile u32 *)0x40005408))
 
#define GPIO_PORTB_IEV_R   (*((volatile u32 *)0x4000540C))
 
#define GPIO_PORTB_IM_R   (*((volatile u32 *)0x40005410))
 
#define GPIO_PORTB_RIS_R   (*((volatile u32 *)0x40005414))
 
#define GPIO_PORTB_MIS_R   (*((volatile u32 *)0x40005418))
 
#define GPIO_PORTB_ICR_R   (*((volatile u32 *)0x4000541C))
 
#define GPIO_PORTB_AFSEL_R   (*((volatile u32 *)0x40005420))
 
#define GPIO_PORTB_DR2R_R   (*((volatile u32 *)0x40005500))
 
#define GPIO_PORTB_DR4R_R   (*((volatile u32 *)0x40005504))
 
#define GPIO_PORTB_DR8R_R   (*((volatile u32 *)0x40005508))
 
#define GPIO_PORTB_ODR_R   (*((volatile u32 *)0x4000550C))
 
#define GPIO_PORTB_PUR_R   (*((volatile u32 *)0x40005510))
 
#define GPIO_PORTB_PDR_R   (*((volatile u32 *)0x40005514))
 
#define GPIO_PORTB_SLR_R   (*((volatile u32 *)0x40005518))
 
#define GPIO_PORTB_DEN_R   (*((volatile u32 *)0x4000551C))
 
#define GPIO_PORTB_LOCK_R   (*((volatile u32 *)0x40005520))
 
#define GPIO_PORTB_CR_R   (*((volatile u32 *)0x40005524))
 
#define GPIO_PORTB_AMSEL_R   (*((volatile u32 *)0x40005528))
 
#define GPIO_PORTB_PCTL_R   (*((volatile u32 *)0x4000552C))
 
#define GPIO_PORTB_ADCCTL_R   (*((volatile u32 *)0x40005530))
 
#define GPIO_PORTB_DMACTL_R   (*((volatile u32 *)0x40005534))
 
#define GPIO_PORTC_DATA_BITS_R   ((volatile u32 *)0x40006000)
 
#define GPIO_PORTC_DATA_R   (*((volatile u32 *)0x400063FC))
 
#define GPIO_PORTC_DIR_R   (*((volatile u32 *)0x40006400))
 
#define GPIO_PORTC_IS_R   (*((volatile u32 *)0x40006404))
 
#define GPIO_PORTC_IBE_R   (*((volatile u32 *)0x40006408))
 
#define GPIO_PORTC_IEV_R   (*((volatile u32 *)0x4000640C))
 
#define GPIO_PORTC_IM_R   (*((volatile u32 *)0x40006410))
 
#define GPIO_PORTC_RIS_R   (*((volatile u32 *)0x40006414))
 
#define GPIO_PORTC_MIS_R   (*((volatile u32 *)0x40006418))
 
#define GPIO_PORTC_ICR_R   (*((volatile u32 *)0x4000641C))
 
#define GPIO_PORTC_AFSEL_R   (*((volatile u32 *)0x40006420))
 
#define GPIO_PORTC_DR2R_R   (*((volatile u32 *)0x40006500))
 
#define GPIO_PORTC_DR4R_R   (*((volatile u32 *)0x40006504))
 
#define GPIO_PORTC_DR8R_R   (*((volatile u32 *)0x40006508))
 
#define GPIO_PORTC_ODR_R   (*((volatile u32 *)0x4000650C))
 
#define GPIO_PORTC_PUR_R   (*((volatile u32 *)0x40006510))
 
#define GPIO_PORTC_PDR_R   (*((volatile u32 *)0x40006514))
 
#define GPIO_PORTC_SLR_R   (*((volatile u32 *)0x40006518))
 
#define GPIO_PORTC_DEN_R   (*((volatile u32 *)0x4000651C))
 
#define GPIO_PORTC_LOCK_R   (*((volatile u32 *)0x40006520))
 
#define GPIO_PORTC_CR_R   (*((volatile u32 *)0x40006524))
 
#define GPIO_PORTC_AMSEL_R   (*((volatile u32 *)0x40006528))
 
#define GPIO_PORTC_PCTL_R   (*((volatile u32 *)0x4000652C))
 
#define GPIO_PORTC_ADCCTL_R   (*((volatile u32 *)0x40006530))
 
#define GPIO_PORTC_DMACTL_R   (*((volatile u32 *)0x40006534))
 
#define GPIO_PORTD_DATA_BITS_R   ((volatile u32 *)0x40007000)
 
#define GPIO_PORTD_DATA_R   (*((volatile u32 *)0x400073FC))
 
#define GPIO_PORTD_DIR_R   (*((volatile u32 *)0x40007400))
 
#define GPIO_PORTD_IS_R   (*((volatile u32 *)0x40007404))
 
#define GPIO_PORTD_IBE_R   (*((volatile u32 *)0x40007408))
 
#define GPIO_PORTD_IEV_R   (*((volatile u32 *)0x4000740C))
 
#define GPIO_PORTD_IM_R   (*((volatile u32 *)0x40007410))
 
#define GPIO_PORTD_RIS_R   (*((volatile u32 *)0x40007414))
 
#define GPIO_PORTD_MIS_R   (*((volatile u32 *)0x40007418))
 
#define GPIO_PORTD_ICR_R   (*((volatile u32 *)0x4000741C))
 
#define GPIO_PORTD_AFSEL_R   (*((volatile u32 *)0x40007420))
 
#define GPIO_PORTD_DR2R_R   (*((volatile u32 *)0x40007500))
 
#define GPIO_PORTD_DR4R_R   (*((volatile u32 *)0x40007504))
 
#define GPIO_PORTD_DR8R_R   (*((volatile u32 *)0x40007508))
 
#define GPIO_PORTD_ODR_R   (*((volatile u32 *)0x4000750C))
 
#define GPIO_PORTD_PUR_R   (*((volatile u32 *)0x40007510))
 
#define GPIO_PORTD_PDR_R   (*((volatile u32 *)0x40007514))
 
#define GPIO_PORTD_SLR_R   (*((volatile u32 *)0x40007518))
 
#define GPIO_PORTD_DEN_R   (*((volatile u32 *)0x4000751C))
 
#define GPIO_PORTD_LOCK_R   (*((volatile u32 *)0x40007520))
 
#define GPIO_PORTD_CR_R   (*((volatile u32 *)0x40007524))
 
#define GPIO_PORTD_AMSEL_R   (*((volatile u32 *)0x40007528))
 
#define GPIO_PORTD_PCTL_R   (*((volatile u32 *)0x4000752C))
 
#define GPIO_PORTD_ADCCTL_R   (*((volatile u32 *)0x40007530))
 
#define GPIO_PORTD_DMACTL_R   (*((volatile u32 *)0x40007534))
 
#define SSI0_CR0_R   (*((volatile u32 *)0x40008000))
 
#define SSI0_CR1_R   (*((volatile u32 *)0x40008004))
 
#define SSI0_DR_R   (*((volatile u32 *)0x40008008))
 
#define SSI0_SR_R   (*((volatile u32 *)0x4000800C))
 
#define SSI0_CPSR_R   (*((volatile u32 *)0x40008010))
 
#define SSI0_IM_R   (*((volatile u32 *)0x40008014))
 
#define SSI0_RIS_R   (*((volatile u32 *)0x40008018))
 
#define SSI0_MIS_R   (*((volatile u32 *)0x4000801C))
 
#define SSI0_ICR_R   (*((volatile u32 *)0x40008020))
 
#define SSI0_DMACTL_R   (*((volatile u32 *)0x40008024))
 
#define SSI0_CC_R   (*((volatile u32 *)0x40008FC8))
 
#define SSI1_CR0_R   (*((volatile u32 *)0x40009000))
 
#define SSI1_CR1_R   (*((volatile u32 *)0x40009004))
 
#define SSI1_DR_R   (*((volatile u32 *)0x40009008))
 
#define SSI1_SR_R   (*((volatile u32 *)0x4000900C))
 
#define SSI1_CPSR_R   (*((volatile u32 *)0x40009010))
 
#define SSI1_IM_R   (*((volatile u32 *)0x40009014))
 
#define SSI1_RIS_R   (*((volatile u32 *)0x40009018))
 
#define SSI1_MIS_R   (*((volatile u32 *)0x4000901C))
 
#define SSI1_ICR_R   (*((volatile u32 *)0x40009020))
 
#define SSI1_DMACTL_R   (*((volatile u32 *)0x40009024))
 
#define SSI1_CC_R   (*((volatile u32 *)0x40009FC8))
 
#define SSI2_CR0_R   (*((volatile u32 *)0x4000A000))
 
#define SSI2_CR1_R   (*((volatile u32 *)0x4000A004))
 
#define SSI2_DR_R   (*((volatile u32 *)0x4000A008))
 
#define SSI2_SR_R   (*((volatile u32 *)0x4000A00C))
 
#define SSI2_CPSR_R   (*((volatile u32 *)0x4000A010))
 
#define SSI2_IM_R   (*((volatile u32 *)0x4000A014))
 
#define SSI2_RIS_R   (*((volatile u32 *)0x4000A018))
 
#define SSI2_MIS_R   (*((volatile u32 *)0x4000A01C))
 
#define SSI2_ICR_R   (*((volatile u32 *)0x4000A020))
 
#define SSI2_DMACTL_R   (*((volatile u32 *)0x4000A024))
 
#define SSI2_CC_R   (*((volatile u32 *)0x4000AFC8))
 
#define SSI3_CR0_R   (*((volatile u32 *)0x4000B000))
 
#define SSI3_CR1_R   (*((volatile u32 *)0x4000B004))
 
#define SSI3_DR_R   (*((volatile u32 *)0x4000B008))
 
#define SSI3_SR_R   (*((volatile u32 *)0x4000B00C))
 
#define SSI3_CPSR_R   (*((volatile u32 *)0x4000B010))
 
#define SSI3_IM_R   (*((volatile u32 *)0x4000B014))
 
#define SSI3_RIS_R   (*((volatile u32 *)0x4000B018))
 
#define SSI3_MIS_R   (*((volatile u32 *)0x4000B01C))
 
#define SSI3_ICR_R   (*((volatile u32 *)0x4000B020))
 
#define SSI3_DMACTL_R   (*((volatile u32 *)0x4000B024))
 
#define SSI3_CC_R   (*((volatile u32 *)0x4000BFC8))
 
#define UART0_DR_R   (*((volatile u32 *)0x4000C000))
 
#define UART0_RSR_R   (*((volatile u32 *)0x4000C004))
 
#define UART0_ECR_R   (*((volatile u32 *)0x4000C004))
 
#define UART0_FR_R   (*((volatile u32 *)0x4000C018))
 
#define UART0_ILPR_R   (*((volatile u32 *)0x4000C020))
 
#define UART0_IBRD_R   (*((volatile u32 *)0x4000C024))
 
#define UART0_FBRD_R   (*((volatile u32 *)0x4000C028))
 
#define UART0_LCRH_R   (*((volatile u32 *)0x4000C02C))
 
#define UART0_CTL_R   (*((volatile u32 *)0x4000C030))
 
#define UART0_IFLS_R   (*((volatile u32 *)0x4000C034))
 
#define UART0_IM_R   (*((volatile u32 *)0x4000C038))
 
#define UART0_RIS_R   (*((volatile u32 *)0x4000C03C))
 
#define UART0_MIS_R   (*((volatile u32 *)0x4000C040))
 
#define UART0_ICR_R   (*((volatile u32 *)0x4000C044))
 
#define UART0_DMACTL_R   (*((volatile u32 *)0x4000C048))
 
#define UART0_9BITADDR_R   (*((volatile u32 *)0x4000C0A4))
 
#define UART0_9BITAMASK_R   (*((volatile u32 *)0x4000C0A8))
 
#define UART0_PP_R   (*((volatile u32 *)0x4000CFC0))
 
#define UART0_CC_R   (*((volatile u32 *)0x4000CFC8))
 
#define UART1_DR_R   (*((volatile u32 *)0x4000D000))
 
#define UART1_RSR_R   (*((volatile u32 *)0x4000D004))
 
#define UART1_ECR_R   (*((volatile u32 *)0x4000D004))
 
#define UART1_FR_R   (*((volatile u32 *)0x4000D018))
 
#define UART1_ILPR_R   (*((volatile u32 *)0x4000D020))
 
#define UART1_IBRD_R   (*((volatile u32 *)0x4000D024))
 
#define UART1_FBRD_R   (*((volatile u32 *)0x4000D028))
 
#define UART1_LCRH_R   (*((volatile u32 *)0x4000D02C))
 
#define UART1_CTL_R   (*((volatile u32 *)0x4000D030))
 
#define UART1_IFLS_R   (*((volatile u32 *)0x4000D034))
 
#define UART1_IM_R   (*((volatile u32 *)0x4000D038))
 
#define UART1_RIS_R   (*((volatile u32 *)0x4000D03C))
 
#define UART1_MIS_R   (*((volatile u32 *)0x4000D040))
 
#define UART1_ICR_R   (*((volatile u32 *)0x4000D044))
 
#define UART1_DMACTL_R   (*((volatile u32 *)0x4000D048))
 
#define UART1_9BITADDR_R   (*((volatile u32 *)0x4000D0A4))
 
#define UART1_9BITAMASK_R   (*((volatile u32 *)0x4000D0A8))
 
#define UART1_PP_R   (*((volatile u32 *)0x4000DFC0))
 
#define UART1_CC_R   (*((volatile u32 *)0x4000DFC8))
 
#define UART2_DR_R   (*((volatile u32 *)0x4000E000))
 
#define UART2_RSR_R   (*((volatile u32 *)0x4000E004))
 
#define UART2_ECR_R   (*((volatile u32 *)0x4000E004))
 
#define UART2_FR_R   (*((volatile u32 *)0x4000E018))
 
#define UART2_ILPR_R   (*((volatile u32 *)0x4000E020))
 
#define UART2_IBRD_R   (*((volatile u32 *)0x4000E024))
 
#define UART2_FBRD_R   (*((volatile u32 *)0x4000E028))
 
#define UART2_LCRH_R   (*((volatile u32 *)0x4000E02C))
 
#define UART2_CTL_R   (*((volatile u32 *)0x4000E030))
 
#define UART2_IFLS_R   (*((volatile u32 *)0x4000E034))
 
#define UART2_IM_R   (*((volatile u32 *)0x4000E038))
 
#define UART2_RIS_R   (*((volatile u32 *)0x4000E03C))
 
#define UART2_MIS_R   (*((volatile u32 *)0x4000E040))
 
#define UART2_ICR_R   (*((volatile u32 *)0x4000E044))
 
#define UART2_DMACTL_R   (*((volatile u32 *)0x4000E048))
 
#define UART2_9BITADDR_R   (*((volatile u32 *)0x4000E0A4))
 
#define UART2_9BITAMASK_R   (*((volatile u32 *)0x4000E0A8))
 
#define UART2_PP_R   (*((volatile u32 *)0x4000EFC0))
 
#define UART2_CC_R   (*((volatile u32 *)0x4000EFC8))
 
#define UART3_DR_R   (*((volatile u32 *)0x4000F000))
 
#define UART3_RSR_R   (*((volatile u32 *)0x4000F004))
 
#define UART3_ECR_R   (*((volatile u32 *)0x4000F004))
 
#define UART3_FR_R   (*((volatile u32 *)0x4000F018))
 
#define UART3_ILPR_R   (*((volatile u32 *)0x4000F020))
 
#define UART3_IBRD_R   (*((volatile u32 *)0x4000F024))
 
#define UART3_FBRD_R   (*((volatile u32 *)0x4000F028))
 
#define UART3_LCRH_R   (*((volatile u32 *)0x4000F02C))
 
#define UART3_CTL_R   (*((volatile u32 *)0x4000F030))
 
#define UART3_IFLS_R   (*((volatile u32 *)0x4000F034))
 
#define UART3_IM_R   (*((volatile u32 *)0x4000F038))
 
#define UART3_RIS_R   (*((volatile u32 *)0x4000F03C))
 
#define UART3_MIS_R   (*((volatile u32 *)0x4000F040))
 
#define UART3_ICR_R   (*((volatile u32 *)0x4000F044))
 
#define UART3_DMACTL_R   (*((volatile u32 *)0x4000F048))
 
#define UART3_9BITADDR_R   (*((volatile u32 *)0x4000F0A4))
 
#define UART3_9BITAMASK_R   (*((volatile u32 *)0x4000F0A8))
 
#define UART3_PP_R   (*((volatile u32 *)0x4000FFC0))
 
#define UART3_CC_R   (*((volatile u32 *)0x4000FFC8))
 
#define UART4_DR_R   (*((volatile u32 *)0x40010000))
 
#define UART4_RSR_R   (*((volatile u32 *)0x40010004))
 
#define UART4_ECR_R   (*((volatile u32 *)0x40010004))
 
#define UART4_FR_R   (*((volatile u32 *)0x40010018))
 
#define UART4_ILPR_R   (*((volatile u32 *)0x40010020))
 
#define UART4_IBRD_R   (*((volatile u32 *)0x40010024))
 
#define UART4_FBRD_R   (*((volatile u32 *)0x40010028))
 
#define UART4_LCRH_R   (*((volatile u32 *)0x4001002C))
 
#define UART4_CTL_R   (*((volatile u32 *)0x40010030))
 
#define UART4_IFLS_R   (*((volatile u32 *)0x40010034))
 
#define UART4_IM_R   (*((volatile u32 *)0x40010038))
 
#define UART4_RIS_R   (*((volatile u32 *)0x4001003C))
 
#define UART4_MIS_R   (*((volatile u32 *)0x40010040))
 
#define UART4_ICR_R   (*((volatile u32 *)0x40010044))
 
#define UART4_DMACTL_R   (*((volatile u32 *)0x40010048))
 
#define UART4_9BITADDR_R   (*((volatile u32 *)0x400100A4))
 
#define UART4_9BITAMASK_R   (*((volatile u32 *)0x400100A8))
 
#define UART4_PP_R   (*((volatile u32 *)0x40010FC0))
 
#define UART4_CC_R   (*((volatile u32 *)0x40010FC8))
 
#define UART5_DR_R   (*((volatile u32 *)0x40011000))
 
#define UART5_RSR_R   (*((volatile u32 *)0x40011004))
 
#define UART5_ECR_R   (*((volatile u32 *)0x40011004))
 
#define UART5_FR_R   (*((volatile u32 *)0x40011018))
 
#define UART5_ILPR_R   (*((volatile u32 *)0x40011020))
 
#define UART5_IBRD_R   (*((volatile u32 *)0x40011024))
 
#define UART5_FBRD_R   (*((volatile u32 *)0x40011028))
 
#define UART5_LCRH_R   (*((volatile u32 *)0x4001102C))
 
#define UART5_CTL_R   (*((volatile u32 *)0x40011030))
 
#define UART5_IFLS_R   (*((volatile u32 *)0x40011034))
 
#define UART5_IM_R   (*((volatile u32 *)0x40011038))
 
#define UART5_RIS_R   (*((volatile u32 *)0x4001103C))
 
#define UART5_MIS_R   (*((volatile u32 *)0x40011040))
 
#define UART5_ICR_R   (*((volatile u32 *)0x40011044))
 
#define UART5_DMACTL_R   (*((volatile u32 *)0x40011048))
 
#define UART5_9BITADDR_R   (*((volatile u32 *)0x400110A4))
 
#define UART5_9BITAMASK_R   (*((volatile u32 *)0x400110A8))
 
#define UART5_PP_R   (*((volatile u32 *)0x40011FC0))
 
#define UART5_CC_R   (*((volatile u32 *)0x40011FC8))
 
#define UART6_DR_R   (*((volatile u32 *)0x40012000))
 
#define UART6_RSR_R   (*((volatile u32 *)0x40012004))
 
#define UART6_ECR_R   (*((volatile u32 *)0x40012004))
 
#define UART6_FR_R   (*((volatile u32 *)0x40012018))
 
#define UART6_ILPR_R   (*((volatile u32 *)0x40012020))
 
#define UART6_IBRD_R   (*((volatile u32 *)0x40012024))
 
#define UART6_FBRD_R   (*((volatile u32 *)0x40012028))
 
#define UART6_LCRH_R   (*((volatile u32 *)0x4001202C))
 
#define UART6_CTL_R   (*((volatile u32 *)0x40012030))
 
#define UART6_IFLS_R   (*((volatile u32 *)0x40012034))
 
#define UART6_IM_R   (*((volatile u32 *)0x40012038))
 
#define UART6_RIS_R   (*((volatile u32 *)0x4001203C))
 
#define UART6_MIS_R   (*((volatile u32 *)0x40012040))
 
#define UART6_ICR_R   (*((volatile u32 *)0x40012044))
 
#define UART6_DMACTL_R   (*((volatile u32 *)0x40012048))
 
#define UART6_9BITADDR_R   (*((volatile u32 *)0x400120A4))
 
#define UART6_9BITAMASK_R   (*((volatile u32 *)0x400120A8))
 
#define UART6_PP_R   (*((volatile u32 *)0x40012FC0))
 
#define UART6_CC_R   (*((volatile u32 *)0x40012FC8))
 
#define UART7_DR_R   (*((volatile u32 *)0x40013000))
 
#define UART7_RSR_R   (*((volatile u32 *)0x40013004))
 
#define UART7_ECR_R   (*((volatile u32 *)0x40013004))
 
#define UART7_FR_R   (*((volatile u32 *)0x40013018))
 
#define UART7_ILPR_R   (*((volatile u32 *)0x40013020))
 
#define UART7_IBRD_R   (*((volatile u32 *)0x40013024))
 
#define UART7_FBRD_R   (*((volatile u32 *)0x40013028))
 
#define UART7_LCRH_R   (*((volatile u32 *)0x4001302C))
 
#define UART7_CTL_R   (*((volatile u32 *)0x40013030))
 
#define UART7_IFLS_R   (*((volatile u32 *)0x40013034))
 
#define UART7_IM_R   (*((volatile u32 *)0x40013038))
 
#define UART7_RIS_R   (*((volatile u32 *)0x4001303C))
 
#define UART7_MIS_R   (*((volatile u32 *)0x40013040))
 
#define UART7_ICR_R   (*((volatile u32 *)0x40013044))
 
#define UART7_DMACTL_R   (*((volatile u32 *)0x40013048))
 
#define UART7_9BITADDR_R   (*((volatile u32 *)0x400130A4))
 
#define UART7_9BITAMASK_R   (*((volatile u32 *)0x400130A8))
 
#define UART7_PP_R   (*((volatile u32 *)0x40013FC0))
 
#define UART7_CC_R   (*((volatile u32 *)0x40013FC8))
 
#define I2C0_MSA_R   (*((volatile u32 *)0x40020000))
 
#define I2C0_MCS_R   (*((volatile u32 *)0x40020004))
 
#define I2C0_MDR_R   (*((volatile u32 *)0x40020008))
 
#define I2C0_MTPR_R   (*((volatile u32 *)0x4002000C))
 
#define I2C0_MIMR_R   (*((volatile u32 *)0x40020010))
 
#define I2C0_MRIS_R   (*((volatile u32 *)0x40020014))
 
#define I2C0_MMIS_R   (*((volatile u32 *)0x40020018))
 
#define I2C0_MICR_R   (*((volatile u32 *)0x4002001C))
 
#define I2C0_MCR_R   (*((volatile u32 *)0x40020020))
 
#define I2C0_MCLKOCNT_R   (*((volatile u32 *)0x40020024))
 
#define I2C0_MBMON_R   (*((volatile u32 *)0x4002002C))
 
#define I2C0_MCR2_R   (*((volatile u32 *)0x40020038))
 
#define I2C0_SOAR_R   (*((volatile u32 *)0x40020800))
 
#define I2C0_SCSR_R   (*((volatile u32 *)0x40020804))
 
#define I2C0_SDR_R   (*((volatile u32 *)0x40020808))
 
#define I2C0_SIMR_R   (*((volatile u32 *)0x4002080C))
 
#define I2C0_SRIS_R   (*((volatile u32 *)0x40020810))
 
#define I2C0_SMIS_R   (*((volatile u32 *)0x40020814))
 
#define I2C0_SICR_R   (*((volatile u32 *)0x40020818))
 
#define I2C0_SOAR2_R   (*((volatile u32 *)0x4002081C))
 
#define I2C0_SACKCTL_R   (*((volatile u32 *)0x40020820))
 
#define I2C0_PP_R   (*((volatile u32 *)0x40020FC0))
 
#define I2C0_PC_R   (*((volatile u32 *)0x40020FC4))
 
#define I2C1_MSA_R   (*((volatile u32 *)0x40021000))
 
#define I2C1_MCS_R   (*((volatile u32 *)0x40021004))
 
#define I2C1_MDR_R   (*((volatile u32 *)0x40021008))
 
#define I2C1_MTPR_R   (*((volatile u32 *)0x4002100C))
 
#define I2C1_MIMR_R   (*((volatile u32 *)0x40021010))
 
#define I2C1_MRIS_R   (*((volatile u32 *)0x40021014))
 
#define I2C1_MMIS_R   (*((volatile u32 *)0x40021018))
 
#define I2C1_MICR_R   (*((volatile u32 *)0x4002101C))
 
#define I2C1_MCR_R   (*((volatile u32 *)0x40021020))
 
#define I2C1_MCLKOCNT_R   (*((volatile u32 *)0x40021024))
 
#define I2C1_MBMON_R   (*((volatile u32 *)0x4002102C))
 
#define I2C1_MCR2_R   (*((volatile u32 *)0x40021038))
 
#define I2C1_SOAR_R   (*((volatile u32 *)0x40021800))
 
#define I2C1_SCSR_R   (*((volatile u32 *)0x40021804))
 
#define I2C1_SDR_R   (*((volatile u32 *)0x40021808))
 
#define I2C1_SIMR_R   (*((volatile u32 *)0x4002180C))
 
#define I2C1_SRIS_R   (*((volatile u32 *)0x40021810))
 
#define I2C1_SMIS_R   (*((volatile u32 *)0x40021814))
 
#define I2C1_SICR_R   (*((volatile u32 *)0x40021818))
 
#define I2C1_SOAR2_R   (*((volatile u32 *)0x4002181C))
 
#define I2C1_SACKCTL_R   (*((volatile u32 *)0x40021820))
 
#define I2C1_PP_R   (*((volatile u32 *)0x40021FC0))
 
#define I2C1_PC_R   (*((volatile u32 *)0x40021FC4))
 
#define I2C2_MSA_R   (*((volatile u32 *)0x40022000))
 
#define I2C2_MCS_R   (*((volatile u32 *)0x40022004))
 
#define I2C2_MDR_R   (*((volatile u32 *)0x40022008))
 
#define I2C2_MTPR_R   (*((volatile u32 *)0x4002200C))
 
#define I2C2_MIMR_R   (*((volatile u32 *)0x40022010))
 
#define I2C2_MRIS_R   (*((volatile u32 *)0x40022014))
 
#define I2C2_MMIS_R   (*((volatile u32 *)0x40022018))
 
#define I2C2_MICR_R   (*((volatile u32 *)0x4002201C))
 
#define I2C2_MCR_R   (*((volatile u32 *)0x40022020))
 
#define I2C2_MCLKOCNT_R   (*((volatile u32 *)0x40022024))
 
#define I2C2_MBMON_R   (*((volatile u32 *)0x4002202C))
 
#define I2C2_MCR2_R   (*((volatile u32 *)0x40022038))
 
#define I2C2_SOAR_R   (*((volatile u32 *)0x40022800))
 
#define I2C2_SCSR_R   (*((volatile u32 *)0x40022804))
 
#define I2C2_SDR_R   (*((volatile u32 *)0x40022808))
 
#define I2C2_SIMR_R   (*((volatile u32 *)0x4002280C))
 
#define I2C2_SRIS_R   (*((volatile u32 *)0x40022810))
 
#define I2C2_SMIS_R   (*((volatile u32 *)0x40022814))
 
#define I2C2_SICR_R   (*((volatile u32 *)0x40022818))
 
#define I2C2_SOAR2_R   (*((volatile u32 *)0x4002281C))
 
#define I2C2_SACKCTL_R   (*((volatile u32 *)0x40022820))
 
#define I2C2_PP_R   (*((volatile u32 *)0x40022FC0))
 
#define I2C2_PC_R   (*((volatile u32 *)0x40022FC4))
 
#define I2C3_MSA_R   (*((volatile u32 *)0x40023000))
 
#define I2C3_MCS_R   (*((volatile u32 *)0x40023004))
 
#define I2C3_MDR_R   (*((volatile u32 *)0x40023008))
 
#define I2C3_MTPR_R   (*((volatile u32 *)0x4002300C))
 
#define I2C3_MIMR_R   (*((volatile u32 *)0x40023010))
 
#define I2C3_MRIS_R   (*((volatile u32 *)0x40023014))
 
#define I2C3_MMIS_R   (*((volatile u32 *)0x40023018))
 
#define I2C3_MICR_R   (*((volatile u32 *)0x4002301C))
 
#define I2C3_MCR_R   (*((volatile u32 *)0x40023020))
 
#define I2C3_MCLKOCNT_R   (*((volatile u32 *)0x40023024))
 
#define I2C3_MBMON_R   (*((volatile u32 *)0x4002302C))
 
#define I2C3_MCR2_R   (*((volatile u32 *)0x40023038))
 
#define I2C3_SOAR_R   (*((volatile u32 *)0x40023800))
 
#define I2C3_SCSR_R   (*((volatile u32 *)0x40023804))
 
#define I2C3_SDR_R   (*((volatile u32 *)0x40023808))
 
#define I2C3_SIMR_R   (*((volatile u32 *)0x4002380C))
 
#define I2C3_SRIS_R   (*((volatile u32 *)0x40023810))
 
#define I2C3_SMIS_R   (*((volatile u32 *)0x40023814))
 
#define I2C3_SICR_R   (*((volatile u32 *)0x40023818))
 
#define I2C3_SOAR2_R   (*((volatile u32 *)0x4002381C))
 
#define I2C3_SACKCTL_R   (*((volatile u32 *)0x40023820))
 
#define I2C3_PP_R   (*((volatile u32 *)0x40023FC0))
 
#define I2C3_PC_R   (*((volatile u32 *)0x40023FC4))
 
#define GPIO_PORTE_DATA_BITS_R   ((volatile u32 *)0x40024000)
 
#define GPIO_PORTE_DATA_R   (*((volatile u32 *)0x400243FC))
 
#define GPIO_PORTE_DIR_R   (*((volatile u32 *)0x40024400))
 
#define GPIO_PORTE_IS_R   (*((volatile u32 *)0x40024404))
 
#define GPIO_PORTE_IBE_R   (*((volatile u32 *)0x40024408))
 
#define GPIO_PORTE_IEV_R   (*((volatile u32 *)0x4002440C))
 
#define GPIO_PORTE_IM_R   (*((volatile u32 *)0x40024410))
 
#define GPIO_PORTE_RIS_R   (*((volatile u32 *)0x40024414))
 
#define GPIO_PORTE_MIS_R   (*((volatile u32 *)0x40024418))
 
#define GPIO_PORTE_ICR_R   (*((volatile u32 *)0x4002441C))
 
#define GPIO_PORTE_AFSEL_R   (*((volatile u32 *)0x40024420))
 
#define GPIO_PORTE_DR2R_R   (*((volatile u32 *)0x40024500))
 
#define GPIO_PORTE_DR4R_R   (*((volatile u32 *)0x40024504))
 
#define GPIO_PORTE_DR8R_R   (*((volatile u32 *)0x40024508))
 
#define GPIO_PORTE_ODR_R   (*((volatile u32 *)0x4002450C))
 
#define GPIO_PORTE_PUR_R   (*((volatile u32 *)0x40024510))
 
#define GPIO_PORTE_PDR_R   (*((volatile u32 *)0x40024514))
 
#define GPIO_PORTE_SLR_R   (*((volatile u32 *)0x40024518))
 
#define GPIO_PORTE_DEN_R   (*((volatile u32 *)0x4002451C))
 
#define GPIO_PORTE_LOCK_R   (*((volatile u32 *)0x40024520))
 
#define GPIO_PORTE_CR_R   (*((volatile u32 *)0x40024524))
 
#define GPIO_PORTE_AMSEL_R   (*((volatile u32 *)0x40024528))
 
#define GPIO_PORTE_PCTL_R   (*((volatile u32 *)0x4002452C))
 
#define GPIO_PORTE_ADCCTL_R   (*((volatile u32 *)0x40024530))
 
#define GPIO_PORTE_DMACTL_R   (*((volatile u32 *)0x40024534))
 
#define GPIO_PORTF_DATA_BITS_R   ((volatile u32 *)0x40025000)
 
#define GPIO_PORTF_DATA_R   (*((volatile u32 *)0x400253FC))
 
#define GPIO_PORTF_DIR_R   (*((volatile u32 *)0x40025400))
 
#define GPIO_PORTF_IS_R   (*((volatile u32 *)0x40025404))
 
#define GPIO_PORTF_IBE_R   (*((volatile u32 *)0x40025408))
 
#define GPIO_PORTF_IEV_R   (*((volatile u32 *)0x4002540C))
 
#define GPIO_PORTF_IM_R   (*((volatile u32 *)0x40025410))
 
#define GPIO_PORTF_RIS_R   (*((volatile u32 *)0x40025414))
 
#define GPIO_PORTF_MIS_R   (*((volatile u32 *)0x40025418))
 
#define GPIO_PORTF_ICR_R   (*((volatile u32 *)0x4002541C))
 
#define GPIO_PORTF_AFSEL_R   (*((volatile u32 *)0x40025420))
 
#define GPIO_PORTF_DR2R_R   (*((volatile u32 *)0x40025500))
 
#define GPIO_PORTF_DR4R_R   (*((volatile u32 *)0x40025504))
 
#define GPIO_PORTF_DR8R_R   (*((volatile u32 *)0x40025508))
 
#define GPIO_PORTF_ODR_R   (*((volatile u32 *)0x4002550C))
 
#define GPIO_PORTF_PUR_R   (*((volatile u32 *)0x40025510))
 
#define GPIO_PORTF_PDR_R   (*((volatile u32 *)0x40025514))
 
#define GPIO_PORTF_SLR_R   (*((volatile u32 *)0x40025518))
 
#define GPIO_PORTF_DEN_R   (*((volatile u32 *)0x4002551C))
 
#define GPIO_PORTF_LOCK_R   (*((volatile u32 *)0x40025520))
 
#define GPIO_PORTF_CR_R   (*((volatile u32 *)0x40025524))
 
#define GPIO_PORTF_AMSEL_R   (*((volatile u32 *)0x40025528))
 
#define GPIO_PORTF_PCTL_R   (*((volatile u32 *)0x4002552C))
 
#define GPIO_PORTF_ADCCTL_R   (*((volatile u32 *)0x40025530))
 
#define GPIO_PORTF_DMACTL_R   (*((volatile u32 *)0x40025534))
 
#define PWM0_CTL_R   (*((volatile u32 *)0x40028000))
 
#define PWM0_SYNC_R   (*((volatile u32 *)0x40028004))
 
#define PWM0_ENABLE_R   (*((volatile u32 *)0x40028008))
 
#define PWM0_INVERT_R   (*((volatile u32 *)0x4002800C))
 
#define PWM0_FAULT_R   (*((volatile u32 *)0x40028010))
 
#define PWM0_INTEN_R   (*((volatile u32 *)0x40028014))
 
#define PWM0_RIS_R   (*((volatile u32 *)0x40028018))
 
#define PWM0_ISC_R   (*((volatile u32 *)0x4002801C))
 
#define PWM0_STATUS_R   (*((volatile u32 *)0x40028020))
 
#define PWM0_FAULTVAL_R   (*((volatile u32 *)0x40028024))
 
#define PWM0_ENUPD_R   (*((volatile u32 *)0x40028028))
 
#define PWM0_0_CTL_R   (*((volatile u32 *)0x40028040))
 
#define PWM0_0_INTEN_R   (*((volatile u32 *)0x40028044))
 
#define PWM0_0_RIS_R   (*((volatile u32 *)0x40028048))
 
#define PWM0_0_ISC_R   (*((volatile u32 *)0x4002804C))
 
#define PWM0_0_LOAD_R   (*((volatile u32 *)0x40028050))
 
#define PWM0_0_COUNT_R   (*((volatile u32 *)0x40028054))
 
#define PWM0_0_CMPA_R   (*((volatile u32 *)0x40028058))
 
#define PWM0_0_CMPB_R   (*((volatile u32 *)0x4002805C))
 
#define PWM0_0_GENA_R   (*((volatile u32 *)0x40028060))
 
#define PWM0_0_GENB_R   (*((volatile u32 *)0x40028064))
 
#define PWM0_0_DBCTL_R   (*((volatile u32 *)0x40028068))
 
#define PWM0_0_DBRISE_R   (*((volatile u32 *)0x4002806C))
 
#define PWM0_0_DBFALL_R   (*((volatile u32 *)0x40028070))
 
#define PWM0_0_FLTSRC0_R   (*((volatile u32 *)0x40028074))
 
#define PWM0_0_FLTSRC1_R   (*((volatile u32 *)0x40028078))
 
#define PWM0_0_MINFLTPER_R   (*((volatile u32 *)0x4002807C))
 
#define PWM0_1_CTL_R   (*((volatile u32 *)0x40028080))
 
#define PWM0_1_INTEN_R   (*((volatile u32 *)0x40028084))
 
#define PWM0_1_RIS_R   (*((volatile u32 *)0x40028088))
 
#define PWM0_1_ISC_R   (*((volatile u32 *)0x4002808C))
 
#define PWM0_1_LOAD_R   (*((volatile u32 *)0x40028090))
 
#define PWM0_1_COUNT_R   (*((volatile u32 *)0x40028094))
 
#define PWM0_1_CMPA_R   (*((volatile u32 *)0x40028098))
 
#define PWM0_1_CMPB_R   (*((volatile u32 *)0x4002809C))
 
#define PWM0_1_GENA_R   (*((volatile u32 *)0x400280A0))
 
#define PWM0_1_GENB_R   (*((volatile u32 *)0x400280A4))
 
#define PWM0_1_DBCTL_R   (*((volatile u32 *)0x400280A8))
 
#define PWM0_1_DBRISE_R   (*((volatile u32 *)0x400280AC))
 
#define PWM0_1_DBFALL_R   (*((volatile u32 *)0x400280B0))
 
#define PWM0_1_FLTSRC0_R   (*((volatile u32 *)0x400280B4))
 
#define PWM0_1_FLTSRC1_R   (*((volatile u32 *)0x400280B8))
 
#define PWM0_1_MINFLTPER_R   (*((volatile u32 *)0x400280BC))
 
#define PWM0_2_CTL_R   (*((volatile u32 *)0x400280C0))
 
#define PWM0_2_INTEN_R   (*((volatile u32 *)0x400280C4))
 
#define PWM0_2_RIS_R   (*((volatile u32 *)0x400280C8))
 
#define PWM0_2_ISC_R   (*((volatile u32 *)0x400280CC))
 
#define PWM0_2_LOAD_R   (*((volatile u32 *)0x400280D0))
 
#define PWM0_2_COUNT_R   (*((volatile u32 *)0x400280D4))
 
#define PWM0_2_CMPA_R   (*((volatile u32 *)0x400280D8))
 
#define PWM0_2_CMPB_R   (*((volatile u32 *)0x400280DC))
 
#define PWM0_2_GENA_R   (*((volatile u32 *)0x400280E0))
 
#define PWM0_2_GENB_R   (*((volatile u32 *)0x400280E4))
 
#define PWM0_2_DBCTL_R   (*((volatile u32 *)0x400280E8))
 
#define PWM0_2_DBRISE_R   (*((volatile u32 *)0x400280EC))
 
#define PWM0_2_DBFALL_R   (*((volatile u32 *)0x400280F0))
 
#define PWM0_2_FLTSRC0_R   (*((volatile u32 *)0x400280F4))
 
#define PWM0_2_FLTSRC1_R   (*((volatile u32 *)0x400280F8))
 
#define PWM0_2_MINFLTPER_R   (*((volatile u32 *)0x400280FC))
 
#define PWM0_3_CTL_R   (*((volatile u32 *)0x40028100))
 
#define PWM0_3_INTEN_R   (*((volatile u32 *)0x40028104))
 
#define PWM0_3_RIS_R   (*((volatile u32 *)0x40028108))
 
#define PWM0_3_ISC_R   (*((volatile u32 *)0x4002810C))
 
#define PWM0_3_LOAD_R   (*((volatile u32 *)0x40028110))
 
#define PWM0_3_COUNT_R   (*((volatile u32 *)0x40028114))
 
#define PWM0_3_CMPA_R   (*((volatile u32 *)0x40028118))
 
#define PWM0_3_CMPB_R   (*((volatile u32 *)0x4002811C))
 
#define PWM0_3_GENA_R   (*((volatile u32 *)0x40028120))
 
#define PWM0_3_GENB_R   (*((volatile u32 *)0x40028124))
 
#define PWM0_3_DBCTL_R   (*((volatile u32 *)0x40028128))
 
#define PWM0_3_DBRISE_R   (*((volatile u32 *)0x4002812C))
 
#define PWM0_3_DBFALL_R   (*((volatile u32 *)0x40028130))
 
#define PWM0_3_FLTSRC0_R   (*((volatile u32 *)0x40028134))
 
#define PWM0_3_FLTSRC1_R   (*((volatile u32 *)0x40028138))
 
#define PWM0_3_MINFLTPER_R   (*((volatile u32 *)0x4002813C))
 
#define PWM0_0_FLTSEN_R   (*((volatile u32 *)0x40028800))
 
#define PWM0_0_FLTSTAT0_R   (*((volatile u32 *)0x40028804))
 
#define PWM0_0_FLTSTAT1_R   (*((volatile u32 *)0x40028808))
 
#define PWM0_1_FLTSEN_R   (*((volatile u32 *)0x40028880))
 
#define PWM0_1_FLTSTAT0_R   (*((volatile u32 *)0x40028884))
 
#define PWM0_1_FLTSTAT1_R   (*((volatile u32 *)0x40028888))
 
#define PWM0_2_FLTSTAT0_R   (*((volatile u32 *)0x40028904))
 
#define PWM0_2_FLTSTAT1_R   (*((volatile u32 *)0x40028908))
 
#define PWM0_3_FLTSTAT0_R   (*((volatile u32 *)0x40028984))
 
#define PWM0_3_FLTSTAT1_R   (*((volatile u32 *)0x40028988))
 
#define PWM0_PP_R   (*((volatile u32 *)0x40028FC0))
 
#define PWM1_CTL_R   (*((volatile u32 *)0x40029000))
 
#define PWM1_SYNC_R   (*((volatile u32 *)0x40029004))
 
#define PWM1_ENABLE_R   (*((volatile u32 *)0x40029008))
 
#define PWM1_INVERT_R   (*((volatile u32 *)0x4002900C))
 
#define PWM1_FAULT_R   (*((volatile u32 *)0x40029010))
 
#define PWM1_INTEN_R   (*((volatile u32 *)0x40029014))
 
#define PWM1_RIS_R   (*((volatile u32 *)0x40029018))
 
#define PWM1_ISC_R   (*((volatile u32 *)0x4002901C))
 
#define PWM1_STATUS_R   (*((volatile u32 *)0x40029020))
 
#define PWM1_FAULTVAL_R   (*((volatile u32 *)0x40029024))
 
#define PWM1_ENUPD_R   (*((volatile u32 *)0x40029028))
 
#define PWM1_0_CTL_R   (*((volatile u32 *)0x40029040))
 
#define PWM1_0_INTEN_R   (*((volatile u32 *)0x40029044))
 
#define PWM1_0_RIS_R   (*((volatile u32 *)0x40029048))
 
#define PWM1_0_ISC_R   (*((volatile u32 *)0x4002904C))
 
#define PWM1_0_LOAD_R   (*((volatile u32 *)0x40029050))
 
#define PWM1_0_COUNT_R   (*((volatile u32 *)0x40029054))
 
#define PWM1_0_CMPA_R   (*((volatile u32 *)0x40029058))
 
#define PWM1_0_CMPB_R   (*((volatile u32 *)0x4002905C))
 
#define PWM1_0_GENA_R   (*((volatile u32 *)0x40029060))
 
#define PWM1_0_GENB_R   (*((volatile u32 *)0x40029064))
 
#define PWM1_0_DBCTL_R   (*((volatile u32 *)0x40029068))
 
#define PWM1_0_DBRISE_R   (*((volatile u32 *)0x4002906C))
 
#define PWM1_0_DBFALL_R   (*((volatile u32 *)0x40029070))
 
#define PWM1_0_FLTSRC0_R   (*((volatile u32 *)0x40029074))
 
#define PWM1_0_FLTSRC1_R   (*((volatile u32 *)0x40029078))
 
#define PWM1_0_MINFLTPER_R   (*((volatile u32 *)0x4002907C))
 
#define PWM1_1_CTL_R   (*((volatile u32 *)0x40029080))
 
#define PWM1_1_INTEN_R   (*((volatile u32 *)0x40029084))
 
#define PWM1_1_RIS_R   (*((volatile u32 *)0x40029088))
 
#define PWM1_1_ISC_R   (*((volatile u32 *)0x4002908C))
 
#define PWM1_1_LOAD_R   (*((volatile u32 *)0x40029090))
 
#define PWM1_1_COUNT_R   (*((volatile u32 *)0x40029094))
 
#define PWM1_1_CMPA_R   (*((volatile u32 *)0x40029098))
 
#define PWM1_1_CMPB_R   (*((volatile u32 *)0x4002909C))
 
#define PWM1_1_GENA_R   (*((volatile u32 *)0x400290A0))
 
#define PWM1_1_GENB_R   (*((volatile u32 *)0x400290A4))
 
#define PWM1_1_DBCTL_R   (*((volatile u32 *)0x400290A8))
 
#define PWM1_1_DBRISE_R   (*((volatile u32 *)0x400290AC))
 
#define PWM1_1_DBFALL_R   (*((volatile u32 *)0x400290B0))
 
#define PWM1_1_FLTSRC0_R   (*((volatile u32 *)0x400290B4))
 
#define PWM1_1_FLTSRC1_R   (*((volatile u32 *)0x400290B8))
 
#define PWM1_1_MINFLTPER_R   (*((volatile u32 *)0x400290BC))
 
#define PWM1_2_CTL_R   (*((volatile u32 *)0x400290C0))
 
#define PWM1_2_INTEN_R   (*((volatile u32 *)0x400290C4))
 
#define PWM1_2_RIS_R   (*((volatile u32 *)0x400290C8))
 
#define PWM1_2_ISC_R   (*((volatile u32 *)0x400290CC))
 
#define PWM1_2_LOAD_R   (*((volatile u32 *)0x400290D0))
 
#define PWM1_2_COUNT_R   (*((volatile u32 *)0x400290D4))
 
#define PWM1_2_CMPA_R   (*((volatile u32 *)0x400290D8))
 
#define PWM1_2_CMPB_R   (*((volatile u32 *)0x400290DC))
 
#define PWM1_2_GENA_R   (*((volatile u32 *)0x400290E0))
 
#define PWM1_2_GENB_R   (*((volatile u32 *)0x400290E4))
 
#define PWM1_2_DBCTL_R   (*((volatile u32 *)0x400290E8))
 
#define PWM1_2_DBRISE_R   (*((volatile u32 *)0x400290EC))
 
#define PWM1_2_DBFALL_R   (*((volatile u32 *)0x400290F0))
 
#define PWM1_2_FLTSRC0_R   (*((volatile u32 *)0x400290F4))
 
#define PWM1_2_FLTSRC1_R   (*((volatile u32 *)0x400290F8))
 
#define PWM1_2_MINFLTPER_R   (*((volatile u32 *)0x400290FC))
 
#define PWM1_3_CTL_R   (*((volatile u32 *)0x40029100))
 
#define PWM1_3_INTEN_R   (*((volatile u32 *)0x40029104))
 
#define PWM1_3_RIS_R   (*((volatile u32 *)0x40029108))
 
#define PWM1_3_ISC_R   (*((volatile u32 *)0x4002910C))
 
#define PWM1_3_LOAD_R   (*((volatile u32 *)0x40029110))
 
#define PWM1_3_COUNT_R   (*((volatile u32 *)0x40029114))
 
#define PWM1_3_CMPA_R   (*((volatile u32 *)0x40029118))
 
#define PWM1_3_CMPB_R   (*((volatile u32 *)0x4002911C))
 
#define PWM1_3_GENA_R   (*((volatile u32 *)0x40029120))
 
#define PWM1_3_GENB_R   (*((volatile u32 *)0x40029124))
 
#define PWM1_3_DBCTL_R   (*((volatile u32 *)0x40029128))
 
#define PWM1_3_DBRISE_R   (*((volatile u32 *)0x4002912C))
 
#define PWM1_3_DBFALL_R   (*((volatile u32 *)0x40029130))
 
#define PWM1_3_FLTSRC0_R   (*((volatile u32 *)0x40029134))
 
#define PWM1_3_FLTSRC1_R   (*((volatile u32 *)0x40029138))
 
#define PWM1_3_MINFLTPER_R   (*((volatile u32 *)0x4002913C))
 
#define PWM1_0_FLTSEN_R   (*((volatile u32 *)0x40029800))
 
#define PWM1_0_FLTSTAT0_R   (*((volatile u32 *)0x40029804))
 
#define PWM1_0_FLTSTAT1_R   (*((volatile u32 *)0x40029808))
 
#define PWM1_1_FLTSEN_R   (*((volatile u32 *)0x40029880))
 
#define PWM1_1_FLTSTAT0_R   (*((volatile u32 *)0x40029884))
 
#define PWM1_1_FLTSTAT1_R   (*((volatile u32 *)0x40029888))
 
#define PWM1_2_FLTSTAT0_R   (*((volatile u32 *)0x40029904))
 
#define PWM1_2_FLTSTAT1_R   (*((volatile u32 *)0x40029908))
 
#define PWM1_3_FLTSTAT0_R   (*((volatile u32 *)0x40029984))
 
#define PWM1_3_FLTSTAT1_R   (*((volatile u32 *)0x40029988))
 
#define PWM1_PP_R   (*((volatile u32 *)0x40029FC0))
 
#define QEI0_CTL_R   (*((volatile u32 *)0x4002C000))
 
#define QEI0_STAT_R   (*((volatile u32 *)0x4002C004))
 
#define QEI0_POS_R   (*((volatile u32 *)0x4002C008))
 
#define QEI0_MAXPOS_R   (*((volatile u32 *)0x4002C00C))
 
#define QEI0_LOAD_R   (*((volatile u32 *)0x4002C010))
 
#define QEI0_TIME_R   (*((volatile u32 *)0x4002C014))
 
#define QEI0_COUNT_R   (*((volatile u32 *)0x4002C018))
 
#define QEI0_SPEED_R   (*((volatile u32 *)0x4002C01C))
 
#define QEI0_INTEN_R   (*((volatile u32 *)0x4002C020))
 
#define QEI0_RIS_R   (*((volatile u32 *)0x4002C024))
 
#define QEI0_ISC_R   (*((volatile u32 *)0x4002C028))
 
#define QEI1_CTL_R   (*((volatile u32 *)0x4002D000))
 
#define QEI1_STAT_R   (*((volatile u32 *)0x4002D004))
 
#define QEI1_POS_R   (*((volatile u32 *)0x4002D008))
 
#define QEI1_MAXPOS_R   (*((volatile u32 *)0x4002D00C))
 
#define QEI1_LOAD_R   (*((volatile u32 *)0x4002D010))
 
#define QEI1_TIME_R   (*((volatile u32 *)0x4002D014))
 
#define QEI1_COUNT_R   (*((volatile u32 *)0x4002D018))
 
#define QEI1_SPEED_R   (*((volatile u32 *)0x4002D01C))
 
#define QEI1_INTEN_R   (*((volatile u32 *)0x4002D020))
 
#define QEI1_RIS_R   (*((volatile u32 *)0x4002D024))
 
#define QEI1_ISC_R   (*((volatile u32 *)0x4002D028))
 
#define TIMER0_CFG_R   (*((volatile u32 *)0x40030000))
 
#define TIMER0_TAMR_R   (*((volatile u32 *)0x40030004))
 
#define TIMER0_TBMR_R   (*((volatile u32 *)0x40030008))
 
#define TIMER0_CTL_R   (*((volatile u32 *)0x4003000C))
 
#define TIMER0_SYNC_R   (*((volatile u32 *)0x40030010))
 
#define TIMER0_IMR_R   (*((volatile u32 *)0x40030018))
 
#define TIMER0_RIS_R   (*((volatile u32 *)0x4003001C))
 
#define TIMER0_MIS_R   (*((volatile u32 *)0x40030020))
 
#define TIMER0_ICR_R   (*((volatile u32 *)0x40030024))
 
#define TIMER0_TAILR_R   (*((volatile u32 *)0x40030028))
 
#define TIMER0_TBILR_R   (*((volatile u32 *)0x4003002C))
 
#define TIMER0_TAMATCHR_R   (*((volatile u32 *)0x40030030))
 
#define TIMER0_TBMATCHR_R   (*((volatile u32 *)0x40030034))
 
#define TIMER0_TAPR_R   (*((volatile u32 *)0x40030038))
 
#define TIMER0_TBPR_R   (*((volatile u32 *)0x4003003C))
 
#define TIMER0_TAPMR_R   (*((volatile u32 *)0x40030040))
 
#define TIMER0_TBPMR_R   (*((volatile u32 *)0x40030044))
 
#define TIMER0_TAR_R   (*((volatile u32 *)0x40030048))
 
#define TIMER0_TBR_R   (*((volatile u32 *)0x4003004C))
 
#define TIMER0_TAV_R   (*((volatile u32 *)0x40030050))
 
#define TIMER0_TBV_R   (*((volatile u32 *)0x40030054))
 
#define TIMER0_RTCPD_R   (*((volatile u32 *)0x40030058))
 
#define TIMER0_TAPS_R   (*((volatile u32 *)0x4003005C))
 
#define TIMER0_TBPS_R   (*((volatile u32 *)0x40030060))
 
#define TIMER0_TAPV_R   (*((volatile u32 *)0x40030064))
 
#define TIMER0_TBPV_R   (*((volatile u32 *)0x40030068))
 
#define TIMER0_PP_R   (*((volatile u32 *)0x40030FC0))
 
#define TIMER1_CFG_R   (*((volatile u32 *)0x40031000))
 
#define TIMER1_TAMR_R   (*((volatile u32 *)0x40031004))
 
#define TIMER1_TBMR_R   (*((volatile u32 *)0x40031008))
 
#define TIMER1_CTL_R   (*((volatile u32 *)0x4003100C))
 
#define TIMER1_SYNC_R   (*((volatile u32 *)0x40031010))
 
#define TIMER1_IMR_R   (*((volatile u32 *)0x40031018))
 
#define TIMER1_RIS_R   (*((volatile u32 *)0x4003101C))
 
#define TIMER1_MIS_R   (*((volatile u32 *)0x40031020))
 
#define TIMER1_ICR_R   (*((volatile u32 *)0x40031024))
 
#define TIMER1_TAILR_R   (*((volatile u32 *)0x40031028))
 
#define TIMER1_TBILR_R   (*((volatile u32 *)0x4003102C))
 
#define TIMER1_TAMATCHR_R   (*((volatile u32 *)0x40031030))
 
#define TIMER1_TBMATCHR_R   (*((volatile u32 *)0x40031034))
 
#define TIMER1_TAPR_R   (*((volatile u32 *)0x40031038))
 
#define TIMER1_TBPR_R   (*((volatile u32 *)0x4003103C))
 
#define TIMER1_TAPMR_R   (*((volatile u32 *)0x40031040))
 
#define TIMER1_TBPMR_R   (*((volatile u32 *)0x40031044))
 
#define TIMER1_TAR_R   (*((volatile u32 *)0x40031048))
 
#define TIMER1_TBR_R   (*((volatile u32 *)0x4003104C))
 
#define TIMER1_TAV_R   (*((volatile u32 *)0x40031050))
 
#define TIMER1_TBV_R   (*((volatile u32 *)0x40031054))
 
#define TIMER1_RTCPD_R   (*((volatile u32 *)0x40031058))
 
#define TIMER1_TAPS_R   (*((volatile u32 *)0x4003105C))
 
#define TIMER1_TBPS_R   (*((volatile u32 *)0x40031060))
 
#define TIMER1_TAPV_R   (*((volatile u32 *)0x40031064))
 
#define TIMER1_TBPV_R   (*((volatile u32 *)0x40031068))
 
#define TIMER1_PP_R   (*((volatile u32 *)0x40031FC0))
 
#define TIMER2_CFG_R   (*((volatile u32 *)0x40032000))
 
#define TIMER2_TAMR_R   (*((volatile u32 *)0x40032004))
 
#define TIMER2_TBMR_R   (*((volatile u32 *)0x40032008))
 
#define TIMER2_CTL_R   (*((volatile u32 *)0x4003200C))
 
#define TIMER2_SYNC_R   (*((volatile u32 *)0x40032010))
 
#define TIMER2_IMR_R   (*((volatile u32 *)0x40032018))
 
#define TIMER2_RIS_R   (*((volatile u32 *)0x4003201C))
 
#define TIMER2_MIS_R   (*((volatile u32 *)0x40032020))
 
#define TIMER2_ICR_R   (*((volatile u32 *)0x40032024))
 
#define TIMER2_TAILR_R   (*((volatile u32 *)0x40032028))
 
#define TIMER2_TBILR_R   (*((volatile u32 *)0x4003202C))
 
#define TIMER2_TAMATCHR_R   (*((volatile u32 *)0x40032030))
 
#define TIMER2_TBMATCHR_R   (*((volatile u32 *)0x40032034))
 
#define TIMER2_TAPR_R   (*((volatile u32 *)0x40032038))
 
#define TIMER2_TBPR_R   (*((volatile u32 *)0x4003203C))
 
#define TIMER2_TAPMR_R   (*((volatile u32 *)0x40032040))
 
#define TIMER2_TBPMR_R   (*((volatile u32 *)0x40032044))
 
#define TIMER2_TAR_R   (*((volatile u32 *)0x40032048))
 
#define TIMER2_TBR_R   (*((volatile u32 *)0x4003204C))
 
#define TIMER2_TAV_R   (*((volatile u32 *)0x40032050))
 
#define TIMER2_TBV_R   (*((volatile u32 *)0x40032054))
 
#define TIMER2_RTCPD_R   (*((volatile u32 *)0x40032058))
 
#define TIMER2_TAPS_R   (*((volatile u32 *)0x4003205C))
 
#define TIMER2_TBPS_R   (*((volatile u32 *)0x40032060))
 
#define TIMER2_TAPV_R   (*((volatile u32 *)0x40032064))
 
#define TIMER2_TBPV_R   (*((volatile u32 *)0x40032068))
 
#define TIMER2_PP_R   (*((volatile u32 *)0x40032FC0))
 
#define TIMER3_CFG_R   (*((volatile u32 *)0x40033000))
 
#define TIMER3_TAMR_R   (*((volatile u32 *)0x40033004))
 
#define TIMER3_TBMR_R   (*((volatile u32 *)0x40033008))
 
#define TIMER3_CTL_R   (*((volatile u32 *)0x4003300C))
 
#define TIMER3_SYNC_R   (*((volatile u32 *)0x40033010))
 
#define TIMER3_IMR_R   (*((volatile u32 *)0x40033018))
 
#define TIMER3_RIS_R   (*((volatile u32 *)0x4003301C))
 
#define TIMER3_MIS_R   (*((volatile u32 *)0x40033020))
 
#define TIMER3_ICR_R   (*((volatile u32 *)0x40033024))
 
#define TIMER3_TAILR_R   (*((volatile u32 *)0x40033028))
 
#define TIMER3_TBILR_R   (*((volatile u32 *)0x4003302C))
 
#define TIMER3_TAMATCHR_R   (*((volatile u32 *)0x40033030))
 
#define TIMER3_TBMATCHR_R   (*((volatile u32 *)0x40033034))
 
#define TIMER3_TAPR_R   (*((volatile u32 *)0x40033038))
 
#define TIMER3_TBPR_R   (*((volatile u32 *)0x4003303C))
 
#define TIMER3_TAPMR_R   (*((volatile u32 *)0x40033040))
 
#define TIMER3_TBPMR_R   (*((volatile u32 *)0x40033044))
 
#define TIMER3_TAR_R   (*((volatile u32 *)0x40033048))
 
#define TIMER3_TBR_R   (*((volatile u32 *)0x4003304C))
 
#define TIMER3_TAV_R   (*((volatile u32 *)0x40033050))
 
#define TIMER3_TBV_R   (*((volatile u32 *)0x40033054))
 
#define TIMER3_RTCPD_R   (*((volatile u32 *)0x40033058))
 
#define TIMER3_TAPS_R   (*((volatile u32 *)0x4003305C))
 
#define TIMER3_TBPS_R   (*((volatile u32 *)0x40033060))
 
#define TIMER3_TAPV_R   (*((volatile u32 *)0x40033064))
 
#define TIMER3_TBPV_R   (*((volatile u32 *)0x40033068))
 
#define TIMER3_PP_R   (*((volatile u32 *)0x40033FC0))
 
#define TIMER4_CFG_R   (*((volatile u32 *)0x40034000))
 
#define TIMER4_TAMR_R   (*((volatile u32 *)0x40034004))
 
#define TIMER4_TBMR_R   (*((volatile u32 *)0x40034008))
 
#define TIMER4_CTL_R   (*((volatile u32 *)0x4003400C))
 
#define TIMER4_SYNC_R   (*((volatile u32 *)0x40034010))
 
#define TIMER4_IMR_R   (*((volatile u32 *)0x40034018))
 
#define TIMER4_RIS_R   (*((volatile u32 *)0x4003401C))
 
#define TIMER4_MIS_R   (*((volatile u32 *)0x40034020))
 
#define TIMER4_ICR_R   (*((volatile u32 *)0x40034024))
 
#define TIMER4_TAILR_R   (*((volatile u32 *)0x40034028))
 
#define TIMER4_TBILR_R   (*((volatile u32 *)0x4003402C))
 
#define TIMER4_TAMATCHR_R   (*((volatile u32 *)0x40034030))
 
#define TIMER4_TBMATCHR_R   (*((volatile u32 *)0x40034034))
 
#define TIMER4_TAPR_R   (*((volatile u32 *)0x40034038))
 
#define TIMER4_TBPR_R   (*((volatile u32 *)0x4003403C))
 
#define TIMER4_TAPMR_R   (*((volatile u32 *)0x40034040))
 
#define TIMER4_TBPMR_R   (*((volatile u32 *)0x40034044))
 
#define TIMER4_TAR_R   (*((volatile u32 *)0x40034048))
 
#define TIMER4_TBR_R   (*((volatile u32 *)0x4003404C))
 
#define TIMER4_TAV_R   (*((volatile u32 *)0x40034050))
 
#define TIMER4_TBV_R   (*((volatile u32 *)0x40034054))
 
#define TIMER4_RTCPD_R   (*((volatile u32 *)0x40034058))
 
#define TIMER4_TAPS_R   (*((volatile u32 *)0x4003405C))
 
#define TIMER4_TBPS_R   (*((volatile u32 *)0x40034060))
 
#define TIMER4_TAPV_R   (*((volatile u32 *)0x40034064))
 
#define TIMER4_TBPV_R   (*((volatile u32 *)0x40034068))
 
#define TIMER4_PP_R   (*((volatile u32 *)0x40034FC0))
 
#define TIMER5_CFG_R   (*((volatile u32 *)0x40035000))
 
#define TIMER5_TAMR_R   (*((volatile u32 *)0x40035004))
 
#define TIMER5_TBMR_R   (*((volatile u32 *)0x40035008))
 
#define TIMER5_CTL_R   (*((volatile u32 *)0x4003500C))
 
#define TIMER5_SYNC_R   (*((volatile u32 *)0x40035010))
 
#define TIMER5_IMR_R   (*((volatile u32 *)0x40035018))
 
#define TIMER5_RIS_R   (*((volatile u32 *)0x4003501C))
 
#define TIMER5_MIS_R   (*((volatile u32 *)0x40035020))
 
#define TIMER5_ICR_R   (*((volatile u32 *)0x40035024))
 
#define TIMER5_TAILR_R   (*((volatile u32 *)0x40035028))
 
#define TIMER5_TBILR_R   (*((volatile u32 *)0x4003502C))
 
#define TIMER5_TAMATCHR_R   (*((volatile u32 *)0x40035030))
 
#define TIMER5_TBMATCHR_R   (*((volatile u32 *)0x40035034))
 
#define TIMER5_TAPR_R   (*((volatile u32 *)0x40035038))
 
#define TIMER5_TBPR_R   (*((volatile u32 *)0x4003503C))
 
#define TIMER5_TAPMR_R   (*((volatile u32 *)0x40035040))
 
#define TIMER5_TBPMR_R   (*((volatile u32 *)0x40035044))
 
#define TIMER5_TAR_R   (*((volatile u32 *)0x40035048))
 
#define TIMER5_TBR_R   (*((volatile u32 *)0x4003504C))
 
#define TIMER5_TAV_R   (*((volatile u32 *)0x40035050))
 
#define TIMER5_TBV_R   (*((volatile u32 *)0x40035054))
 
#define TIMER5_RTCPD_R   (*((volatile u32 *)0x40035058))
 
#define TIMER5_TAPS_R   (*((volatile u32 *)0x4003505C))
 
#define TIMER5_TBPS_R   (*((volatile u32 *)0x40035060))
 
#define TIMER5_TAPV_R   (*((volatile u32 *)0x40035064))
 
#define TIMER5_TBPV_R   (*((volatile u32 *)0x40035068))
 
#define TIMER5_PP_R   (*((volatile u32 *)0x40035FC0))
 
#define WTIMER0_CFG_R   (*((volatile u32 *)0x40036000))
 
#define WTIMER0_TAMR_R   (*((volatile u32 *)0x40036004))
 
#define WTIMER0_TBMR_R   (*((volatile u32 *)0x40036008))
 
#define WTIMER0_CTL_R   (*((volatile u32 *)0x4003600C))
 
#define WTIMER0_SYNC_R   (*((volatile u32 *)0x40036010))
 
#define WTIMER0_IMR_R   (*((volatile u32 *)0x40036018))
 
#define WTIMER0_RIS_R   (*((volatile u32 *)0x4003601C))
 
#define WTIMER0_MIS_R   (*((volatile u32 *)0x40036020))
 
#define WTIMER0_ICR_R   (*((volatile u32 *)0x40036024))
 
#define WTIMER0_TAILR_R   (*((volatile u32 *)0x40036028))
 
#define WTIMER0_TBILR_R   (*((volatile u32 *)0x4003602C))
 
#define WTIMER0_TAMATCHR_R   (*((volatile u32 *)0x40036030))
 
#define WTIMER0_TBMATCHR_R   (*((volatile u32 *)0x40036034))
 
#define WTIMER0_TAPR_R   (*((volatile u32 *)0x40036038))
 
#define WTIMER0_TBPR_R   (*((volatile u32 *)0x4003603C))
 
#define WTIMER0_TAPMR_R   (*((volatile u32 *)0x40036040))
 
#define WTIMER0_TBPMR_R   (*((volatile u32 *)0x40036044))
 
#define WTIMER0_TAR_R   (*((volatile u32 *)0x40036048))
 
#define WTIMER0_TBR_R   (*((volatile u32 *)0x4003604C))
 
#define WTIMER0_TAV_R   (*((volatile u32 *)0x40036050))
 
#define WTIMER0_TBV_R   (*((volatile u32 *)0x40036054))
 
#define WTIMER0_RTCPD_R   (*((volatile u32 *)0x40036058))
 
#define WTIMER0_TAPS_R   (*((volatile u32 *)0x4003605C))
 
#define WTIMER0_TBPS_R   (*((volatile u32 *)0x40036060))
 
#define WTIMER0_TAPV_R   (*((volatile u32 *)0x40036064))
 
#define WTIMER0_TBPV_R   (*((volatile u32 *)0x40036068))
 
#define WTIMER0_PP_R   (*((volatile u32 *)0x40036FC0))
 
#define WTIMER1_CFG_R   (*((volatile u32 *)0x40037000))
 
#define WTIMER1_TAMR_R   (*((volatile u32 *)0x40037004))
 
#define WTIMER1_TBMR_R   (*((volatile u32 *)0x40037008))
 
#define WTIMER1_CTL_R   (*((volatile u32 *)0x4003700C))
 
#define WTIMER1_SYNC_R   (*((volatile u32 *)0x40037010))
 
#define WTIMER1_IMR_R   (*((volatile u32 *)0x40037018))
 
#define WTIMER1_RIS_R   (*((volatile u32 *)0x4003701C))
 
#define WTIMER1_MIS_R   (*((volatile u32 *)0x40037020))
 
#define WTIMER1_ICR_R   (*((volatile u32 *)0x40037024))
 
#define WTIMER1_TAILR_R   (*((volatile u32 *)0x40037028))
 
#define WTIMER1_TBILR_R   (*((volatile u32 *)0x4003702C))
 
#define WTIMER1_TAMATCHR_R   (*((volatile u32 *)0x40037030))
 
#define WTIMER1_TBMATCHR_R   (*((volatile u32 *)0x40037034))
 
#define WTIMER1_TAPR_R   (*((volatile u32 *)0x40037038))
 
#define WTIMER1_TBPR_R   (*((volatile u32 *)0x4003703C))
 
#define WTIMER1_TAPMR_R   (*((volatile u32 *)0x40037040))
 
#define WTIMER1_TBPMR_R   (*((volatile u32 *)0x40037044))
 
#define WTIMER1_TAR_R   (*((volatile u32 *)0x40037048))
 
#define WTIMER1_TBR_R   (*((volatile u32 *)0x4003704C))
 
#define WTIMER1_TAV_R   (*((volatile u32 *)0x40037050))
 
#define WTIMER1_TBV_R   (*((volatile u32 *)0x40037054))
 
#define WTIMER1_RTCPD_R   (*((volatile u32 *)0x40037058))
 
#define WTIMER1_TAPS_R   (*((volatile u32 *)0x4003705C))
 
#define WTIMER1_TBPS_R   (*((volatile u32 *)0x40037060))
 
#define WTIMER1_TAPV_R   (*((volatile u32 *)0x40037064))
 
#define WTIMER1_TBPV_R   (*((volatile u32 *)0x40037068))
 
#define WTIMER1_PP_R   (*((volatile u32 *)0x40037FC0))
 
#define ADC0_ACTSS_R   (*((volatile u32 *)0x40038000))
 
#define ADC0_RIS_R   (*((volatile u32 *)0x40038004))
 
#define ADC0_IM_R   (*((volatile u32 *)0x40038008))
 
#define ADC0_ISC_R   (*((volatile u32 *)0x4003800C))
 
#define ADC0_OSTAT_R   (*((volatile u32 *)0x40038010))
 
#define ADC0_EMUX_R   (*((volatile u32 *)0x40038014))
 
#define ADC0_USTAT_R   (*((volatile u32 *)0x40038018))
 
#define ADC0_TSSEL_R   (*((volatile u32 *)0x4003801C))
 
#define ADC0_SSPRI_R   (*((volatile u32 *)0x40038020))
 
#define ADC0_SPC_R   (*((volatile u32 *)0x40038024))
 
#define ADC0_PSSI_R   (*((volatile u32 *)0x40038028))
 
#define ADC0_SAC_R   (*((volatile u32 *)0x40038030))
 
#define ADC0_DCISC_R   (*((volatile u32 *)0x40038034))
 
#define ADC0_CTL_R   (*((volatile u32 *)0x40038038))
 
#define ADC0_SSMUX0_R   (*((volatile u32 *)0x40038040))
 
#define ADC0_SSCTL0_R   (*((volatile u32 *)0x40038044))
 
#define ADC0_SSFIFO0_R   (*((volatile u32 *)0x40038048))
 
#define ADC0_SSFSTAT0_R   (*((volatile u32 *)0x4003804C))
 
#define ADC0_SSOP0_R   (*((volatile u32 *)0x40038050))
 
#define ADC0_SSDC0_R   (*((volatile u32 *)0x40038054))
 
#define ADC0_SSMUX1_R   (*((volatile u32 *)0x40038060))
 
#define ADC0_SSCTL1_R   (*((volatile u32 *)0x40038064))
 
#define ADC0_SSFIFO1_R   (*((volatile u32 *)0x40038068))
 
#define ADC0_SSFSTAT1_R   (*((volatile u32 *)0x4003806C))
 
#define ADC0_SSOP1_R   (*((volatile u32 *)0x40038070))
 
#define ADC0_SSDC1_R   (*((volatile u32 *)0x40038074))
 
#define ADC0_SSMUX2_R   (*((volatile u32 *)0x40038080))
 
#define ADC0_SSCTL2_R   (*((volatile u32 *)0x40038084))
 
#define ADC0_SSFIFO2_R   (*((volatile u32 *)0x40038088))
 
#define ADC0_SSFSTAT2_R   (*((volatile u32 *)0x4003808C))
 
#define ADC0_SSOP2_R   (*((volatile u32 *)0x40038090))
 
#define ADC0_SSDC2_R   (*((volatile u32 *)0x40038094))
 
#define ADC0_SSMUX3_R   (*((volatile u32 *)0x400380A0))
 
#define ADC0_SSCTL3_R   (*((volatile u32 *)0x400380A4))
 
#define ADC0_SSFIFO3_R   (*((volatile u32 *)0x400380A8))
 
#define ADC0_SSFSTAT3_R   (*((volatile u32 *)0x400380AC))
 
#define ADC0_SSOP3_R   (*((volatile u32 *)0x400380B0))
 
#define ADC0_SSDC3_R   (*((volatile u32 *)0x400380B4))
 
#define ADC0_DCRIC_R   (*((volatile u32 *)0x40038D00))
 
#define ADC0_DCCTL0_R   (*((volatile u32 *)0x40038E00))
 
#define ADC0_DCCTL1_R   (*((volatile u32 *)0x40038E04))
 
#define ADC0_DCCTL2_R   (*((volatile u32 *)0x40038E08))
 
#define ADC0_DCCTL3_R   (*((volatile u32 *)0x40038E0C))
 
#define ADC0_DCCTL4_R   (*((volatile u32 *)0x40038E10))
 
#define ADC0_DCCTL5_R   (*((volatile u32 *)0x40038E14))
 
#define ADC0_DCCTL6_R   (*((volatile u32 *)0x40038E18))
 
#define ADC0_DCCTL7_R   (*((volatile u32 *)0x40038E1C))
 
#define ADC0_DCCMP0_R   (*((volatile u32 *)0x40038E40))
 
#define ADC0_DCCMP1_R   (*((volatile u32 *)0x40038E44))
 
#define ADC0_DCCMP2_R   (*((volatile u32 *)0x40038E48))
 
#define ADC0_DCCMP3_R   (*((volatile u32 *)0x40038E4C))
 
#define ADC0_DCCMP4_R   (*((volatile u32 *)0x40038E50))
 
#define ADC0_DCCMP5_R   (*((volatile u32 *)0x40038E54))
 
#define ADC0_DCCMP6_R   (*((volatile u32 *)0x40038E58))
 
#define ADC0_DCCMP7_R   (*((volatile u32 *)0x40038E5C))
 
#define ADC0_PP_R   (*((volatile u32 *)0x40038FC0))
 
#define ADC0_PC_R   (*((volatile u32 *)0x40038FC4))
 
#define ADC0_CC_R   (*((volatile u32 *)0x40038FC8))
 
#define ADC1_ACTSS_R   (*((volatile u32 *)0x40039000))
 
#define ADC1_RIS_R   (*((volatile u32 *)0x40039004))
 
#define ADC1_IM_R   (*((volatile u32 *)0x40039008))
 
#define ADC1_ISC_R   (*((volatile u32 *)0x4003900C))
 
#define ADC1_OSTAT_R   (*((volatile u32 *)0x40039010))
 
#define ADC1_EMUX_R   (*((volatile u32 *)0x40039014))
 
#define ADC1_USTAT_R   (*((volatile u32 *)0x40039018))
 
#define ADC1_TSSEL_R   (*((volatile u32 *)0x4003901C))
 
#define ADC1_SSPRI_R   (*((volatile u32 *)0x40039020))
 
#define ADC1_SPC_R   (*((volatile u32 *)0x40039024))
 
#define ADC1_PSSI_R   (*((volatile u32 *)0x40039028))
 
#define ADC1_SAC_R   (*((volatile u32 *)0x40039030))
 
#define ADC1_DCISC_R   (*((volatile u32 *)0x40039034))
 
#define ADC1_CTL_R   (*((volatile u32 *)0x40039038))
 
#define ADC1_SSMUX0_R   (*((volatile u32 *)0x40039040))
 
#define ADC1_SSCTL0_R   (*((volatile u32 *)0x40039044))
 
#define ADC1_SSFIFO0_R   (*((volatile u32 *)0x40039048))
 
#define ADC1_SSFSTAT0_R   (*((volatile u32 *)0x4003904C))
 
#define ADC1_SSOP0_R   (*((volatile u32 *)0x40039050))
 
#define ADC1_SSDC0_R   (*((volatile u32 *)0x40039054))
 
#define ADC1_SSMUX1_R   (*((volatile u32 *)0x40039060))
 
#define ADC1_SSCTL1_R   (*((volatile u32 *)0x40039064))
 
#define ADC1_SSFIFO1_R   (*((volatile u32 *)0x40039068))
 
#define ADC1_SSFSTAT1_R   (*((volatile u32 *)0x4003906C))
 
#define ADC1_SSOP1_R   (*((volatile u32 *)0x40039070))
 
#define ADC1_SSDC1_R   (*((volatile u32 *)0x40039074))
 
#define ADC1_SSMUX2_R   (*((volatile u32 *)0x40039080))
 
#define ADC1_SSCTL2_R   (*((volatile u32 *)0x40039084))
 
#define ADC1_SSFIFO2_R   (*((volatile u32 *)0x40039088))
 
#define ADC1_SSFSTAT2_R   (*((volatile u32 *)0x4003908C))
 
#define ADC1_SSOP2_R   (*((volatile u32 *)0x40039090))
 
#define ADC1_SSDC2_R   (*((volatile u32 *)0x40039094))
 
#define ADC1_SSMUX3_R   (*((volatile u32 *)0x400390A0))
 
#define ADC1_SSCTL3_R   (*((volatile u32 *)0x400390A4))
 
#define ADC1_SSFIFO3_R   (*((volatile u32 *)0x400390A8))
 
#define ADC1_SSFSTAT3_R   (*((volatile u32 *)0x400390AC))
 
#define ADC1_SSOP3_R   (*((volatile u32 *)0x400390B0))
 
#define ADC1_SSDC3_R   (*((volatile u32 *)0x400390B4))
 
#define ADC1_DCRIC_R   (*((volatile u32 *)0x40039D00))
 
#define ADC1_DCCTL0_R   (*((volatile u32 *)0x40039E00))
 
#define ADC1_DCCTL1_R   (*((volatile u32 *)0x40039E04))
 
#define ADC1_DCCTL2_R   (*((volatile u32 *)0x40039E08))
 
#define ADC1_DCCTL3_R   (*((volatile u32 *)0x40039E0C))
 
#define ADC1_DCCTL4_R   (*((volatile u32 *)0x40039E10))
 
#define ADC1_DCCTL5_R   (*((volatile u32 *)0x40039E14))
 
#define ADC1_DCCTL6_R   (*((volatile u32 *)0x40039E18))
 
#define ADC1_DCCTL7_R   (*((volatile u32 *)0x40039E1C))
 
#define ADC1_DCCMP0_R   (*((volatile u32 *)0x40039E40))
 
#define ADC1_DCCMP1_R   (*((volatile u32 *)0x40039E44))
 
#define ADC1_DCCMP2_R   (*((volatile u32 *)0x40039E48))
 
#define ADC1_DCCMP3_R   (*((volatile u32 *)0x40039E4C))
 
#define ADC1_DCCMP4_R   (*((volatile u32 *)0x40039E50))
 
#define ADC1_DCCMP5_R   (*((volatile u32 *)0x40039E54))
 
#define ADC1_DCCMP6_R   (*((volatile u32 *)0x40039E58))
 
#define ADC1_DCCMP7_R   (*((volatile u32 *)0x40039E5C))
 
#define ADC1_PP_R   (*((volatile u32 *)0x40039FC0))
 
#define ADC1_PC_R   (*((volatile u32 *)0x40039FC4))
 
#define ADC1_CC_R   (*((volatile u32 *)0x40039FC8))
 
#define COMP_ACMIS_R   (*((volatile u32 *)0x4003C000))
 
#define COMP_ACRIS_R   (*((volatile u32 *)0x4003C004))
 
#define COMP_ACINTEN_R   (*((volatile u32 *)0x4003C008))
 
#define COMP_ACREFCTL_R   (*((volatile u32 *)0x4003C010))
 
#define COMP_ACSTAT0_R   (*((volatile u32 *)0x4003C020))
 
#define COMP_ACCTL0_R   (*((volatile u32 *)0x4003C024))
 
#define COMP_ACSTAT1_R   (*((volatile u32 *)0x4003C040))
 
#define COMP_ACCTL1_R   (*((volatile u32 *)0x4003C044))
 
#define COMP_PP_R   (*((volatile u32 *)0x4003CFC0))
 
#define CAN0_CTL_R   (*((volatile u32 *)0x40040000))
 
#define CAN0_STS_R   (*((volatile u32 *)0x40040004))
 
#define CAN0_ERR_R   (*((volatile u32 *)0x40040008))
 
#define CAN0_BIT_R   (*((volatile u32 *)0x4004000C))
 
#define CAN0_INT_R   (*((volatile u32 *)0x40040010))
 
#define CAN0_TST_R   (*((volatile u32 *)0x40040014))
 
#define CAN0_BRPE_R   (*((volatile u32 *)0x40040018))
 
#define CAN0_IF1CRQ_R   (*((volatile u32 *)0x40040020))
 
#define CAN0_IF1CMSK_R   (*((volatile u32 *)0x40040024))
 
#define CAN0_IF1MSK1_R   (*((volatile u32 *)0x40040028))
 
#define CAN0_IF1MSK2_R   (*((volatile u32 *)0x4004002C))
 
#define CAN0_IF1ARB1_R   (*((volatile u32 *)0x40040030))
 
#define CAN0_IF1ARB2_R   (*((volatile u32 *)0x40040034))
 
#define CAN0_IF1MCTL_R   (*((volatile u32 *)0x40040038))
 
#define CAN0_IF1DA1_R   (*((volatile u32 *)0x4004003C))
 
#define CAN0_IF1DA2_R   (*((volatile u32 *)0x40040040))
 
#define CAN0_IF1DB1_R   (*((volatile u32 *)0x40040044))
 
#define CAN0_IF1DB2_R   (*((volatile u32 *)0x40040048))
 
#define CAN0_IF2CRQ_R   (*((volatile u32 *)0x40040080))
 
#define CAN0_IF2CMSK_R   (*((volatile u32 *)0x40040084))
 
#define CAN0_IF2MSK1_R   (*((volatile u32 *)0x40040088))
 
#define CAN0_IF2MSK2_R   (*((volatile u32 *)0x4004008C))
 
#define CAN0_IF2ARB1_R   (*((volatile u32 *)0x40040090))
 
#define CAN0_IF2ARB2_R   (*((volatile u32 *)0x40040094))
 
#define CAN0_IF2MCTL_R   (*((volatile u32 *)0x40040098))
 
#define CAN0_IF2DA1_R   (*((volatile u32 *)0x4004009C))
 
#define CAN0_IF2DA2_R   (*((volatile u32 *)0x400400A0))
 
#define CAN0_IF2DB1_R   (*((volatile u32 *)0x400400A4))
 
#define CAN0_IF2DB2_R   (*((volatile u32 *)0x400400A8))
 
#define CAN0_TXRQ1_R   (*((volatile u32 *)0x40040100))
 
#define CAN0_TXRQ2_R   (*((volatile u32 *)0x40040104))
 
#define CAN0_NWDA1_R   (*((volatile u32 *)0x40040120))
 
#define CAN0_NWDA2_R   (*((volatile u32 *)0x40040124))
 
#define CAN0_MSG1INT_R   (*((volatile u32 *)0x40040140))
 
#define CAN0_MSG2INT_R   (*((volatile u32 *)0x40040144))
 
#define CAN0_MSG1VAL_R   (*((volatile u32 *)0x40040160))
 
#define CAN0_MSG2VAL_R   (*((volatile u32 *)0x40040164))
 
#define CAN1_CTL_R   (*((volatile u32 *)0x40041000))
 
#define CAN1_STS_R   (*((volatile u32 *)0x40041004))
 
#define CAN1_ERR_R   (*((volatile u32 *)0x40041008))
 
#define CAN1_BIT_R   (*((volatile u32 *)0x4004100C))
 
#define CAN1_INT_R   (*((volatile u32 *)0x40041010))
 
#define CAN1_TST_R   (*((volatile u32 *)0x40041014))
 
#define CAN1_BRPE_R   (*((volatile u32 *)0x40041018))
 
#define CAN1_IF1CRQ_R   (*((volatile u32 *)0x40041020))
 
#define CAN1_IF1CMSK_R   (*((volatile u32 *)0x40041024))
 
#define CAN1_IF1MSK1_R   (*((volatile u32 *)0x40041028))
 
#define CAN1_IF1MSK2_R   (*((volatile u32 *)0x4004102C))
 
#define CAN1_IF1ARB1_R   (*((volatile u32 *)0x40041030))
 
#define CAN1_IF1ARB2_R   (*((volatile u32 *)0x40041034))
 
#define CAN1_IF1MCTL_R   (*((volatile u32 *)0x40041038))
 
#define CAN1_IF1DA1_R   (*((volatile u32 *)0x4004103C))
 
#define CAN1_IF1DA2_R   (*((volatile u32 *)0x40041040))
 
#define CAN1_IF1DB1_R   (*((volatile u32 *)0x40041044))
 
#define CAN1_IF1DB2_R   (*((volatile u32 *)0x40041048))
 
#define CAN1_IF2CRQ_R   (*((volatile u32 *)0x40041080))
 
#define CAN1_IF2CMSK_R   (*((volatile u32 *)0x40041084))
 
#define CAN1_IF2MSK1_R   (*((volatile u32 *)0x40041088))
 
#define CAN1_IF2MSK2_R   (*((volatile u32 *)0x4004108C))
 
#define CAN1_IF2ARB1_R   (*((volatile u32 *)0x40041090))
 
#define CAN1_IF2ARB2_R   (*((volatile u32 *)0x40041094))
 
#define CAN1_IF2MCTL_R   (*((volatile u32 *)0x40041098))
 
#define CAN1_IF2DA1_R   (*((volatile u32 *)0x4004109C))
 
#define CAN1_IF2DA2_R   (*((volatile u32 *)0x400410A0))
 
#define CAN1_IF2DB1_R   (*((volatile u32 *)0x400410A4))
 
#define CAN1_IF2DB2_R   (*((volatile u32 *)0x400410A8))
 
#define CAN1_TXRQ1_R   (*((volatile u32 *)0x40041100))
 
#define CAN1_TXRQ2_R   (*((volatile u32 *)0x40041104))
 
#define CAN1_NWDA1_R   (*((volatile u32 *)0x40041120))
 
#define CAN1_NWDA2_R   (*((volatile u32 *)0x40041124))
 
#define CAN1_MSG1INT_R   (*((volatile u32 *)0x40041140))
 
#define CAN1_MSG2INT_R   (*((volatile u32 *)0x40041144))
 
#define CAN1_MSG1VAL_R   (*((volatile u32 *)0x40041160))
 
#define CAN1_MSG2VAL_R   (*((volatile u32 *)0x40041164))
 
#define WTIMER2_CFG_R   (*((volatile u32 *)0x4004C000))
 
#define WTIMER2_TAMR_R   (*((volatile u32 *)0x4004C004))
 
#define WTIMER2_TBMR_R   (*((volatile u32 *)0x4004C008))
 
#define WTIMER2_CTL_R   (*((volatile u32 *)0x4004C00C))
 
#define WTIMER2_SYNC_R   (*((volatile u32 *)0x4004C010))
 
#define WTIMER2_IMR_R   (*((volatile u32 *)0x4004C018))
 
#define WTIMER2_RIS_R   (*((volatile u32 *)0x4004C01C))
 
#define WTIMER2_MIS_R   (*((volatile u32 *)0x4004C020))
 
#define WTIMER2_ICR_R   (*((volatile u32 *)0x4004C024))
 
#define WTIMER2_TAILR_R   (*((volatile u32 *)0x4004C028))
 
#define WTIMER2_TBILR_R   (*((volatile u32 *)0x4004C02C))
 
#define WTIMER2_TAMATCHR_R   (*((volatile u32 *)0x4004C030))
 
#define WTIMER2_TBMATCHR_R   (*((volatile u32 *)0x4004C034))
 
#define WTIMER2_TAPR_R   (*((volatile u32 *)0x4004C038))
 
#define WTIMER2_TBPR_R   (*((volatile u32 *)0x4004C03C))
 
#define WTIMER2_TAPMR_R   (*((volatile u32 *)0x4004C040))
 
#define WTIMER2_TBPMR_R   (*((volatile u32 *)0x4004C044))
 
#define WTIMER2_TAR_R   (*((volatile u32 *)0x4004C048))
 
#define WTIMER2_TBR_R   (*((volatile u32 *)0x4004C04C))
 
#define WTIMER2_TAV_R   (*((volatile u32 *)0x4004C050))
 
#define WTIMER2_TBV_R   (*((volatile u32 *)0x4004C054))
 
#define WTIMER2_RTCPD_R   (*((volatile u32 *)0x4004C058))
 
#define WTIMER2_TAPS_R   (*((volatile u32 *)0x4004C05C))
 
#define WTIMER2_TBPS_R   (*((volatile u32 *)0x4004C060))
 
#define WTIMER2_TAPV_R   (*((volatile u32 *)0x4004C064))
 
#define WTIMER2_TBPV_R   (*((volatile u32 *)0x4004C068))
 
#define WTIMER2_PP_R   (*((volatile u32 *)0x4004CFC0))
 
#define WTIMER3_CFG_R   (*((volatile u32 *)0x4004D000))
 
#define WTIMER3_TAMR_R   (*((volatile u32 *)0x4004D004))
 
#define WTIMER3_TBMR_R   (*((volatile u32 *)0x4004D008))
 
#define WTIMER3_CTL_R   (*((volatile u32 *)0x4004D00C))
 
#define WTIMER3_SYNC_R   (*((volatile u32 *)0x4004D010))
 
#define WTIMER3_IMR_R   (*((volatile u32 *)0x4004D018))
 
#define WTIMER3_RIS_R   (*((volatile u32 *)0x4004D01C))
 
#define WTIMER3_MIS_R   (*((volatile u32 *)0x4004D020))
 
#define WTIMER3_ICR_R   (*((volatile u32 *)0x4004D024))
 
#define WTIMER3_TAILR_R   (*((volatile u32 *)0x4004D028))
 
#define WTIMER3_TBILR_R   (*((volatile u32 *)0x4004D02C))
 
#define WTIMER3_TAMATCHR_R   (*((volatile u32 *)0x4004D030))
 
#define WTIMER3_TBMATCHR_R   (*((volatile u32 *)0x4004D034))
 
#define WTIMER3_TAPR_R   (*((volatile u32 *)0x4004D038))
 
#define WTIMER3_TBPR_R   (*((volatile u32 *)0x4004D03C))
 
#define WTIMER3_TAPMR_R   (*((volatile u32 *)0x4004D040))
 
#define WTIMER3_TBPMR_R   (*((volatile u32 *)0x4004D044))
 
#define WTIMER3_TAR_R   (*((volatile u32 *)0x4004D048))
 
#define WTIMER3_TBR_R   (*((volatile u32 *)0x4004D04C))
 
#define WTIMER3_TAV_R   (*((volatile u32 *)0x4004D050))
 
#define WTIMER3_TBV_R   (*((volatile u32 *)0x4004D054))
 
#define WTIMER3_RTCPD_R   (*((volatile u32 *)0x4004D058))
 
#define WTIMER3_TAPS_R   (*((volatile u32 *)0x4004D05C))
 
#define WTIMER3_TBPS_R   (*((volatile u32 *)0x4004D060))
 
#define WTIMER3_TAPV_R   (*((volatile u32 *)0x4004D064))
 
#define WTIMER3_TBPV_R   (*((volatile u32 *)0x4004D068))
 
#define WTIMER3_PP_R   (*((volatile u32 *)0x4004DFC0))
 
#define WTIMER4_CFG_R   (*((volatile u32 *)0x4004E000))
 
#define WTIMER4_TAMR_R   (*((volatile u32 *)0x4004E004))
 
#define WTIMER4_TBMR_R   (*((volatile u32 *)0x4004E008))
 
#define WTIMER4_CTL_R   (*((volatile u32 *)0x4004E00C))
 
#define WTIMER4_SYNC_R   (*((volatile u32 *)0x4004E010))
 
#define WTIMER4_IMR_R   (*((volatile u32 *)0x4004E018))
 
#define WTIMER4_RIS_R   (*((volatile u32 *)0x4004E01C))
 
#define WTIMER4_MIS_R   (*((volatile u32 *)0x4004E020))
 
#define WTIMER4_ICR_R   (*((volatile u32 *)0x4004E024))
 
#define WTIMER4_TAILR_R   (*((volatile u32 *)0x4004E028))
 
#define WTIMER4_TBILR_R   (*((volatile u32 *)0x4004E02C))
 
#define WTIMER4_TAMATCHR_R   (*((volatile u32 *)0x4004E030))
 
#define WTIMER4_TBMATCHR_R   (*((volatile u32 *)0x4004E034))
 
#define WTIMER4_TAPR_R   (*((volatile u32 *)0x4004E038))
 
#define WTIMER4_TBPR_R   (*((volatile u32 *)0x4004E03C))
 
#define WTIMER4_TAPMR_R   (*((volatile u32 *)0x4004E040))
 
#define WTIMER4_TBPMR_R   (*((volatile u32 *)0x4004E044))
 
#define WTIMER4_TAR_R   (*((volatile u32 *)0x4004E048))
 
#define WTIMER4_TBR_R   (*((volatile u32 *)0x4004E04C))
 
#define WTIMER4_TAV_R   (*((volatile u32 *)0x4004E050))
 
#define WTIMER4_TBV_R   (*((volatile u32 *)0x4004E054))
 
#define WTIMER4_RTCPD_R   (*((volatile u32 *)0x4004E058))
 
#define WTIMER4_TAPS_R   (*((volatile u32 *)0x4004E05C))
 
#define WTIMER4_TBPS_R   (*((volatile u32 *)0x4004E060))
 
#define WTIMER4_TAPV_R   (*((volatile u32 *)0x4004E064))
 
#define WTIMER4_TBPV_R   (*((volatile u32 *)0x4004E068))
 
#define WTIMER4_PP_R   (*((volatile u32 *)0x4004EFC0))
 
#define WTIMER5_CFG_R   (*((volatile u32 *)0x4004F000))
 
#define WTIMER5_TAMR_R   (*((volatile u32 *)0x4004F004))
 
#define WTIMER5_TBMR_R   (*((volatile u32 *)0x4004F008))
 
#define WTIMER5_CTL_R   (*((volatile u32 *)0x4004F00C))
 
#define WTIMER5_SYNC_R   (*((volatile u32 *)0x4004F010))
 
#define WTIMER5_IMR_R   (*((volatile u32 *)0x4004F018))
 
#define WTIMER5_RIS_R   (*((volatile u32 *)0x4004F01C))
 
#define WTIMER5_MIS_R   (*((volatile u32 *)0x4004F020))
 
#define WTIMER5_ICR_R   (*((volatile u32 *)0x4004F024))
 
#define WTIMER5_TAILR_R   (*((volatile u32 *)0x4004F028))
 
#define WTIMER5_TBILR_R   (*((volatile u32 *)0x4004F02C))
 
#define WTIMER5_TAMATCHR_R   (*((volatile u32 *)0x4004F030))
 
#define WTIMER5_TBMATCHR_R   (*((volatile u32 *)0x4004F034))
 
#define WTIMER5_TAPR_R   (*((volatile u32 *)0x4004F038))
 
#define WTIMER5_TBPR_R   (*((volatile u32 *)0x4004F03C))
 
#define WTIMER5_TAPMR_R   (*((volatile u32 *)0x4004F040))
 
#define WTIMER5_TBPMR_R   (*((volatile u32 *)0x4004F044))
 
#define WTIMER5_TAR_R   (*((volatile u32 *)0x4004F048))
 
#define WTIMER5_TBR_R   (*((volatile u32 *)0x4004F04C))
 
#define WTIMER5_TAV_R   (*((volatile u32 *)0x4004F050))
 
#define WTIMER5_TBV_R   (*((volatile u32 *)0x4004F054))
 
#define WTIMER5_RTCPD_R   (*((volatile u32 *)0x4004F058))
 
#define WTIMER5_TAPS_R   (*((volatile u32 *)0x4004F05C))
 
#define WTIMER5_TBPS_R   (*((volatile u32 *)0x4004F060))
 
#define WTIMER5_TAPV_R   (*((volatile u32 *)0x4004F064))
 
#define WTIMER5_TBPV_R   (*((volatile u32 *)0x4004F068))
 
#define WTIMER5_PP_R   (*((volatile u32 *)0x4004FFC0))
 
#define USB0_FADDR_R   (*((volatile uint8_t *)0x40050000))
 
#define USB0_POWER_R   (*((volatile uint8_t *)0x40050001))
 
#define USB0_TXIS_R   (*((volatile uint16_t *)0x40050002))
 
#define USB0_RXIS_R   (*((volatile uint16_t *)0x40050004))
 
#define USB0_TXIE_R   (*((volatile uint16_t *)0x40050006))
 
#define USB0_RXIE_R   (*((volatile uint16_t *)0x40050008))
 
#define USB0_IS_R   (*((volatile uint8_t *)0x4005000A))
 
#define USB0_IE_R   (*((volatile uint8_t *)0x4005000B))
 
#define USB0_FRAME_R   (*((volatile uint16_t *)0x4005000C))
 
#define USB0_EPIDX_R   (*((volatile uint8_t *)0x4005000E))
 
#define USB0_TEST_R   (*((volatile uint8_t *)0x4005000F))
 
#define USB0_FIFO0_R   (*((volatile u32 *)0x40050020))
 
#define USB0_FIFO1_R   (*((volatile u32 *)0x40050024))
 
#define USB0_FIFO2_R   (*((volatile u32 *)0x40050028))
 
#define USB0_FIFO3_R   (*((volatile u32 *)0x4005002C))
 
#define USB0_FIFO4_R   (*((volatile u32 *)0x40050030))
 
#define USB0_FIFO5_R   (*((volatile u32 *)0x40050034))
 
#define USB0_FIFO6_R   (*((volatile u32 *)0x40050038))
 
#define USB0_FIFO7_R   (*((volatile u32 *)0x4005003C))
 
#define USB0_DEVCTL_R   (*((volatile uint8_t *)0x40050060))
 
#define USB0_TXFIFOSZ_R   (*((volatile uint8_t *)0x40050062))
 
#define USB0_RXFIFOSZ_R   (*((volatile uint8_t *)0x40050063))
 
#define USB0_TXFIFOADD_R   (*((volatile uint16_t *)0x40050064))
 
#define USB0_RXFIFOADD_R   (*((volatile uint16_t *)0x40050066))
 
#define USB0_CONTIM_R   (*((volatile uint8_t *)0x4005007A))
 
#define USB0_VPLEN_R   (*((volatile uint8_t *)0x4005007B))
 
#define USB0_FSEOF_R   (*((volatile uint8_t *)0x4005007D))
 
#define USB0_LSEOF_R   (*((volatile uint8_t *)0x4005007E))
 
#define USB0_TXFUNCADDR0_R   (*((volatile uint8_t *)0x40050080))
 
#define USB0_TXHUBADDR0_R   (*((volatile uint8_t *)0x40050082))
 
#define USB0_TXHUBPORT0_R   (*((volatile uint8_t *)0x40050083))
 
#define USB0_TXFUNCADDR1_R   (*((volatile uint8_t *)0x40050088))
 
#define USB0_TXHUBADDR1_R   (*((volatile uint8_t *)0x4005008A))
 
#define USB0_TXHUBPORT1_R   (*((volatile uint8_t *)0x4005008B))
 
#define USB0_RXFUNCADDR1_R   (*((volatile uint8_t *)0x4005008C))
 
#define USB0_RXHUBADDR1_R   (*((volatile uint8_t *)0x4005008E))
 
#define USB0_RXHUBPORT1_R   (*((volatile uint8_t *)0x4005008F))
 
#define USB0_TXFUNCADDR2_R   (*((volatile uint8_t *)0x40050090))
 
#define USB0_TXHUBADDR2_R   (*((volatile uint8_t *)0x40050092))
 
#define USB0_TXHUBPORT2_R   (*((volatile uint8_t *)0x40050093))
 
#define USB0_RXFUNCADDR2_R   (*((volatile uint8_t *)0x40050094))
 
#define USB0_RXHUBADDR2_R   (*((volatile uint8_t *)0x40050096))
 
#define USB0_RXHUBPORT2_R   (*((volatile uint8_t *)0x40050097))
 
#define USB0_TXFUNCADDR3_R   (*((volatile uint8_t *)0x40050098))
 
#define USB0_TXHUBADDR3_R   (*((volatile uint8_t *)0x4005009A))
 
#define USB0_TXHUBPORT3_R   (*((volatile uint8_t *)0x4005009B))
 
#define USB0_RXFUNCADDR3_R   (*((volatile uint8_t *)0x4005009C))
 
#define USB0_RXHUBADDR3_R   (*((volatile uint8_t *)0x4005009E))
 
#define USB0_RXHUBPORT3_R   (*((volatile uint8_t *)0x4005009F))
 
#define USB0_TXFUNCADDR4_R   (*((volatile uint8_t *)0x400500A0))
 
#define USB0_TXHUBADDR4_R   (*((volatile uint8_t *)0x400500A2))
 
#define USB0_TXHUBPORT4_R   (*((volatile uint8_t *)0x400500A3))
 
#define USB0_RXFUNCADDR4_R   (*((volatile uint8_t *)0x400500A4))
 
#define USB0_RXHUBADDR4_R   (*((volatile uint8_t *)0x400500A6))
 
#define USB0_RXHUBPORT4_R   (*((volatile uint8_t *)0x400500A7))
 
#define USB0_TXFUNCADDR5_R   (*((volatile uint8_t *)0x400500A8))
 
#define USB0_TXHUBADDR5_R   (*((volatile uint8_t *)0x400500AA))
 
#define USB0_TXHUBPORT5_R   (*((volatile uint8_t *)0x400500AB))
 
#define USB0_RXFUNCADDR5_R   (*((volatile uint8_t *)0x400500AC))
 
#define USB0_RXHUBADDR5_R   (*((volatile uint8_t *)0x400500AE))
 
#define USB0_RXHUBPORT5_R   (*((volatile uint8_t *)0x400500AF))
 
#define USB0_TXFUNCADDR6_R   (*((volatile uint8_t *)0x400500B0))
 
#define USB0_TXHUBADDR6_R   (*((volatile uint8_t *)0x400500B2))
 
#define USB0_TXHUBPORT6_R   (*((volatile uint8_t *)0x400500B3))
 
#define USB0_RXFUNCADDR6_R   (*((volatile uint8_t *)0x400500B4))
 
#define USB0_RXHUBADDR6_R   (*((volatile uint8_t *)0x400500B6))
 
#define USB0_RXHUBPORT6_R   (*((volatile uint8_t *)0x400500B7))
 
#define USB0_TXFUNCADDR7_R   (*((volatile uint8_t *)0x400500B8))
 
#define USB0_TXHUBADDR7_R   (*((volatile uint8_t *)0x400500BA))
 
#define USB0_TXHUBPORT7_R   (*((volatile uint8_t *)0x400500BB))
 
#define USB0_RXFUNCADDR7_R   (*((volatile uint8_t *)0x400500BC))
 
#define USB0_RXHUBADDR7_R   (*((volatile uint8_t *)0x400500BE))
 
#define USB0_RXHUBPORT7_R   (*((volatile uint8_t *)0x400500BF))
 
#define USB0_CSRL0_R   (*((volatile uint8_t *)0x40050102))
 
#define USB0_CSRH0_R   (*((volatile uint8_t *)0x40050103))
 
#define USB0_COUNT0_R   (*((volatile uint8_t *)0x40050108))
 
#define USB0_TYPE0_R   (*((volatile uint8_t *)0x4005010A))
 
#define USB0_NAKLMT_R   (*((volatile uint8_t *)0x4005010B))
 
#define USB0_TXMAXP1_R   (*((volatile uint16_t *)0x40050110))
 
#define USB0_TXCSRL1_R   (*((volatile uint8_t *)0x40050112))
 
#define USB0_TXCSRH1_R   (*((volatile uint8_t *)0x40050113))
 
#define USB0_RXMAXP1_R   (*((volatile uint16_t *)0x40050114))
 
#define USB0_RXCSRL1_R   (*((volatile uint8_t *)0x40050116))
 
#define USB0_RXCSRH1_R   (*((volatile uint8_t *)0x40050117))
 
#define USB0_RXCOUNT1_R   (*((volatile uint16_t *)0x40050118))
 
#define USB0_TXTYPE1_R   (*((volatile uint8_t *)0x4005011A))
 
#define USB0_TXINTERVAL1_R   (*((volatile uint8_t *)0x4005011B))
 
#define USB0_RXTYPE1_R   (*((volatile uint8_t *)0x4005011C))
 
#define USB0_RXINTERVAL1_R   (*((volatile uint8_t *)0x4005011D))
 
#define USB0_TXMAXP2_R   (*((volatile uint16_t *)0x40050120))
 
#define USB0_TXCSRL2_R   (*((volatile uint8_t *)0x40050122))
 
#define USB0_TXCSRH2_R   (*((volatile uint8_t *)0x40050123))
 
#define USB0_RXMAXP2_R   (*((volatile uint16_t *)0x40050124))
 
#define USB0_RXCSRL2_R   (*((volatile uint8_t *)0x40050126))
 
#define USB0_RXCSRH2_R   (*((volatile uint8_t *)0x40050127))
 
#define USB0_RXCOUNT2_R   (*((volatile uint16_t *)0x40050128))
 
#define USB0_TXTYPE2_R   (*((volatile uint8_t *)0x4005012A))
 
#define USB0_TXINTERVAL2_R   (*((volatile uint8_t *)0x4005012B))
 
#define USB0_RXTYPE2_R   (*((volatile uint8_t *)0x4005012C))
 
#define USB0_RXINTERVAL2_R   (*((volatile uint8_t *)0x4005012D))
 
#define USB0_TXMAXP3_R   (*((volatile uint16_t *)0x40050130))
 
#define USB0_TXCSRL3_R   (*((volatile uint8_t *)0x40050132))
 
#define USB0_TXCSRH3_R   (*((volatile uint8_t *)0x40050133))
 
#define USB0_RXMAXP3_R   (*((volatile uint16_t *)0x40050134))
 
#define USB0_RXCSRL3_R   (*((volatile uint8_t *)0x40050136))
 
#define USB0_RXCSRH3_R   (*((volatile uint8_t *)0x40050137))
 
#define USB0_RXCOUNT3_R   (*((volatile uint16_t *)0x40050138))
 
#define USB0_TXTYPE3_R   (*((volatile uint8_t *)0x4005013A))
 
#define USB0_TXINTERVAL3_R   (*((volatile uint8_t *)0x4005013B))
 
#define USB0_RXTYPE3_R   (*((volatile uint8_t *)0x4005013C))
 
#define USB0_RXINTERVAL3_R   (*((volatile uint8_t *)0x4005013D))
 
#define USB0_TXMAXP4_R   (*((volatile uint16_t *)0x40050140))
 
#define USB0_TXCSRL4_R   (*((volatile uint8_t *)0x40050142))
 
#define USB0_TXCSRH4_R   (*((volatile uint8_t *)0x40050143))
 
#define USB0_RXMAXP4_R   (*((volatile uint16_t *)0x40050144))
 
#define USB0_RXCSRL4_R   (*((volatile uint8_t *)0x40050146))
 
#define USB0_RXCSRH4_R   (*((volatile uint8_t *)0x40050147))
 
#define USB0_RXCOUNT4_R   (*((volatile uint16_t *)0x40050148))
 
#define USB0_TXTYPE4_R   (*((volatile uint8_t *)0x4005014A))
 
#define USB0_TXINTERVAL4_R   (*((volatile uint8_t *)0x4005014B))
 
#define USB0_RXTYPE4_R   (*((volatile uint8_t *)0x4005014C))
 
#define USB0_RXINTERVAL4_R   (*((volatile uint8_t *)0x4005014D))
 
#define USB0_TXMAXP5_R   (*((volatile uint16_t *)0x40050150))
 
#define USB0_TXCSRL5_R   (*((volatile uint8_t *)0x40050152))
 
#define USB0_TXCSRH5_R   (*((volatile uint8_t *)0x40050153))
 
#define USB0_RXMAXP5_R   (*((volatile uint16_t *)0x40050154))
 
#define USB0_RXCSRL5_R   (*((volatile uint8_t *)0x40050156))
 
#define USB0_RXCSRH5_R   (*((volatile uint8_t *)0x40050157))
 
#define USB0_RXCOUNT5_R   (*((volatile uint16_t *)0x40050158))
 
#define USB0_TXTYPE5_R   (*((volatile uint8_t *)0x4005015A))
 
#define USB0_TXINTERVAL5_R   (*((volatile uint8_t *)0x4005015B))
 
#define USB0_RXTYPE5_R   (*((volatile uint8_t *)0x4005015C))
 
#define USB0_RXINTERVAL5_R   (*((volatile uint8_t *)0x4005015D))
 
#define USB0_TXMAXP6_R   (*((volatile uint16_t *)0x40050160))
 
#define USB0_TXCSRL6_R   (*((volatile uint8_t *)0x40050162))
 
#define USB0_TXCSRH6_R   (*((volatile uint8_t *)0x40050163))
 
#define USB0_RXMAXP6_R   (*((volatile uint16_t *)0x40050164))
 
#define USB0_RXCSRL6_R   (*((volatile uint8_t *)0x40050166))
 
#define USB0_RXCSRH6_R   (*((volatile uint8_t *)0x40050167))
 
#define USB0_RXCOUNT6_R   (*((volatile uint16_t *)0x40050168))
 
#define USB0_TXTYPE6_R   (*((volatile uint8_t *)0x4005016A))
 
#define USB0_TXINTERVAL6_R   (*((volatile uint8_t *)0x4005016B))
 
#define USB0_RXTYPE6_R   (*((volatile uint8_t *)0x4005016C))
 
#define USB0_RXINTERVAL6_R   (*((volatile uint8_t *)0x4005016D))
 
#define USB0_TXMAXP7_R   (*((volatile uint16_t *)0x40050170))
 
#define USB0_TXCSRL7_R   (*((volatile uint8_t *)0x40050172))
 
#define USB0_TXCSRH7_R   (*((volatile uint8_t *)0x40050173))
 
#define USB0_RXMAXP7_R   (*((volatile uint16_t *)0x40050174))
 
#define USB0_RXCSRL7_R   (*((volatile uint8_t *)0x40050176))
 
#define USB0_RXCSRH7_R   (*((volatile uint8_t *)0x40050177))
 
#define USB0_RXCOUNT7_R   (*((volatile uint16_t *)0x40050178))
 
#define USB0_TXTYPE7_R   (*((volatile uint8_t *)0x4005017A))
 
#define USB0_TXINTERVAL7_R   (*((volatile uint8_t *)0x4005017B))
 
#define USB0_RXTYPE7_R   (*((volatile uint8_t *)0x4005017C))
 
#define USB0_RXINTERVAL7_R   (*((volatile uint8_t *)0x4005017D))
 
#define USB0_RQPKTCOUNT1_R   (*((volatile uint16_t *)0x40050304))
 
#define USB0_RQPKTCOUNT2_R   (*((volatile uint16_t *)0x40050308))
 
#define USB0_RQPKTCOUNT3_R   (*((volatile uint16_t *)0x4005030C))
 
#define USB0_RQPKTCOUNT4_R   (*((volatile uint16_t *)0x40050310))
 
#define USB0_RQPKTCOUNT5_R   (*((volatile uint16_t *)0x40050314))
 
#define USB0_RQPKTCOUNT6_R   (*((volatile uint16_t *)0x40050318))
 
#define USB0_RQPKTCOUNT7_R   (*((volatile uint16_t *)0x4005031C))
 
#define USB0_RXDPKTBUFDIS_R   (*((volatile uint16_t *)0x40050340))
 
#define USB0_TXDPKTBUFDIS_R   (*((volatile uint16_t *)0x40050342))
 
#define USB0_EPC_R   (*((volatile u32 *)0x40050400))
 
#define USB0_EPCRIS_R   (*((volatile u32 *)0x40050404))
 
#define USB0_EPCIM_R   (*((volatile u32 *)0x40050408))
 
#define USB0_EPCISC_R   (*((volatile u32 *)0x4005040C))
 
#define USB0_DRRIS_R   (*((volatile u32 *)0x40050410))
 
#define USB0_DRIM_R   (*((volatile u32 *)0x40050414))
 
#define USB0_DRISC_R   (*((volatile u32 *)0x40050418))
 
#define USB0_GPCS_R   (*((volatile u32 *)0x4005041C))
 
#define USB0_VDC_R   (*((volatile u32 *)0x40050430))
 
#define USB0_VDCRIS_R   (*((volatile u32 *)0x40050434))
 
#define USB0_VDCIM_R   (*((volatile u32 *)0x40050438))
 
#define USB0_VDCISC_R   (*((volatile u32 *)0x4005043C))
 
#define USB0_IDVRIS_R   (*((volatile u32 *)0x40050444))
 
#define USB0_IDVIM_R   (*((volatile u32 *)0x40050448))
 
#define USB0_IDVISC_R   (*((volatile u32 *)0x4005044C))
 
#define USB0_DMASEL_R   (*((volatile u32 *)0x40050450))
 
#define USB0_PP_R   (*((volatile u32 *)0x40050FC0))
 
#define GPIO_PORTA_AHB_DATA_BITS_R    ((volatile u32 *)0x40058000)
 
#define GPIO_PORTA_AHB_DATA_R   (*((volatile u32 *)0x400583FC))
 
#define GPIO_PORTA_AHB_DIR_R   (*((volatile u32 *)0x40058400))
 
#define GPIO_PORTA_AHB_IS_R   (*((volatile u32 *)0x40058404))
 
#define GPIO_PORTA_AHB_IBE_R   (*((volatile u32 *)0x40058408))
 
#define GPIO_PORTA_AHB_IEV_R   (*((volatile u32 *)0x4005840C))
 
#define GPIO_PORTA_AHB_IM_R   (*((volatile u32 *)0x40058410))
 
#define GPIO_PORTA_AHB_RIS_R   (*((volatile u32 *)0x40058414))
 
#define GPIO_PORTA_AHB_MIS_R   (*((volatile u32 *)0x40058418))
 
#define GPIO_PORTA_AHB_ICR_R   (*((volatile u32 *)0x4005841C))
 
#define GPIO_PORTA_AHB_AFSEL_R   (*((volatile u32 *)0x40058420))
 
#define GPIO_PORTA_AHB_DR2R_R   (*((volatile u32 *)0x40058500))
 
#define GPIO_PORTA_AHB_DR4R_R   (*((volatile u32 *)0x40058504))
 
#define GPIO_PORTA_AHB_DR8R_R   (*((volatile u32 *)0x40058508))
 
#define GPIO_PORTA_AHB_ODR_R   (*((volatile u32 *)0x4005850C))
 
#define GPIO_PORTA_AHB_PUR_R   (*((volatile u32 *)0x40058510))
 
#define GPIO_PORTA_AHB_PDR_R   (*((volatile u32 *)0x40058514))
 
#define GPIO_PORTA_AHB_SLR_R   (*((volatile u32 *)0x40058518))
 
#define GPIO_PORTA_AHB_DEN_R   (*((volatile u32 *)0x4005851C))
 
#define GPIO_PORTA_AHB_LOCK_R   (*((volatile u32 *)0x40058520))
 
#define GPIO_PORTA_AHB_CR_R   (*((volatile u32 *)0x40058524))
 
#define GPIO_PORTA_AHB_AMSEL_R   (*((volatile u32 *)0x40058528))
 
#define GPIO_PORTA_AHB_PCTL_R   (*((volatile u32 *)0x4005852C))
 
#define GPIO_PORTA_AHB_ADCCTL_R   (*((volatile u32 *)0x40058530))
 
#define GPIO_PORTA_AHB_DMACTL_R   (*((volatile u32 *)0x40058534))
 
#define GPIO_PORTB_AHB_DATA_BITS_R    ((volatile u32 *)0x40059000)
 
#define GPIO_PORTB_AHB_DATA_R   (*((volatile u32 *)0x400593FC))
 
#define GPIO_PORTB_AHB_DIR_R   (*((volatile u32 *)0x40059400))
 
#define GPIO_PORTB_AHB_IS_R   (*((volatile u32 *)0x40059404))
 
#define GPIO_PORTB_AHB_IBE_R   (*((volatile u32 *)0x40059408))
 
#define GPIO_PORTB_AHB_IEV_R   (*((volatile u32 *)0x4005940C))
 
#define GPIO_PORTB_AHB_IM_R   (*((volatile u32 *)0x40059410))
 
#define GPIO_PORTB_AHB_RIS_R   (*((volatile u32 *)0x40059414))
 
#define GPIO_PORTB_AHB_MIS_R   (*((volatile u32 *)0x40059418))
 
#define GPIO_PORTB_AHB_ICR_R   (*((volatile u32 *)0x4005941C))
 
#define GPIO_PORTB_AHB_AFSEL_R   (*((volatile u32 *)0x40059420))
 
#define GPIO_PORTB_AHB_DR2R_R   (*((volatile u32 *)0x40059500))
 
#define GPIO_PORTB_AHB_DR4R_R   (*((volatile u32 *)0x40059504))
 
#define GPIO_PORTB_AHB_DR8R_R   (*((volatile u32 *)0x40059508))
 
#define GPIO_PORTB_AHB_ODR_R   (*((volatile u32 *)0x4005950C))
 
#define GPIO_PORTB_AHB_PUR_R   (*((volatile u32 *)0x40059510))
 
#define GPIO_PORTB_AHB_PDR_R   (*((volatile u32 *)0x40059514))
 
#define GPIO_PORTB_AHB_SLR_R   (*((volatile u32 *)0x40059518))
 
#define GPIO_PORTB_AHB_DEN_R   (*((volatile u32 *)0x4005951C))
 
#define GPIO_PORTB_AHB_LOCK_R   (*((volatile u32 *)0x40059520))
 
#define GPIO_PORTB_AHB_CR_R   (*((volatile u32 *)0x40059524))
 
#define GPIO_PORTB_AHB_AMSEL_R   (*((volatile u32 *)0x40059528))
 
#define GPIO_PORTB_AHB_PCTL_R   (*((volatile u32 *)0x4005952C))
 
#define GPIO_PORTB_AHB_ADCCTL_R   (*((volatile u32 *)0x40059530))
 
#define GPIO_PORTB_AHB_DMACTL_R   (*((volatile u32 *)0x40059534))
 
#define GPIO_PORTC_AHB_DATA_BITS_R    ((volatile u32 *)0x4005A000)
 
#define GPIO_PORTC_AHB_DATA_R   (*((volatile u32 *)0x4005A3FC))
 
#define GPIO_PORTC_AHB_DIR_R   (*((volatile u32 *)0x4005A400))
 
#define GPIO_PORTC_AHB_IS_R   (*((volatile u32 *)0x4005A404))
 
#define GPIO_PORTC_AHB_IBE_R   (*((volatile u32 *)0x4005A408))
 
#define GPIO_PORTC_AHB_IEV_R   (*((volatile u32 *)0x4005A40C))
 
#define GPIO_PORTC_AHB_IM_R   (*((volatile u32 *)0x4005A410))
 
#define GPIO_PORTC_AHB_RIS_R   (*((volatile u32 *)0x4005A414))
 
#define GPIO_PORTC_AHB_MIS_R   (*((volatile u32 *)0x4005A418))
 
#define GPIO_PORTC_AHB_ICR_R   (*((volatile u32 *)0x4005A41C))
 
#define GPIO_PORTC_AHB_AFSEL_R   (*((volatile u32 *)0x4005A420))
 
#define GPIO_PORTC_AHB_DR2R_R   (*((volatile u32 *)0x4005A500))
 
#define GPIO_PORTC_AHB_DR4R_R   (*((volatile u32 *)0x4005A504))
 
#define GPIO_PORTC_AHB_DR8R_R   (*((volatile u32 *)0x4005A508))
 
#define GPIO_PORTC_AHB_ODR_R   (*((volatile u32 *)0x4005A50C))
 
#define GPIO_PORTC_AHB_PUR_R   (*((volatile u32 *)0x4005A510))
 
#define GPIO_PORTC_AHB_PDR_R   (*((volatile u32 *)0x4005A514))
 
#define GPIO_PORTC_AHB_SLR_R   (*((volatile u32 *)0x4005A518))
 
#define GPIO_PORTC_AHB_DEN_R   (*((volatile u32 *)0x4005A51C))
 
#define GPIO_PORTC_AHB_LOCK_R   (*((volatile u32 *)0x4005A520))
 
#define GPIO_PORTC_AHB_CR_R   (*((volatile u32 *)0x4005A524))
 
#define GPIO_PORTC_AHB_AMSEL_R   (*((volatile u32 *)0x4005A528))
 
#define GPIO_PORTC_AHB_PCTL_R   (*((volatile u32 *)0x4005A52C))
 
#define GPIO_PORTC_AHB_ADCCTL_R   (*((volatile u32 *)0x4005A530))
 
#define GPIO_PORTC_AHB_DMACTL_R   (*((volatile u32 *)0x4005A534))
 
#define GPIO_PORTD_AHB_DATA_BITS_R    ((volatile u32 *)0x4005B000)
 
#define GPIO_PORTD_AHB_DATA_R   (*((volatile u32 *)0x4005B3FC))
 
#define GPIO_PORTD_AHB_DIR_R   (*((volatile u32 *)0x4005B400))
 
#define GPIO_PORTD_AHB_IS_R   (*((volatile u32 *)0x4005B404))
 
#define GPIO_PORTD_AHB_IBE_R   (*((volatile u32 *)0x4005B408))
 
#define GPIO_PORTD_AHB_IEV_R   (*((volatile u32 *)0x4005B40C))
 
#define GPIO_PORTD_AHB_IM_R   (*((volatile u32 *)0x4005B410))
 
#define GPIO_PORTD_AHB_RIS_R   (*((volatile u32 *)0x4005B414))
 
#define GPIO_PORTD_AHB_MIS_R   (*((volatile u32 *)0x4005B418))
 
#define GPIO_PORTD_AHB_ICR_R   (*((volatile u32 *)0x4005B41C))
 
#define GPIO_PORTD_AHB_AFSEL_R   (*((volatile u32 *)0x4005B420))
 
#define GPIO_PORTD_AHB_DR2R_R   (*((volatile u32 *)0x4005B500))
 
#define GPIO_PORTD_AHB_DR4R_R   (*((volatile u32 *)0x4005B504))
 
#define GPIO_PORTD_AHB_DR8R_R   (*((volatile u32 *)0x4005B508))
 
#define GPIO_PORTD_AHB_ODR_R   (*((volatile u32 *)0x4005B50C))
 
#define GPIO_PORTD_AHB_PUR_R   (*((volatile u32 *)0x4005B510))
 
#define GPIO_PORTD_AHB_PDR_R   (*((volatile u32 *)0x4005B514))
 
#define GPIO_PORTD_AHB_SLR_R   (*((volatile u32 *)0x4005B518))
 
#define GPIO_PORTD_AHB_DEN_R   (*((volatile u32 *)0x4005B51C))
 
#define GPIO_PORTD_AHB_LOCK_R   (*((volatile u32 *)0x4005B520))
 
#define GPIO_PORTD_AHB_CR_R   (*((volatile u32 *)0x4005B524))
 
#define GPIO_PORTD_AHB_AMSEL_R   (*((volatile u32 *)0x4005B528))
 
#define GPIO_PORTD_AHB_PCTL_R   (*((volatile u32 *)0x4005B52C))
 
#define GPIO_PORTD_AHB_ADCCTL_R   (*((volatile u32 *)0x4005B530))
 
#define GPIO_PORTD_AHB_DMACTL_R   (*((volatile u32 *)0x4005B534))
 
#define GPIO_PORTE_AHB_DATA_BITS_R    ((volatile u32 *)0x4005C000)
 
#define GPIO_PORTE_AHB_DATA_R   (*((volatile u32 *)0x4005C3FC))
 
#define GPIO_PORTE_AHB_DIR_R   (*((volatile u32 *)0x4005C400))
 
#define GPIO_PORTE_AHB_IS_R   (*((volatile u32 *)0x4005C404))
 
#define GPIO_PORTE_AHB_IBE_R   (*((volatile u32 *)0x4005C408))
 
#define GPIO_PORTE_AHB_IEV_R   (*((volatile u32 *)0x4005C40C))
 
#define GPIO_PORTE_AHB_IM_R   (*((volatile u32 *)0x4005C410))
 
#define GPIO_PORTE_AHB_RIS_R   (*((volatile u32 *)0x4005C414))
 
#define GPIO_PORTE_AHB_MIS_R   (*((volatile u32 *)0x4005C418))
 
#define GPIO_PORTE_AHB_ICR_R   (*((volatile u32 *)0x4005C41C))
 
#define GPIO_PORTE_AHB_AFSEL_R   (*((volatile u32 *)0x4005C420))
 
#define GPIO_PORTE_AHB_DR2R_R   (*((volatile u32 *)0x4005C500))
 
#define GPIO_PORTE_AHB_DR4R_R   (*((volatile u32 *)0x4005C504))
 
#define GPIO_PORTE_AHB_DR8R_R   (*((volatile u32 *)0x4005C508))
 
#define GPIO_PORTE_AHB_ODR_R   (*((volatile u32 *)0x4005C50C))
 
#define GPIO_PORTE_AHB_PUR_R   (*((volatile u32 *)0x4005C510))
 
#define GPIO_PORTE_AHB_PDR_R   (*((volatile u32 *)0x4005C514))
 
#define GPIO_PORTE_AHB_SLR_R   (*((volatile u32 *)0x4005C518))
 
#define GPIO_PORTE_AHB_DEN_R   (*((volatile u32 *)0x4005C51C))
 
#define GPIO_PORTE_AHB_LOCK_R   (*((volatile u32 *)0x4005C520))
 
#define GPIO_PORTE_AHB_CR_R   (*((volatile u32 *)0x4005C524))
 
#define GPIO_PORTE_AHB_AMSEL_R   (*((volatile u32 *)0x4005C528))
 
#define GPIO_PORTE_AHB_PCTL_R   (*((volatile u32 *)0x4005C52C))
 
#define GPIO_PORTE_AHB_ADCCTL_R   (*((volatile u32 *)0x4005C530))
 
#define GPIO_PORTE_AHB_DMACTL_R   (*((volatile u32 *)0x4005C534))
 
#define GPIO_PORTF_AHB_DATA_BITS_R    ((volatile u32 *)0x4005D000)
 
#define GPIO_PORTF_AHB_DATA_R   (*((volatile u32 *)0x4005D3FC))
 
#define GPIO_PORTF_AHB_DIR_R   (*((volatile u32 *)0x4005D400))
 
#define GPIO_PORTF_AHB_IS_R   (*((volatile u32 *)0x4005D404))
 
#define GPIO_PORTF_AHB_IBE_R   (*((volatile u32 *)0x4005D408))
 
#define GPIO_PORTF_AHB_IEV_R   (*((volatile u32 *)0x4005D40C))
 
#define GPIO_PORTF_AHB_IM_R   (*((volatile u32 *)0x4005D410))
 
#define GPIO_PORTF_AHB_RIS_R   (*((volatile u32 *)0x4005D414))
 
#define GPIO_PORTF_AHB_MIS_R   (*((volatile u32 *)0x4005D418))
 
#define GPIO_PORTF_AHB_ICR_R   (*((volatile u32 *)0x4005D41C))
 
#define GPIO_PORTF_AHB_AFSEL_R   (*((volatile u32 *)0x4005D420))
 
#define GPIO_PORTF_AHB_DR2R_R   (*((volatile u32 *)0x4005D500))
 
#define GPIO_PORTF_AHB_DR4R_R   (*((volatile u32 *)0x4005D504))
 
#define GPIO_PORTF_AHB_DR8R_R   (*((volatile u32 *)0x4005D508))
 
#define GPIO_PORTF_AHB_ODR_R   (*((volatile u32 *)0x4005D50C))
 
#define GPIO_PORTF_AHB_PUR_R   (*((volatile u32 *)0x4005D510))
 
#define GPIO_PORTF_AHB_PDR_R   (*((volatile u32 *)0x4005D514))
 
#define GPIO_PORTF_AHB_SLR_R   (*((volatile u32 *)0x4005D518))
 
#define GPIO_PORTF_AHB_DEN_R   (*((volatile u32 *)0x4005D51C))
 
#define GPIO_PORTF_AHB_LOCK_R   (*((volatile u32 *)0x4005D520))
 
#define GPIO_PORTF_AHB_CR_R   (*((volatile u32 *)0x4005D524))
 
#define GPIO_PORTF_AHB_AMSEL_R   (*((volatile u32 *)0x4005D528))
 
#define GPIO_PORTF_AHB_PCTL_R   (*((volatile u32 *)0x4005D52C))
 
#define GPIO_PORTF_AHB_ADCCTL_R   (*((volatile u32 *)0x4005D530))
 
#define GPIO_PORTF_AHB_DMACTL_R   (*((volatile u32 *)0x4005D534))
 
#define EEPROM_EESIZE_R   (*((volatile u32 *)0x400AF000))
 
#define EEPROM_EEBLOCK_R   (*((volatile u32 *)0x400AF004))
 
#define EEPROM_EEOFFSET_R   (*((volatile u32 *)0x400AF008))
 
#define EEPROM_EERDWR_R   (*((volatile u32 *)0x400AF010))
 
#define EEPROM_EERDWRINC_R   (*((volatile u32 *)0x400AF014))
 
#define EEPROM_EEDONE_R   (*((volatile u32 *)0x400AF018))
 
#define EEPROM_EESUPP_R   (*((volatile u32 *)0x400AF01C))
 
#define EEPROM_EEUNLOCK_R   (*((volatile u32 *)0x400AF020))
 
#define EEPROM_EEPROT_R   (*((volatile u32 *)0x400AF030))
 
#define EEPROM_EEPASS0_R   (*((volatile u32 *)0x400AF034))
 
#define EEPROM_EEPASS1_R   (*((volatile u32 *)0x400AF038))
 
#define EEPROM_EEPASS2_R   (*((volatile u32 *)0x400AF03C))
 
#define EEPROM_EEINT_R   (*((volatile u32 *)0x400AF040))
 
#define EEPROM_EEHIDE_R   (*((volatile u32 *)0x400AF050))
 
#define EEPROM_EEDBGME_R   (*((volatile u32 *)0x400AF080))
 
#define EEPROM_PP_R   (*((volatile u32 *)0x400AFFC0))
 
#define SYSEXC_RIS_R   (*((volatile u32 *)0x400F9000))
 
#define SYSEXC_IM_R   (*((volatile u32 *)0x400F9004))
 
#define SYSEXC_MIS_R   (*((volatile u32 *)0x400F9008))
 
#define SYSEXC_IC_R   (*((volatile u32 *)0x400F900C))
 
#define HIB_RTCC_R   (*((volatile u32 *)0x400FC000))
 
#define HIB_RTCM0_R   (*((volatile u32 *)0x400FC004))
 
#define HIB_RTCLD_R   (*((volatile u32 *)0x400FC00C))
 
#define HIB_CTL_R   (*((volatile u32 *)0x400FC010))
 
#define HIB_IM_R   (*((volatile u32 *)0x400FC014))
 
#define HIB_RIS_R   (*((volatile u32 *)0x400FC018))
 
#define HIB_MIS_R   (*((volatile u32 *)0x400FC01C))
 
#define HIB_IC_R   (*((volatile u32 *)0x400FC020))
 
#define HIB_RTCT_R   (*((volatile u32 *)0x400FC024))
 
#define HIB_RTCSS_R   (*((volatile u32 *)0x400FC028))
 
#define HIB_DATA_R   (*((volatile u32 *)0x400FC030))
 
#define FLASH_FMA_R   (*((volatile u32 *)0x400FD000))
 
#define FLASH_FMD_R   (*((volatile u32 *)0x400FD004))
 
#define FLASH_FMC_R   (*((volatile u32 *)0x400FD008))
 
#define FLASH_FCRIS_R   (*((volatile u32 *)0x400FD00C))
 
#define FLASH_FCIM_R   (*((volatile u32 *)0x400FD010))
 
#define FLASH_FCMISC_R   (*((volatile u32 *)0x400FD014))
 
#define FLASH_FMC2_R   (*((volatile u32 *)0x400FD020))
 
#define FLASH_FWBVAL_R   (*((volatile u32 *)0x400FD030))
 
#define FLASH_FWBN_R   (*((volatile u32 *)0x400FD100))
 
#define FLASH_FSIZE_R   (*((volatile u32 *)0x400FDFC0))
 
#define FLASH_SSIZE_R   (*((volatile u32 *)0x400FDFC4))
 
#define FLASH_ROMSWMAP_R   (*((volatile u32 *)0x400FDFCC))
 
#define FLASH_RMCTL_R   (*((volatile u32 *)0x400FE0F0))
 
#define FLASH_BOOTCFG_R   (*((volatile u32 *)0x400FE1D0))
 
#define FLASH_USERREG0_R   (*((volatile u32 *)0x400FE1E0))
 
#define FLASH_USERREG1_R   (*((volatile u32 *)0x400FE1E4))
 
#define FLASH_USERREG2_R   (*((volatile u32 *)0x400FE1E8))
 
#define FLASH_USERREG3_R   (*((volatile u32 *)0x400FE1EC))
 
#define FLASH_FMPRE0_R   (*((volatile u32 *)0x400FE200))
 
#define FLASH_FMPRE1_R   (*((volatile u32 *)0x400FE204))
 
#define FLASH_FMPRE2_R   (*((volatile u32 *)0x400FE208))
 
#define FLASH_FMPRE3_R   (*((volatile u32 *)0x400FE20C))
 
#define FLASH_FMPPE0_R   (*((volatile u32 *)0x400FE400))
 
#define FLASH_FMPPE1_R   (*((volatile u32 *)0x400FE404))
 
#define FLASH_FMPPE2_R   (*((volatile u32 *)0x400FE408))
 
#define FLASH_FMPPE3_R   (*((volatile u32 *)0x400FE40C))
 
#define SYSCTL_DID0_R   (*((volatile u32 *)0x400FE000))
 
#define SYSCTL_DID1_R   (*((volatile u32 *)0x400FE004))
 
#define SYSCTL_DC0_R   (*((volatile u32 *)0x400FE008))
 
#define SYSCTL_DC1_R   (*((volatile u32 *)0x400FE010))
 
#define SYSCTL_DC2_R   (*((volatile u32 *)0x400FE014))
 
#define SYSCTL_DC3_R   (*((volatile u32 *)0x400FE018))
 
#define SYSCTL_DC4_R   (*((volatile u32 *)0x400FE01C))
 
#define SYSCTL_DC5_R   (*((volatile u32 *)0x400FE020))
 
#define SYSCTL_DC6_R   (*((volatile u32 *)0x400FE024))
 
#define SYSCTL_DC7_R   (*((volatile u32 *)0x400FE028))
 
#define SYSCTL_DC8_R   (*((volatile u32 *)0x400FE02C))
 
#define SYSCTL_PBORCTL_R   (*((volatile u32 *)0x400FE030))
 
#define SYSCTL_SRCR0_R   (*((volatile u32 *)0x400FE040))
 
#define SYSCTL_SRCR1_R   (*((volatile u32 *)0x400FE044))
 
#define SYSCTL_SRCR2_R   (*((volatile u32 *)0x400FE048))
 
#define SYSCTL_RIS_R   (*((volatile u32 *)0x400FE050))
 
#define SYSCTL_IMC_R   (*((volatile u32 *)0x400FE054))
 
#define SYSCTL_MISC_R   (*((volatile u32 *)0x400FE058))
 
#define SYSCTL_RESC_R   (*((volatile u32 *)0x400FE05C))
 
#define SYSCTL_RCC_R   (*((volatile u32 *)0x400FE060))
 
#define SYSCTL_GPIOHBCTL_R   (*((volatile u32 *)0x400FE06C))
 
#define SYSCTL_RCC2_R   (*((volatile u32 *)0x400FE070))
 
#define SYSCTL_MOSCCTL_R   (*((volatile u32 *)0x400FE07C))
 
#define SYSCTL_RCGC0_R   (*((volatile u32 *)0x400FE100))
 
#define SYSCTL_RCGC1_R   (*((volatile u32 *)0x400FE104))
 
#define SYSCTL_RCGC2_R   (*((volatile u32 *)0x400FE108))
 
#define SYSCTL_SCGC0_R   (*((volatile u32 *)0x400FE110))
 
#define SYSCTL_SCGC1_R   (*((volatile u32 *)0x400FE114))
 
#define SYSCTL_SCGC2_R   (*((volatile u32 *)0x400FE118))
 
#define SYSCTL_DCGC0_R   (*((volatile u32 *)0x400FE120))
 
#define SYSCTL_DCGC1_R   (*((volatile u32 *)0x400FE124))
 
#define SYSCTL_DCGC2_R   (*((volatile u32 *)0x400FE128))
 
#define SYSCTL_DSLPCLKCFG_R   (*((volatile u32 *)0x400FE144))
 
#define SYSCTL_SYSPROP_R   (*((volatile u32 *)0x400FE14C))
 
#define SYSCTL_PIOSCCAL_R   (*((volatile u32 *)0x400FE150))
 
#define SYSCTL_PIOSCSTAT_R   (*((volatile u32 *)0x400FE154))
 
#define SYSCTL_PLLFREQ0_R   (*((volatile u32 *)0x400FE160))
 
#define SYSCTL_PLLFREQ1_R   (*((volatile u32 *)0x400FE164))
 
#define SYSCTL_PLLSTAT_R   (*((volatile u32 *)0x400FE168))
 
#define SYSCTL_SLPPWRCFG_R   (*((volatile u32 *)0x400FE188))
 
#define SYSCTL_DSLPPWRCFG_R   (*((volatile u32 *)0x400FE18C))
 
#define SYSCTL_DC9_R   (*((volatile u32 *)0x400FE190))
 
#define SYSCTL_NVMSTAT_R   (*((volatile u32 *)0x400FE1A0))
 
#define SYSCTL_LDOSPCTL_R   (*((volatile u32 *)0x400FE1B4))
 
#define SYSCTL_LDODPCTL_R   (*((volatile u32 *)0x400FE1BC))
 
#define SYSCTL_PPWD_R   (*((volatile u32 *)0x400FE300))
 
#define SYSCTL_PPTIMER_R   (*((volatile u32 *)0x400FE304))
 
#define SYSCTL_PPGPIO_R   (*((volatile u32 *)0x400FE308))
 
#define SYSCTL_PPDMA_R   (*((volatile u32 *)0x400FE30C))
 
#define SYSCTL_PPHIB_R   (*((volatile u32 *)0x400FE314))
 
#define SYSCTL_PPUART_R   (*((volatile u32 *)0x400FE318))
 
#define SYSCTL_PPSSI_R   (*((volatile u32 *)0x400FE31C))
 
#define SYSCTL_PPI2C_R   (*((volatile u32 *)0x400FE320))
 
#define SYSCTL_PPUSB_R   (*((volatile u32 *)0x400FE328))
 
#define SYSCTL_PPCAN_R   (*((volatile u32 *)0x400FE334))
 
#define SYSCTL_PPADC_R   (*((volatile u32 *)0x400FE338))
 
#define SYSCTL_PPACMP_R   (*((volatile u32 *)0x400FE33C))
 
#define SYSCTL_PPPWM_R   (*((volatile u32 *)0x400FE340))
 
#define SYSCTL_PPQEI_R   (*((volatile u32 *)0x400FE344))
 
#define SYSCTL_PPEEPROM_R   (*((volatile u32 *)0x400FE358))
 
#define SYSCTL_PPWTIMER_R   (*((volatile u32 *)0x400FE35C))
 
#define SYSCTL_SRWD_R   (*((volatile u32 *)0x400FE500))
 
#define SYSCTL_SRTIMER_R   (*((volatile u32 *)0x400FE504))
 
#define SYSCTL_SRGPIO_R   (*((volatile u32 *)0x400FE508))
 
#define SYSCTL_SRDMA_R   (*((volatile u32 *)0x400FE50C))
 
#define SYSCTL_SRHIB_R   (*((volatile u32 *)0x400FE514))
 
#define SYSCTL_SRUART_R   (*((volatile u32 *)0x400FE518))
 
#define SYSCTL_SRSSI_R   (*((volatile u32 *)0x400FE51C))
 
#define SYSCTL_SRI2C_R   (*((volatile u32 *)0x400FE520))
 
#define SYSCTL_SRUSB_R   (*((volatile u32 *)0x400FE528))
 
#define SYSCTL_SRCAN_R   (*((volatile u32 *)0x400FE534))
 
#define SYSCTL_SRADC_R   (*((volatile u32 *)0x400FE538))
 
#define SYSCTL_SRACMP_R   (*((volatile u32 *)0x400FE53C))
 
#define SYSCTL_SRPWM_R   (*((volatile u32 *)0x400FE540))
 
#define SYSCTL_SRQEI_R   (*((volatile u32 *)0x400FE544))
 
#define SYSCTL_SREEPROM_R   (*((volatile u32 *)0x400FE558))
 
#define SYSCTL_SRWTIMER_R   (*((volatile u32 *)0x400FE55C))
 
#define SYSCTL_RCGCWD_R   (*((volatile u32 *)0x400FE600))
 
#define SYSCTL_RCGCTIMER_R   (*((volatile u32 *)0x400FE604))
 
#define SYSCTL_RCGCGPIO_R   (*((volatile u32 *)0x400FE608))
 
#define SYSCTL_RCGCDMA_R   (*((volatile u32 *)0x400FE60C))
 
#define SYSCTL_RCGCHIB_R   (*((volatile u32 *)0x400FE614))
 
#define SYSCTL_RCGCUART_R   (*((volatile u32 *)0x400FE618))
 
#define SYSCTL_RCGCSSI_R   (*((volatile u32 *)0x400FE61C))
 
#define SYSCTL_RCGCI2C_R   (*((volatile u32 *)0x400FE620))
 
#define SYSCTL_RCGCUSB_R   (*((volatile u32 *)0x400FE628))
 
#define SYSCTL_RCGCCAN_R   (*((volatile u32 *)0x400FE634))
 
#define SYSCTL_RCGCADC_R   (*((volatile u32 *)0x400FE638))
 
#define SYSCTL_RCGCACMP_R   (*((volatile u32 *)0x400FE63C))
 
#define SYSCTL_RCGCPWM_R   (*((volatile u32 *)0x400FE640))
 
#define SYSCTL_RCGCQEI_R   (*((volatile u32 *)0x400FE644))
 
#define SYSCTL_RCGCEEPROM_R   (*((volatile u32 *)0x400FE658))
 
#define SYSCTL_RCGCWTIMER_R   (*((volatile u32 *)0x400FE65C))
 
#define SYSCTL_SCGCWD_R   (*((volatile u32 *)0x400FE700))
 
#define SYSCTL_SCGCTIMER_R   (*((volatile u32 *)0x400FE704))
 
#define SYSCTL_SCGCGPIO_R   (*((volatile u32 *)0x400FE708))
 
#define SYSCTL_SCGCDMA_R   (*((volatile u32 *)0x400FE70C))
 
#define SYSCTL_SCGCHIB_R   (*((volatile u32 *)0x400FE714))
 
#define SYSCTL_SCGCUART_R   (*((volatile u32 *)0x400FE718))
 
#define SYSCTL_SCGCSSI_R   (*((volatile u32 *)0x400FE71C))
 
#define SYSCTL_SCGCI2C_R   (*((volatile u32 *)0x400FE720))
 
#define SYSCTL_SCGCUSB_R   (*((volatile u32 *)0x400FE728))
 
#define SYSCTL_SCGCCAN_R   (*((volatile u32 *)0x400FE734))
 
#define SYSCTL_SCGCADC_R   (*((volatile u32 *)0x400FE738))
 
#define SYSCTL_SCGCACMP_R   (*((volatile u32 *)0x400FE73C))
 
#define SYSCTL_SCGCPWM_R   (*((volatile u32 *)0x400FE740))
 
#define SYSCTL_SCGCQEI_R   (*((volatile u32 *)0x400FE744))
 
#define SYSCTL_SCGCEEPROM_R   (*((volatile u32 *)0x400FE758))
 
#define SYSCTL_SCGCWTIMER_R   (*((volatile u32 *)0x400FE75C))
 
#define SYSCTL_DCGCWD_R   (*((volatile u32 *)0x400FE800))
 
#define SYSCTL_DCGCTIMER_R   (*((volatile u32 *)0x400FE804))
 
#define SYSCTL_DCGCGPIO_R   (*((volatile u32 *)0x400FE808))
 
#define SYSCTL_DCGCDMA_R   (*((volatile u32 *)0x400FE80C))
 
#define SYSCTL_DCGCHIB_R   (*((volatile u32 *)0x400FE814))
 
#define SYSCTL_DCGCUART_R   (*((volatile u32 *)0x400FE818))
 
#define SYSCTL_DCGCSSI_R   (*((volatile u32 *)0x400FE81C))
 
#define SYSCTL_DCGCI2C_R   (*((volatile u32 *)0x400FE820))
 
#define SYSCTL_DCGCUSB_R   (*((volatile u32 *)0x400FE828))
 
#define SYSCTL_DCGCCAN_R   (*((volatile u32 *)0x400FE834))
 
#define SYSCTL_DCGCADC_R   (*((volatile u32 *)0x400FE838))
 
#define SYSCTL_DCGCACMP_R   (*((volatile u32 *)0x400FE83C))
 
#define SYSCTL_DCGCPWM_R   (*((volatile u32 *)0x400FE840))
 
#define SYSCTL_DCGCQEI_R   (*((volatile u32 *)0x400FE844))
 
#define SYSCTL_DCGCEEPROM_R   (*((volatile u32 *)0x400FE858))
 
#define SYSCTL_DCGCWTIMER_R   (*((volatile u32 *)0x400FE85C))
 
#define SYSCTL_PRWD_R   (*((volatile u32 *)0x400FEA00))
 
#define SYSCTL_PRTIMER_R   (*((volatile u32 *)0x400FEA04))
 
#define SYSCTL_PRGPIO_R   (*((volatile u32 *)0x400FEA08))
 
#define SYSCTL_PRDMA_R   (*((volatile u32 *)0x400FEA0C))
 
#define SYSCTL_PRHIB_R   (*((volatile u32 *)0x400FEA14))
 
#define SYSCTL_PRUART_R   (*((volatile u32 *)0x400FEA18))
 
#define SYSCTL_PRSSI_R   (*((volatile u32 *)0x400FEA1C))
 
#define SYSCTL_PRI2C_R   (*((volatile u32 *)0x400FEA20))
 
#define SYSCTL_PRUSB_R   (*((volatile u32 *)0x400FEA28))
 
#define SYSCTL_PRCAN_R   (*((volatile u32 *)0x400FEA34))
 
#define SYSCTL_PRADC_R   (*((volatile u32 *)0x400FEA38))
 
#define SYSCTL_PRACMP_R   (*((volatile u32 *)0x400FEA3C))
 
#define SYSCTL_PRPWM_R   (*((volatile u32 *)0x400FEA40))
 
#define SYSCTL_PRQEI_R   (*((volatile u32 *)0x400FEA44))
 
#define SYSCTL_PREEPROM_R   (*((volatile u32 *)0x400FEA58))
 
#define SYSCTL_PRWTIMER_R   (*((volatile u32 *)0x400FEA5C))
 
#define UDMA_STAT_R   (*((volatile u32 *)0x400FF000))
 
#define UDMA_CFG_R   (*((volatile u32 *)0x400FF004))
 
#define UDMA_CTLBASE_R   (*((volatile u32 *)0x400FF008))
 
#define UDMA_ALTBASE_R   (*((volatile u32 *)0x400FF00C))
 
#define UDMA_WAITSTAT_R   (*((volatile u32 *)0x400FF010))
 
#define UDMA_SWREQ_R   (*((volatile u32 *)0x400FF014))
 
#define UDMA_USEBURSTSET_R   (*((volatile u32 *)0x400FF018))
 
#define UDMA_USEBURSTCLR_R   (*((volatile u32 *)0x400FF01C))
 
#define UDMA_REQMASKSET_R   (*((volatile u32 *)0x400FF020))
 
#define UDMA_REQMASKCLR_R   (*((volatile u32 *)0x400FF024))
 
#define UDMA_ENASET_R   (*((volatile u32 *)0x400FF028))
 
#define UDMA_ENACLR_R   (*((volatile u32 *)0x400FF02C))
 
#define UDMA_ALTSET_R   (*((volatile u32 *)0x400FF030))
 
#define UDMA_ALTCLR_R   (*((volatile u32 *)0x400FF034))
 
#define UDMA_PRIOSET_R   (*((volatile u32 *)0x400FF038))
 
#define UDMA_PRIOCLR_R   (*((volatile u32 *)0x400FF03C))
 
#define UDMA_ERRCLR_R   (*((volatile u32 *)0x400FF04C))
 
#define UDMA_CHASGN_R   (*((volatile u32 *)0x400FF500))
 
#define UDMA_CHIS_R   (*((volatile u32 *)0x400FF504))
 
#define UDMA_CHMAP0_R   (*((volatile u32 *)0x400FF510))
 
#define UDMA_CHMAP1_R   (*((volatile u32 *)0x400FF514))
 
#define UDMA_CHMAP2_R   (*((volatile u32 *)0x400FF518))
 
#define UDMA_CHMAP3_R   (*((volatile u32 *)0x400FF51C))
 
#define UDMA_SRCENDP   0x00000000
 
#define UDMA_DSTENDP   0x00000004
 
#define UDMA_CHCTL   0x00000008
 
#define NVIC_ACTLR_R   (*((volatile u32 *)0xE000E008))
 
#define NVIC_ST_CTRL_R   (*((volatile u32 *)0xE000E010))
 
#define NVIC_ST_RELOAD_R   (*((volatile u32 *)0xE000E014))
 
#define NVIC_ST_CURRENT_R   (*((volatile u32 *)0xE000E018))
 
#define NVIC_EN0_R   (*((volatile u32 *)0xE000E100))
 
#define NVIC_EN1_R   (*((volatile u32 *)0xE000E104))
 
#define NVIC_EN2_R   (*((volatile u32 *)0xE000E108))
 
#define NVIC_EN3_R   (*((volatile u32 *)0xE000E10C))
 
#define NVIC_EN4_R   (*((volatile u32 *)0xE000E110))
 
#define NVIC_DIS0_R   (*((volatile u32 *)0xE000E180))
 
#define NVIC_DIS1_R   (*((volatile u32 *)0xE000E184))
 
#define NVIC_DIS2_R   (*((volatile u32 *)0xE000E188))
 
#define NVIC_DIS3_R   (*((volatile u32 *)0xE000E18C))
 
#define NVIC_DIS4_R   (*((volatile u32 *)0xE000E190))
 
#define NVIC_PEND0_R   (*((volatile u32 *)0xE000E200))
 
#define NVIC_PEND1_R   (*((volatile u32 *)0xE000E204))
 
#define NVIC_PEND2_R   (*((volatile u32 *)0xE000E208))
 
#define NVIC_PEND3_R   (*((volatile u32 *)0xE000E20C))
 
#define NVIC_PEND4_R   (*((volatile u32 *)0xE000E210))
 
#define NVIC_UNPEND0_R   (*((volatile u32 *)0xE000E280))
 
#define NVIC_UNPEND1_R   (*((volatile u32 *)0xE000E284))
 
#define NVIC_UNPEND2_R   (*((volatile u32 *)0xE000E288))
 
#define NVIC_UNPEND3_R   (*((volatile u32 *)0xE000E28C))
 
#define NVIC_UNPEND4_R   (*((volatile u32 *)0xE000E290))
 
#define NVIC_ACTIVE0_R   (*((volatile u32 *)0xE000E300))
 
#define NVIC_ACTIVE1_R   (*((volatile u32 *)0xE000E304))
 
#define NVIC_ACTIVE2_R   (*((volatile u32 *)0xE000E308))
 
#define NVIC_ACTIVE3_R   (*((volatile u32 *)0xE000E30C))
 
#define NVIC_ACTIVE4_R   (*((volatile u32 *)0xE000E310))
 
#define NVIC_PRI0_R   (*((volatile u32 *)0xE000E400))
 
#define NVIC_PRI1_R   (*((volatile u32 *)0xE000E404))
 
#define NVIC_PRI2_R   (*((volatile u32 *)0xE000E408))
 
#define NVIC_PRI3_R   (*((volatile u32 *)0xE000E40C))
 
#define NVIC_PRI4_R   (*((volatile u32 *)0xE000E410))
 
#define NVIC_PRI5_R   (*((volatile u32 *)0xE000E414))
 
#define NVIC_PRI6_R   (*((volatile u32 *)0xE000E418))
 
#define NVIC_PRI7_R   (*((volatile u32 *)0xE000E41C))
 
#define NVIC_PRI8_R   (*((volatile u32 *)0xE000E420))
 
#define NVIC_PRI9_R   (*((volatile u32 *)0xE000E424))
 
#define NVIC_PRI10_R   (*((volatile u32 *)0xE000E428))
 
#define NVIC_PRI11_R   (*((volatile u32 *)0xE000E42C))
 
#define NVIC_PRI12_R   (*((volatile u32 *)0xE000E430))
 
#define NVIC_PRI13_R   (*((volatile u32 *)0xE000E434))
 
#define NVIC_PRI14_R   (*((volatile u32 *)0xE000E438))
 
#define NVIC_PRI15_R   (*((volatile u32 *)0xE000E43C))
 
#define NVIC_PRI16_R   (*((volatile u32 *)0xE000E440))
 
#define NVIC_PRI17_R   (*((volatile u32 *)0xE000E444))
 
#define NVIC_PRI18_R   (*((volatile u32 *)0xE000E448))
 
#define NVIC_PRI19_R   (*((volatile u32 *)0xE000E44C))
 
#define NVIC_PRI20_R   (*((volatile u32 *)0xE000E450))
 
#define NVIC_PRI21_R   (*((volatile u32 *)0xE000E454))
 
#define NVIC_PRI22_R   (*((volatile u32 *)0xE000E458))
 
#define NVIC_PRI23_R   (*((volatile u32 *)0xE000E45C))
 
#define NVIC_PRI24_R   (*((volatile u32 *)0xE000E460))
 
#define NVIC_PRI25_R   (*((volatile u32 *)0xE000E464))
 
#define NVIC_PRI26_R   (*((volatile u32 *)0xE000E468))
 
#define NVIC_PRI27_R   (*((volatile u32 *)0xE000E46C))
 
#define NVIC_PRI28_R   (*((volatile u32 *)0xE000E470))
 
#define NVIC_PRI29_R   (*((volatile u32 *)0xE000E474))
 
#define NVIC_PRI30_R   (*((volatile u32 *)0xE000E478))
 
#define NVIC_PRI31_R   (*((volatile u32 *)0xE000E47C))
 
#define NVIC_PRI32_R   (*((volatile u32 *)0xE000E480))
 
#define NVIC_PRI33_R   (*((volatile u32 *)0xE000E484))
 
#define NVIC_PRI34_R   (*((volatile u32 *)0xE000E488))
 
#define NVIC_CPUID_R   (*((volatile u32 *)0xE000ED00))
 
#define NVIC_INT_CTRL_R   (*((volatile u32 *)0xE000ED04))
 
#define NVIC_VTABLE_R   (*((volatile u32 *)0xE000ED08))
 
#define NVIC_APINT_R   (*((volatile u32 *)0xE000ED0C))
 
#define NVIC_SYS_CTRL_R   (*((volatile u32 *)0xE000ED10))
 
#define NVIC_CFG_CTRL_R   (*((volatile u32 *)0xE000ED14))
 
#define NVIC_SYS_PRI1_R   (*((volatile u32 *)0xE000ED18))
 
#define NVIC_SYS_PRI2_R   (*((volatile u32 *)0xE000ED1C))
 
#define NVIC_SYS_PRI3_R   (*((volatile u32 *)0xE000ED20))
 
#define NVIC_SYS_HND_CTRL_R   (*((volatile u32 *)0xE000ED24))
 
#define NVIC_FAULT_STAT_R   (*((volatile u32 *)0xE000ED28))
 
#define NVIC_HFAULT_STAT_R   (*((volatile u32 *)0xE000ED2C))
 
#define NVIC_DEBUG_STAT_R   (*((volatile u32 *)0xE000ED30))
 
#define NVIC_MM_ADDR_R   (*((volatile u32 *)0xE000ED34))
 
#define NVIC_FAULT_ADDR_R   (*((volatile u32 *)0xE000ED38))
 
#define NVIC_CPAC_R   (*((volatile u32 *)0xE000ED88))
 
#define NVIC_MPU_TYPE_R   (*((volatile u32 *)0xE000ED90))
 
#define NVIC_MPU_CTRL_R   (*((volatile u32 *)0xE000ED94))
 
#define NVIC_MPU_NUMBER_R   (*((volatile u32 *)0xE000ED98))
 
#define NVIC_MPU_BASE_R   (*((volatile u32 *)0xE000ED9C))
 
#define NVIC_MPU_ATTR_R   (*((volatile u32 *)0xE000EDA0))
 
#define NVIC_MPU_BASE1_R   (*((volatile u32 *)0xE000EDA4))
 
#define NVIC_MPU_ATTR1_R   (*((volatile u32 *)0xE000EDA8))
 
#define NVIC_MPU_BASE2_R   (*((volatile u32 *)0xE000EDAC))
 
#define NVIC_MPU_ATTR2_R   (*((volatile u32 *)0xE000EDB0))
 
#define NVIC_MPU_BASE3_R   (*((volatile u32 *)0xE000EDB4))
 
#define NVIC_MPU_ATTR3_R   (*((volatile u32 *)0xE000EDB8))
 
#define NVIC_DBG_CTRL_R   (*((volatile u32 *)0xE000EDF0))
 
#define NVIC_DBG_XFER_R   (*((volatile u32 *)0xE000EDF4))
 
#define NVIC_DBG_DATA_R   (*((volatile u32 *)0xE000EDF8))
 
#define NVIC_DBG_INT_R   (*((volatile u32 *)0xE000EDFC))
 
#define NVIC_SW_TRIG_R   (*((volatile u32 *)0xE000EF00))
 
#define NVIC_FPCC_R   (*((volatile u32 *)0xE000EF34))
 
#define NVIC_FPCA_R   (*((volatile u32 *)0xE000EF38))
 
#define NVIC_FPDSC_R   (*((volatile u32 *)0xE000EF3C))
 
#define WDT_LOAD_M   0xFFFFFFFF
 
#define WDT_LOAD_S   0
 
#define WDT_VALUE_M   0xFFFFFFFF
 
#define WDT_VALUE_S   0
 
#define WDT_CTL_WRC   0x80000000
 
#define WDT_CTL_INTTYPE   0x00000004
 
#define WDT_CTL_RESEN   0x00000002
 
#define WDT_CTL_INTEN   0x00000001
 
#define WDT_ICR_M   0xFFFFFFFF
 
#define WDT_ICR_S   0
 
#define WDT_RIS_WDTRIS   0x00000001
 
#define WDT_MIS_WDTMIS   0x00000001
 
#define WDT_TEST_STALL   0x00000100
 
#define WDT_LOCK_M   0xFFFFFFFF
 
#define WDT_LOCK_UNLOCKED   0x00000000
 
#define WDT_LOCK_LOCKED   0x00000001
 
#define WDT_LOCK_UNLOCK   0x1ACCE551
 
#define GPIO_IM_GPIO_M   0x000000FF
 
#define GPIO_IM_GPIO_S   0
 
#define GPIO_RIS_GPIO_M   0x000000FF
 
#define GPIO_RIS_GPIO_S   0
 
#define GPIO_MIS_GPIO_M   0x000000FF
 
#define GPIO_MIS_GPIO_S   0
 
#define GPIO_ICR_GPIO_M   0x000000FF
 
#define GPIO_ICR_GPIO_S   0
 
#define GPIO_LOCK_M   0xFFFFFFFF
 
#define GPIO_LOCK_UNLOCKED   0x00000000
 
#define GPIO_LOCK_LOCKED   0x00000001
 
#define GPIO_LOCK_KEY   0x4C4F434B
 
#define GPIO_PCTL_PA7_M   0xF0000000
 
#define GPIO_PCTL_PA7_I2C1SDA   0x30000000
 
#define GPIO_PCTL_PA7_M1PWM3   0x50000000
 
#define GPIO_PCTL_PA6_M   0x0F000000
 
#define GPIO_PCTL_PA6_I2C1SCL   0x03000000
 
#define GPIO_PCTL_PA6_M1PWM2   0x05000000
 
#define GPIO_PCTL_PA5_M   0x00F00000
 
#define GPIO_PCTL_PA5_SSI0TX   0x00200000
 
#define GPIO_PCTL_PA4_M   0x000F0000
 
#define GPIO_PCTL_PA4_SSI0RX   0x00020000
 
#define GPIO_PCTL_PA3_M   0x0000F000
 
#define GPIO_PCTL_PA3_SSI0FSS   0x00002000
 
#define GPIO_PCTL_PA2_M   0x00000F00
 
#define GPIO_PCTL_PA2_SSI0CLK   0x00000200
 
#define GPIO_PCTL_PA1_M   0x000000F0
 
#define GPIO_PCTL_PA1_U0TX   0x00000010
 
#define GPIO_PCTL_PA1_CAN1TX   0x00000080
 
#define GPIO_PCTL_PA0_M   0x0000000F
 
#define GPIO_PCTL_PA0_U0RX   0x00000001
 
#define GPIO_PCTL_PA0_CAN1RX   0x00000008
 
#define GPIO_PCTL_PB7_M   0xF0000000
 
#define GPIO_PCTL_PB7_SSI2TX   0x20000000
 
#define GPIO_PCTL_PB7_M0PWM1   0x40000000
 
#define GPIO_PCTL_PB7_T0CCP1   0x70000000
 
#define GPIO_PCTL_PB6_M   0x0F000000
 
#define GPIO_PCTL_PB6_SSI2RX   0x02000000
 
#define GPIO_PCTL_PB6_M0PWM0   0x04000000
 
#define GPIO_PCTL_PB6_T0CCP0   0x07000000
 
#define GPIO_PCTL_PB5_M   0x00F00000
 
#define GPIO_PCTL_PB5_SSI2FSS   0x00200000
 
#define GPIO_PCTL_PB5_M0PWM3   0x00400000
 
#define GPIO_PCTL_PB5_T1CCP1   0x00700000
 
#define GPIO_PCTL_PB5_CAN0TX   0x00800000
 
#define GPIO_PCTL_PB4_M   0x000F0000
 
#define GPIO_PCTL_PB4_SSI2CLK   0x00020000
 
#define GPIO_PCTL_PB4_M0PWM2   0x00040000
 
#define GPIO_PCTL_PB4_T1CCP0   0x00070000
 
#define GPIO_PCTL_PB4_CAN0RX   0x00080000
 
#define GPIO_PCTL_PB3_M   0x0000F000
 
#define GPIO_PCTL_PB3_I2C0SDA   0x00003000
 
#define GPIO_PCTL_PB3_T3CCP1   0x00007000
 
#define GPIO_PCTL_PB2_M   0x00000F00
 
#define GPIO_PCTL_PB2_I2C0SCL   0x00000300
 
#define GPIO_PCTL_PB2_T3CCP0   0x00000700
 
#define GPIO_PCTL_PB1_M   0x000000F0
 
#define GPIO_PCTL_PB1_USB0VBUS   0x00000000
 
#define GPIO_PCTL_PB1_U1TX   0x00000010
 
#define GPIO_PCTL_PB1_T2CCP1   0x00000070
 
#define GPIO_PCTL_PB0_M   0x0000000F
 
#define GPIO_PCTL_PB0_USB0ID   0x00000000
 
#define GPIO_PCTL_PB0_U1RX   0x00000001
 
#define GPIO_PCTL_PB0_T2CCP0   0x00000007
 
#define GPIO_PCTL_PC7_M   0xF0000000
 
#define GPIO_PCTL_PC7_U3TX   0x10000000
 
#define GPIO_PCTL_PC7_WT1CCP1   0x70000000
 
#define GPIO_PCTL_PC7_USB0PFLT   0x80000000
 
#define GPIO_PCTL_PC6_M   0x0F000000
 
#define GPIO_PCTL_PC6_U3RX   0x01000000
 
#define GPIO_PCTL_PC6_PHB1   0x06000000
 
#define GPIO_PCTL_PC6_WT1CCP0   0x07000000
 
#define GPIO_PCTL_PC6_USB0EPEN   0x08000000
 
#define GPIO_PCTL_PC5_M   0x00F00000
 
#define GPIO_PCTL_PC5_U4TX   0x00100000
 
#define GPIO_PCTL_PC5_U1TX   0x00200000
 
#define GPIO_PCTL_PC5_M0PWM7   0x00400000
 
#define GPIO_PCTL_PC5_PHA1   0x00600000
 
#define GPIO_PCTL_PC5_WT0CCP1   0x00700000
 
#define GPIO_PCTL_PC5_U1CTS   0x00800000
 
#define GPIO_PCTL_PC4_M   0x000F0000
 
#define GPIO_PCTL_PC4_U4RX   0x00010000
 
#define GPIO_PCTL_PC4_U1RX   0x00020000
 
#define GPIO_PCTL_PC4_M0PWM6   0x00040000
 
#define GPIO_PCTL_PC4_IDX1   0x00060000
 
#define GPIO_PCTL_PC4_WT0CCP0   0x00070000
 
#define GPIO_PCTL_PC4_U1RTS   0x00080000
 
#define GPIO_PCTL_PC3_M   0x0000F000
 
#define GPIO_PCTL_PC3_TDO   0x00001000
 
#define GPIO_PCTL_PC3_T5CCP1   0x00007000
 
#define GPIO_PCTL_PC2_M   0x00000F00
 
#define GPIO_PCTL_PC2_TDI   0x00000100
 
#define GPIO_PCTL_PC2_T5CCP0   0x00000700
 
#define GPIO_PCTL_PC1_M   0x000000F0
 
#define GPIO_PCTL_PC1_TMS   0x00000010
 
#define GPIO_PCTL_PC1_T4CCP1   0x00000070
 
#define GPIO_PCTL_PC0_M   0x0000000F
 
#define GPIO_PCTL_PC0_TCK   0x00000001
 
#define GPIO_PCTL_PC0_T4CCP0   0x00000007
 
#define GPIO_PCTL_PD7_M   0xF0000000
 
#define GPIO_PCTL_PD7_U2TX   0x10000000
 
#define GPIO_PCTL_PD7_PHB0   0x60000000
 
#define GPIO_PCTL_PD7_WT5CCP1   0x70000000
 
#define GPIO_PCTL_PD7_NMI   0x80000000
 
#define GPIO_PCTL_PD6_M   0x0F000000
 
#define GPIO_PCTL_PD6_U2RX   0x01000000
 
#define GPIO_PCTL_PD6_M0FAULT0   0x04000000
 
#define GPIO_PCTL_PD6_PHA0   0x06000000
 
#define GPIO_PCTL_PD6_WT5CCP0   0x07000000
 
#define GPIO_PCTL_PD5_M   0x00F00000
 
#define GPIO_PCTL_PD5_USB0DP   0x00000000
 
#define GPIO_PCTL_PD5_U6TX   0x00100000
 
#define GPIO_PCTL_PD5_WT4CCP1   0x00700000
 
#define GPIO_PCTL_PD4_M   0x000F0000
 
#define GPIO_PCTL_PD4_USB0DM   0x00000000
 
#define GPIO_PCTL_PD4_U6RX   0x00010000
 
#define GPIO_PCTL_PD4_WT4CCP0   0x00070000
 
#define GPIO_PCTL_PD3_M   0x0000F000
 
#define GPIO_PCTL_PD3_AIN4   0x00000000
 
#define GPIO_PCTL_PD3_SSI3TX   0x00001000
 
#define GPIO_PCTL_PD3_SSI1TX   0x00002000
 
#define GPIO_PCTL_PD3_IDX0   0x00006000
 
#define GPIO_PCTL_PD3_WT3CCP1   0x00007000
 
#define GPIO_PCTL_PD3_USB0PFLT   0x00008000
 
#define GPIO_PCTL_PD2_M   0x00000F00
 
#define GPIO_PCTL_PD2_AIN5   0x00000000
 
#define GPIO_PCTL_PD2_SSI3RX   0x00000100
 
#define GPIO_PCTL_PD2_SSI1RX   0x00000200
 
#define GPIO_PCTL_PD2_M0FAULT0   0x00000400
 
#define GPIO_PCTL_PD2_WT3CCP0   0x00000700
 
#define GPIO_PCTL_PD2_USB0EPEN   0x00000800
 
#define GPIO_PCTL_PD1_M   0x000000F0
 
#define GPIO_PCTL_PD1_AIN6   0x00000000
 
#define GPIO_PCTL_PD1_SSI3FSS   0x00000010
 
#define GPIO_PCTL_PD1_SSI1FSS   0x00000020
 
#define GPIO_PCTL_PD1_I2C3SDA   0x00000030
 
#define GPIO_PCTL_PD1_M0PWM7   0x00000040
 
#define GPIO_PCTL_PD1_M1PWM1   0x00000050
 
#define GPIO_PCTL_PD1_WT2CCP1   0x00000070
 
#define GPIO_PCTL_PD0_M   0x0000000F
 
#define GPIO_PCTL_PD0_AIN7   0x00000000
 
#define GPIO_PCTL_PD0_SSI3CLK   0x00000001
 
#define GPIO_PCTL_PD0_SSI1CLK   0x00000002
 
#define GPIO_PCTL_PD0_I2C3SCL   0x00000003
 
#define GPIO_PCTL_PD0_M0PWM6   0x00000004
 
#define GPIO_PCTL_PD0_M1PWM0   0x00000005
 
#define GPIO_PCTL_PD0_WT2CCP0   0x00000007
 
#define GPIO_PCTL_PE5_M   0x00F00000
 
#define GPIO_PCTL_PE5_AIN8   0x00000000
 
#define GPIO_PCTL_PE5_U5TX   0x00100000
 
#define GPIO_PCTL_PE5_I2C2SDA   0x00300000
 
#define GPIO_PCTL_PE5_M0PWM5   0x00400000
 
#define GPIO_PCTL_PE5_M1PWM3   0x00500000
 
#define GPIO_PCTL_PE5_CAN0TX   0x00800000
 
#define GPIO_PCTL_PE4_M   0x000F0000
 
#define GPIO_PCTL_PE4_AIN9   0x00000000
 
#define GPIO_PCTL_PE4_U5RX   0x00010000
 
#define GPIO_PCTL_PE4_I2C2SCL   0x00030000
 
#define GPIO_PCTL_PE4_M0PWM4   0x00040000
 
#define GPIO_PCTL_PE4_M1PWM2   0x00050000
 
#define GPIO_PCTL_PE4_CAN0RX   0x00080000
 
#define GPIO_PCTL_PE3_M   0x0000F000
 
#define GPIO_PCTL_PE3_AIN0   0x00000000
 
#define GPIO_PCTL_PE2_M   0x00000F00
 
#define GPIO_PCTL_PE2_AIN1   0x00000000
 
#define GPIO_PCTL_PE1_M   0x000000F0
 
#define GPIO_PCTL_PE1_AIN2   0x00000000
 
#define GPIO_PCTL_PE1_U7TX   0x00000010
 
#define GPIO_PCTL_PE0_M   0x0000000F
 
#define GPIO_PCTL_PE0_AIN3   0x00000000
 
#define GPIO_PCTL_PE0_U7RX   0x00000001
 
#define GPIO_PCTL_PF4_M   0x000F0000
 
#define GPIO_PCTL_PF4_M1FAULT0   0x00050000
 
#define GPIO_PCTL_PF4_IDX0   0x00060000
 
#define GPIO_PCTL_PF4_T2CCP0   0x00070000
 
#define GPIO_PCTL_PF4_USB0EPEN   0x00080000
 
#define GPIO_PCTL_PF3_M   0x0000F000
 
#define GPIO_PCTL_PF3_SSI1FSS   0x00002000
 
#define GPIO_PCTL_PF3_CAN0TX   0x00003000
 
#define GPIO_PCTL_PF3_M1PWM7   0x00005000
 
#define GPIO_PCTL_PF3_T1CCP1   0x00007000
 
#define GPIO_PCTL_PF3_TRCLK   0x0000E000
 
#define GPIO_PCTL_PF2_M   0x00000F00
 
#define GPIO_PCTL_PF2_SSI1CLK   0x00000200
 
#define GPIO_PCTL_PF2_M0FAULT0   0x00000400
 
#define GPIO_PCTL_PF2_M1PWM6   0x00000500
 
#define GPIO_PCTL_PF2_T1CCP0   0x00000700
 
#define GPIO_PCTL_PF2_TRD0   0x00000E00
 
#define GPIO_PCTL_PF1_M   0x000000F0
 
#define GPIO_PCTL_PF1_U1CTS   0x00000010
 
#define GPIO_PCTL_PF1_SSI1TX   0x00000020
 
#define GPIO_PCTL_PF1_M1PWM5   0x00000050
 
#define GPIO_PCTL_PF1_PHB0   0x00000060
 
#define GPIO_PCTL_PF1_T0CCP1   0x00000070
 
#define GPIO_PCTL_PF1_C1O   0x00000090
 
#define GPIO_PCTL_PF1_TRD1   0x000000E0
 
#define GPIO_PCTL_PF0_M   0x0000000F
 
#define GPIO_PCTL_PF0_U1RTS   0x00000001
 
#define GPIO_PCTL_PF0_SSI1RX   0x00000002
 
#define GPIO_PCTL_PF0_CAN0RX   0x00000003
 
#define GPIO_PCTL_PF0_M1PWM4   0x00000005
 
#define GPIO_PCTL_PF0_PHA0   0x00000006
 
#define GPIO_PCTL_PF0_T0CCP0   0x00000007
 
#define GPIO_PCTL_PF0_NMI   0x00000008
 
#define GPIO_PCTL_PF0_C0O   0x00000009
 
#define SSI_CR0_SCR_M   0x0000FF00
 
#define SSI_CR0_SPH   0x00000080
 
#define SSI_CR0_SPO   0x00000040
 
#define SSI_CR0_FRF_M   0x00000030
 
#define SSI_CR0_FRF_MOTO   0x00000000
 
#define SSI_CR0_FRF_TI   0x00000010
 
#define SSI_CR0_FRF_NMW   0x00000020
 
#define SSI_CR0_DSS_M   0x0000000F
 
#define SSI_CR0_DSS_4   0x00000003
 
#define SSI_CR0_DSS_5   0x00000004
 
#define SSI_CR0_DSS_6   0x00000005
 
#define SSI_CR0_DSS_7   0x00000006
 
#define SSI_CR0_DSS_8   0x00000007
 
#define SSI_CR0_DSS_9   0x00000008
 
#define SSI_CR0_DSS_10   0x00000009
 
#define SSI_CR0_DSS_11   0x0000000A
 
#define SSI_CR0_DSS_12   0x0000000B
 
#define SSI_CR0_DSS_13   0x0000000C
 
#define SSI_CR0_DSS_14   0x0000000D
 
#define SSI_CR0_DSS_15   0x0000000E
 
#define SSI_CR0_DSS_16   0x0000000F
 
#define SSI_CR0_SCR_S   8
 
#define SSI_CR1_EOT   0x00000010
 
#define SSI_CR1_MS   0x00000004
 
#define SSI_CR1_SSE   0x00000002
 
#define SSI_CR1_LBM   0x00000001
 
#define SSI_DR_DATA_M   0x0000FFFF
 
#define SSI_DR_DATA_S   0
 
#define SSI_SR_BSY   0x00000010
 
#define SSI_SR_RFF   0x00000008
 
#define SSI_SR_RNE   0x00000004
 
#define SSI_SR_TNF   0x00000002
 
#define SSI_SR_TFE   0x00000001
 
#define SSI_CPSR_CPSDVSR_M   0x000000FF
 
#define SSI_CPSR_CPSDVSR_S   0
 
#define SSI_IM_TXIM   0x00000008
 
#define SSI_IM_RXIM   0x00000004
 
#define SSI_IM_RTIM   0x00000002
 
#define SSI_IM_RORIM   0x00000001
 
#define SSI_RIS_TXRIS   0x00000008
 
#define SSI_RIS_RXRIS   0x00000004
 
#define SSI_RIS_RTRIS   0x00000002
 
#define SSI_RIS_RORRIS   0x00000001
 
#define SSI_MIS_TXMIS   0x00000008
 
#define SSI_MIS_RXMIS   0x00000004
 
#define SSI_MIS_RTMIS   0x00000002
 
#define SSI_MIS_RORMIS   0x00000001
 
#define SSI_ICR_RTIC   0x00000002
 
#define SSI_ICR_RORIC   0x00000001
 
#define SSI_DMACTL_TXDMAE   0x00000002
 
#define SSI_DMACTL_RXDMAE   0x00000001
 
#define SSI_CC_CS_M   0x0000000F
 
#define SSI_CC_CS_SYSPLL   0x00000000
 
#define SSI_CC_CS_PIOSC   0x00000005
 
#define UART_DR_OE   0x00000800
 
#define UART_DR_BE   0x00000400
 
#define UART_DR_PE   0x00000200
 
#define UART_DR_FE   0x00000100
 
#define UART_DR_DATA_M   0x000000FF
 
#define UART_DR_DATA_S   0
 
#define UART_RSR_OE   0x00000008
 
#define UART_RSR_BE   0x00000004
 
#define UART_RSR_PE   0x00000002
 
#define UART_RSR_FE   0x00000001
 
#define UART_ECR_DATA_M   0x000000FF
 
#define UART_ECR_DATA_S   0
 
#define UART_FR_TXFE   0x00000080
 
#define UART_FR_RXFF   0x00000040
 
#define UART_FR_TXFF   0x00000020
 
#define UART_FR_RXFE   0x00000010
 
#define UART_FR_BUSY   0x00000008
 
#define UART_FR_CTS   0x00000001
 
#define UART_ILPR_ILPDVSR_M   0x000000FF
 
#define UART_ILPR_ILPDVSR_S   0
 
#define UART_IBRD_DIVINT_M   0x0000FFFF
 
#define UART_IBRD_DIVINT_S   0
 
#define UART_FBRD_DIVFRAC_M   0x0000003F
 
#define UART_FBRD_DIVFRAC_S   0
 
#define UART_LCRH_SPS   0x00000080
 
#define UART_LCRH_WLEN_M   0x00000060
 
#define UART_LCRH_WLEN_5   0x00000000
 
#define UART_LCRH_WLEN_6   0x00000020
 
#define UART_LCRH_WLEN_7   0x00000040
 
#define UART_LCRH_WLEN_8   0x00000060
 
#define UART_LCRH_FEN   0x00000010
 
#define UART_LCRH_STP2   0x00000008
 
#define UART_LCRH_EPS   0x00000004
 
#define UART_LCRH_PEN   0x00000002
 
#define UART_LCRH_BRK   0x00000001
 
#define UART_CTL_CTSEN   0x00008000
 
#define UART_CTL_RTSEN   0x00004000
 
#define UART_CTL_RTS   0x00000800
 
#define UART_CTL_RXE   0x00000200
 
#define UART_CTL_TXE   0x00000100
 
#define UART_CTL_LBE   0x00000080
 
#define UART_CTL_HSE   0x00000020
 
#define UART_CTL_EOT   0x00000010
 
#define UART_CTL_SMART   0x00000008
 
#define UART_CTL_SIRLP   0x00000004
 
#define UART_CTL_SIREN   0x00000002
 
#define UART_CTL_UARTEN   0x00000001
 
#define UART_IFLS_RX_M   0x00000038
 
#define UART_IFLS_RX1_8   0x00000000
 
#define UART_IFLS_RX2_8   0x00000008
 
#define UART_IFLS_RX4_8   0x00000010
 
#define UART_IFLS_RX6_8   0x00000018
 
#define UART_IFLS_RX7_8   0x00000020
 
#define UART_IFLS_TX_M   0x00000007
 
#define UART_IFLS_TX1_8   0x00000000
 
#define UART_IFLS_TX2_8   0x00000001
 
#define UART_IFLS_TX4_8   0x00000002
 
#define UART_IFLS_TX6_8   0x00000003
 
#define UART_IFLS_TX7_8   0x00000004
 
#define UART_IM_9BITIM   0x00001000
 
#define UART_IM_OEIM   0x00000400
 
#define UART_IM_BEIM   0x00000200
 
#define UART_IM_PEIM   0x00000100
 
#define UART_IM_FEIM   0x00000080
 
#define UART_IM_RTIM   0x00000040
 
#define UART_IM_TXIM   0x00000020
 
#define UART_IM_RXIM   0x00000010
 
#define UART_IM_CTSMIM   0x00000002
 
#define UART_RIS_9BITRIS   0x00001000
 
#define UART_RIS_OERIS   0x00000400
 
#define UART_RIS_BERIS   0x00000200
 
#define UART_RIS_PERIS   0x00000100
 
#define UART_RIS_FERIS   0x00000080
 
#define UART_RIS_RTRIS   0x00000040
 
#define UART_RIS_TXRIS   0x00000020
 
#define UART_RIS_RXRIS   0x00000010
 
#define UART_RIS_CTSRIS   0x00000002
 
#define UART_MIS_9BITMIS   0x00001000
 
#define UART_MIS_OEMIS   0x00000400
 
#define UART_MIS_BEMIS   0x00000200
 
#define UART_MIS_PEMIS   0x00000100
 
#define UART_MIS_FEMIS   0x00000080
 
#define UART_MIS_RTMIS   0x00000040
 
#define UART_MIS_TXMIS   0x00000020
 
#define UART_MIS_RXMIS   0x00000010
 
#define UART_MIS_CTSMIS   0x00000002
 
#define UART_ICR_9BITIC   0x00001000
 
#define UART_ICR_OEIC   0x00000400
 
#define UART_ICR_BEIC   0x00000200
 
#define UART_ICR_PEIC   0x00000100
 
#define UART_ICR_FEIC   0x00000080
 
#define UART_ICR_RTIC   0x00000040
 
#define UART_ICR_TXIC   0x00000020
 
#define UART_ICR_RXIC   0x00000010
 
#define UART_ICR_CTSMIC   0x00000002
 
#define UART_DMACTL_DMAERR   0x00000004
 
#define UART_DMACTL_TXDMAE   0x00000002
 
#define UART_DMACTL_RXDMAE   0x00000001
 
#define UART_9BITADDR_9BITEN   0x00008000
 
#define UART_9BITADDR_ADDR_M   0x000000FF
 
#define UART_9BITADDR_ADDR_S   0
 
#define UART_9BITAMASK_MASK_M   0x000000FF
 
#define UART_9BITAMASK_MASK_S   0
 
#define UART_PP_NB   0x00000002
 
#define UART_PP_SC   0x00000001
 
#define UART_CC_CS_M   0x0000000F
 
#define UART_CC_CS_SYSCLK   0x00000000
 
#define UART_CC_CS_PIOSC   0x00000005
 
#define I2C_MSA_SA_M   0x000000FE
 
#define I2C_MSA_RS   0x00000001
 
#define I2C_MSA_SA_S   1
 
#define I2C_MCS_CLKTO   0x00000080
 
#define I2C_MCS_BUSBSY   0x00000040
 
#define I2C_MCS_IDLE   0x00000020
 
#define I2C_MCS_ARBLST   0x00000010
 
#define I2C_MCS_HS   0x00000010
 
#define I2C_MCS_ACK   0x00000008
 
#define I2C_MCS_DATACK   0x00000008
 
#define I2C_MCS_ADRACK   0x00000004
 
#define I2C_MCS_STOP   0x00000004
 
#define I2C_MCS_ERROR   0x00000002
 
#define I2C_MCS_START   0x00000002
 
#define I2C_MCS_RUN   0x00000001
 
#define I2C_MCS_BUSY   0x00000001
 
#define I2C_MDR_DATA_M   0x000000FF
 
#define I2C_MDR_DATA_S   0
 
#define I2C_MTPR_HS   0x00000080
 
#define I2C_MTPR_TPR_M   0x0000007F
 
#define I2C_MTPR_TPR_S   0
 
#define I2C_MIMR_CLKIM   0x00000002
 
#define I2C_MIMR_IM   0x00000001
 
#define I2C_MRIS_CLKRIS   0x00000002
 
#define I2C_MRIS_RIS   0x00000001
 
#define I2C_MMIS_CLKMIS   0x00000002
 
#define I2C_MMIS_MIS   0x00000001
 
#define I2C_MICR_CLKIC   0x00000002
 
#define I2C_MICR_IC   0x00000001
 
#define I2C_MCR_GFE   0x00000040
 
#define I2C_MCR_SFE   0x00000020
 
#define I2C_MCR_MFE   0x00000010
 
#define I2C_MCR_LPBK   0x00000001
 
#define I2C_MCLKOCNT_CNTL_M   0x000000FF
 
#define I2C_MCLKOCNT_CNTL_S   0
 
#define I2C_MBMON_SDA   0x00000002
 
#define I2C_MBMON_SCL   0x00000001
 
#define I2C_MCR2_GFPW_M   0x00000070
 
#define I2C_MCR2_GFPW_BYPASS   0x00000000
 
#define I2C_MCR2_GFPW_1   0x00000010
 
#define I2C_MCR2_GFPW_2   0x00000020
 
#define I2C_MCR2_GFPW_3   0x00000030
 
#define I2C_MCR2_GFPW_4   0x00000040
 
#define I2C_MCR2_GFPW_8   0x00000050
 
#define I2C_MCR2_GFPW_16   0x00000060
 
#define I2C_MCR2_GFPW_31   0x00000070
 
#define I2C_SOAR_OAR_M   0x0000007F
 
#define I2C_SOAR_OAR_S   0
 
#define I2C_SCSR_OAR2SEL   0x00000008
 
#define I2C_SCSR_FBR   0x00000004
 
#define I2C_SCSR_TREQ   0x00000002
 
#define I2C_SCSR_DA   0x00000001
 
#define I2C_SCSR_RREQ   0x00000001
 
#define I2C_SDR_DATA_M   0x000000FF
 
#define I2C_SDR_DATA_S   0
 
#define I2C_SIMR_STOPIM   0x00000004
 
#define I2C_SIMR_STARTIM   0x00000002
 
#define I2C_SIMR_DATAIM   0x00000001
 
#define I2C_SRIS_STOPRIS   0x00000004
 
#define I2C_SRIS_STARTRIS   0x00000002
 
#define I2C_SRIS_DATARIS   0x00000001
 
#define I2C_SMIS_STOPMIS   0x00000004
 
#define I2C_SMIS_STARTMIS   0x00000002
 
#define I2C_SMIS_DATAMIS   0x00000001
 
#define I2C_SICR_STOPIC   0x00000004
 
#define I2C_SICR_STARTIC   0x00000002
 
#define I2C_SICR_DATAIC   0x00000001
 
#define I2C_SOAR2_OAR2EN   0x00000080
 
#define I2C_SOAR2_OAR2_M   0x0000007F
 
#define I2C_SOAR2_OAR2_S   0
 
#define I2C_SACKCTL_ACKOVAL   0x00000002
 
#define I2C_SACKCTL_ACKOEN   0x00000001
 
#define I2C_PP_HS   0x00000001
 
#define I2C_PC_HS   0x00000001
 
#define PWM_CTL_GLOBALSYNC3   0x00000008
 
#define PWM_CTL_GLOBALSYNC2   0x00000004
 
#define PWM_CTL_GLOBALSYNC1   0x00000002
 
#define PWM_CTL_GLOBALSYNC0   0x00000001
 
#define PWM_SYNC_SYNC3   0x00000008
 
#define PWM_SYNC_SYNC2   0x00000004
 
#define PWM_SYNC_SYNC1   0x00000002
 
#define PWM_SYNC_SYNC0   0x00000001
 
#define PWM_ENABLE_PWM7EN   0x00000080
 
#define PWM_ENABLE_PWM6EN   0x00000040
 
#define PWM_ENABLE_PWM5EN   0x00000020
 
#define PWM_ENABLE_PWM4EN   0x00000010
 
#define PWM_ENABLE_PWM3EN   0x00000008
 
#define PWM_ENABLE_PWM2EN   0x00000004
 
#define PWM_ENABLE_PWM1EN   0x00000002
 
#define PWM_ENABLE_PWM0EN   0x00000001
 
#define PWM_INVERT_PWM7INV   0x00000080
 
#define PWM_INVERT_PWM6INV   0x00000040
 
#define PWM_INVERT_PWM5INV   0x00000020
 
#define PWM_INVERT_PWM4INV   0x00000010
 
#define PWM_INVERT_PWM3INV   0x00000008
 
#define PWM_INVERT_PWM2INV   0x00000004
 
#define PWM_INVERT_PWM1INV   0x00000002
 
#define PWM_INVERT_PWM0INV   0x00000001
 
#define PWM_FAULT_FAULT7   0x00000080
 
#define PWM_FAULT_FAULT6   0x00000040
 
#define PWM_FAULT_FAULT5   0x00000020
 
#define PWM_FAULT_FAULT4   0x00000010
 
#define PWM_FAULT_FAULT3   0x00000008
 
#define PWM_FAULT_FAULT2   0x00000004
 
#define PWM_FAULT_FAULT1   0x00000002
 
#define PWM_FAULT_FAULT0   0x00000001
 
#define PWM_INTEN_INTFAULT1   0x00020000
 
#define PWM_INTEN_INTFAULT0   0x00010000
 
#define PWM_INTEN_INTPWM3   0x00000008
 
#define PWM_INTEN_INTPWM2   0x00000004
 
#define PWM_INTEN_INTPWM1   0x00000002
 
#define PWM_INTEN_INTPWM0   0x00000001
 
#define PWM_RIS_INTFAULT1   0x00020000
 
#define PWM_RIS_INTFAULT0   0x00010000
 
#define PWM_RIS_INTPWM3   0x00000008
 
#define PWM_RIS_INTPWM2   0x00000004
 
#define PWM_RIS_INTPWM1   0x00000002
 
#define PWM_RIS_INTPWM0   0x00000001
 
#define PWM_ISC_INTFAULT1   0x00020000
 
#define PWM_ISC_INTFAULT0   0x00010000
 
#define PWM_ISC_INTPWM3   0x00000008
 
#define PWM_ISC_INTPWM2   0x00000004
 
#define PWM_ISC_INTPWM1   0x00000002
 
#define PWM_ISC_INTPWM0   0x00000001
 
#define PWM_STATUS_FAULT1   0x00000002
 
#define PWM_STATUS_FAULT0   0x00000001
 
#define PWM_FAULTVAL_PWM7   0x00000080
 
#define PWM_FAULTVAL_PWM6   0x00000040
 
#define PWM_FAULTVAL_PWM5   0x00000020
 
#define PWM_FAULTVAL_PWM4   0x00000010
 
#define PWM_FAULTVAL_PWM3   0x00000008
 
#define PWM_FAULTVAL_PWM2   0x00000004
 
#define PWM_FAULTVAL_PWM1   0x00000002
 
#define PWM_FAULTVAL_PWM0   0x00000001
 
#define PWM_ENUPD_ENUPD7_M   0x0000C000
 
#define PWM_ENUPD_ENUPD7_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD7_LSYNC   0x00008000
 
#define PWM_ENUPD_ENUPD7_GSYNC   0x0000C000
 
#define PWM_ENUPD_ENUPD6_M   0x00003000
 
#define PWM_ENUPD_ENUPD6_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD6_LSYNC   0x00002000
 
#define PWM_ENUPD_ENUPD6_GSYNC   0x00003000
 
#define PWM_ENUPD_ENUPD5_M   0x00000C00
 
#define PWM_ENUPD_ENUPD5_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD5_LSYNC   0x00000800
 
#define PWM_ENUPD_ENUPD5_GSYNC   0x00000C00
 
#define PWM_ENUPD_ENUPD4_M   0x00000300
 
#define PWM_ENUPD_ENUPD4_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD4_LSYNC   0x00000200
 
#define PWM_ENUPD_ENUPD4_GSYNC   0x00000300
 
#define PWM_ENUPD_ENUPD3_M   0x000000C0
 
#define PWM_ENUPD_ENUPD3_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD3_LSYNC   0x00000080
 
#define PWM_ENUPD_ENUPD3_GSYNC   0x000000C0
 
#define PWM_ENUPD_ENUPD2_M   0x00000030
 
#define PWM_ENUPD_ENUPD2_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD2_LSYNC   0x00000020
 
#define PWM_ENUPD_ENUPD2_GSYNC   0x00000030
 
#define PWM_ENUPD_ENUPD1_M   0x0000000C
 
#define PWM_ENUPD_ENUPD1_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD1_LSYNC   0x00000008
 
#define PWM_ENUPD_ENUPD1_GSYNC   0x0000000C
 
#define PWM_ENUPD_ENUPD0_M   0x00000003
 
#define PWM_ENUPD_ENUPD0_IMM   0x00000000
 
#define PWM_ENUPD_ENUPD0_LSYNC   0x00000002
 
#define PWM_ENUPD_ENUPD0_GSYNC   0x00000003
 
#define PWM_0_CTL_LATCH   0x00040000
 
#define PWM_0_CTL_MINFLTPER   0x00020000
 
#define PWM_0_CTL_FLTSRC   0x00010000
 
#define PWM_0_CTL_DBFALLUPD_M   0x0000C000
 
#define PWM_0_CTL_DBFALLUPD_I   0x00000000
 
#define PWM_0_CTL_DBFALLUPD_LS   0x00008000
 
#define PWM_0_CTL_DBFALLUPD_GS   0x0000C000
 
#define PWM_0_CTL_DBRISEUPD_M   0x00003000
 
#define PWM_0_CTL_DBRISEUPD_I   0x00000000
 
#define PWM_0_CTL_DBRISEUPD_LS   0x00002000
 
#define PWM_0_CTL_DBRISEUPD_GS   0x00003000
 
#define PWM_0_CTL_DBCTLUPD_M   0x00000C00
 
#define PWM_0_CTL_DBCTLUPD_I   0x00000000
 
#define PWM_0_CTL_DBCTLUPD_LS   0x00000800
 
#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00
 
#define PWM_0_CTL_GENBUPD_M   0x00000300
 
#define PWM_0_CTL_GENBUPD_I   0x00000000
 
#define PWM_0_CTL_GENBUPD_LS   0x00000200
 
#define PWM_0_CTL_GENBUPD_GS   0x00000300
 
#define PWM_0_CTL_GENAUPD_M   0x000000C0
 
#define PWM_0_CTL_GENAUPD_I   0x00000000
 
#define PWM_0_CTL_GENAUPD_LS   0x00000080
 
#define PWM_0_CTL_GENAUPD_GS   0x000000C0
 
#define PWM_0_CTL_CMPBUPD   0x00000020
 
#define PWM_0_CTL_CMPAUPD   0x00000010
 
#define PWM_0_CTL_LOADUPD   0x00000008
 
#define PWM_0_CTL_DEBUG   0x00000004
 
#define PWM_0_CTL_MODE   0x00000002
 
#define PWM_0_CTL_ENABLE   0x00000001
 
#define PWM_0_INTEN_TRCMPBD   0x00002000
 
#define PWM_0_INTEN_TRCMPBU   0x00001000
 
#define PWM_0_INTEN_TRCMPAD   0x00000800
 
#define PWM_0_INTEN_TRCMPAU   0x00000400
 
#define PWM_0_INTEN_TRCNTLOAD   0x00000200
 
#define PWM_0_INTEN_TRCNTZERO   0x00000100
 
#define PWM_0_INTEN_INTCMPBD   0x00000020
 
#define PWM_0_INTEN_INTCMPBU   0x00000010
 
#define PWM_0_INTEN_INTCMPAD   0x00000008
 
#define PWM_0_INTEN_INTCMPAU   0x00000004
 
#define PWM_0_INTEN_INTCNTLOAD   0x00000002
 
#define PWM_0_INTEN_INTCNTZERO   0x00000001
 
#define PWM_0_RIS_INTCMPBD   0x00000020
 
#define PWM_0_RIS_INTCMPBU   0x00000010
 
#define PWM_0_RIS_INTCMPAD   0x00000008
 
#define PWM_0_RIS_INTCMPAU   0x00000004
 
#define PWM_0_RIS_INTCNTLOAD   0x00000002
 
#define PWM_0_RIS_INTCNTZERO   0x00000001
 
#define PWM_0_ISC_INTCMPBD   0x00000020
 
#define PWM_0_ISC_INTCMPBU   0x00000010
 
#define PWM_0_ISC_INTCMPAD   0x00000008
 
#define PWM_0_ISC_INTCMPAU   0x00000004
 
#define PWM_0_ISC_INTCNTLOAD   0x00000002
 
#define PWM_0_ISC_INTCNTZERO   0x00000001
 
#define PWM_0_LOAD_M   0x0000FFFF
 
#define PWM_0_LOAD_S   0
 
#define PWM_0_COUNT_M   0x0000FFFF
 
#define PWM_0_COUNT_S   0
 
#define PWM_0_CMPA_M   0x0000FFFF
 
#define PWM_0_CMPA_S   0
 
#define PWM_0_CMPB_M   0x0000FFFF
 
#define PWM_0_CMPB_S   0
 
#define PWM_0_GENA_ACTCMPBD_M   0x00000C00
 
#define PWM_0_GENA_ACTCMPBD_NONE    0x00000000
 
#define PWM_0_GENA_ACTCMPBD_INV   0x00000400
 
#define PWM_0_GENA_ACTCMPBD_ZERO    0x00000800
 
#define PWM_0_GENA_ACTCMPBD_ONE   0x00000C00
 
#define PWM_0_GENA_ACTCMPBU_M   0x00000300
 
#define PWM_0_GENA_ACTCMPBU_NONE    0x00000000
 
#define PWM_0_GENA_ACTCMPBU_INV   0x00000100
 
#define PWM_0_GENA_ACTCMPBU_ZERO    0x00000200
 
#define PWM_0_GENA_ACTCMPBU_ONE   0x00000300
 
#define PWM_0_GENA_ACTCMPAD_M   0x000000C0
 
#define PWM_0_GENA_ACTCMPAD_NONE    0x00000000
 
#define PWM_0_GENA_ACTCMPAD_INV   0x00000040
 
#define PWM_0_GENA_ACTCMPAD_ZERO    0x00000080
 
#define PWM_0_GENA_ACTCMPAD_ONE   0x000000C0
 
#define PWM_0_GENA_ACTCMPAU_M   0x00000030
 
#define PWM_0_GENA_ACTCMPAU_NONE    0x00000000
 
#define PWM_0_GENA_ACTCMPAU_INV   0x00000010
 
#define PWM_0_GENA_ACTCMPAU_ZERO    0x00000020
 
#define PWM_0_GENA_ACTCMPAU_ONE   0x00000030
 
#define PWM_0_GENA_ACTLOAD_M   0x0000000C
 
#define PWM_0_GENA_ACTLOAD_NONE   0x00000000
 
#define PWM_0_GENA_ACTLOAD_INV   0x00000004
 
#define PWM_0_GENA_ACTLOAD_ZERO   0x00000008
 
#define PWM_0_GENA_ACTLOAD_ONE   0x0000000C
 
#define PWM_0_GENA_ACTZERO_M   0x00000003
 
#define PWM_0_GENA_ACTZERO_NONE   0x00000000
 
#define PWM_0_GENA_ACTZERO_INV   0x00000001
 
#define PWM_0_GENA_ACTZERO_ZERO   0x00000002
 
#define PWM_0_GENA_ACTZERO_ONE   0x00000003
 
#define PWM_0_GENB_ACTCMPBD_M   0x00000C00
 
#define PWM_0_GENB_ACTCMPBD_NONE    0x00000000
 
#define PWM_0_GENB_ACTCMPBD_INV   0x00000400
 
#define PWM_0_GENB_ACTCMPBD_ZERO    0x00000800
 
#define PWM_0_GENB_ACTCMPBD_ONE   0x00000C00
 
#define PWM_0_GENB_ACTCMPBU_M   0x00000300
 
#define PWM_0_GENB_ACTCMPBU_NONE    0x00000000
 
#define PWM_0_GENB_ACTCMPBU_INV   0x00000100
 
#define PWM_0_GENB_ACTCMPBU_ZERO    0x00000200
 
#define PWM_0_GENB_ACTCMPBU_ONE   0x00000300
 
#define PWM_0_GENB_ACTCMPAD_M   0x000000C0
 
#define PWM_0_GENB_ACTCMPAD_NONE    0x00000000
 
#define PWM_0_GENB_ACTCMPAD_INV   0x00000040
 
#define PWM_0_GENB_ACTCMPAD_ZERO    0x00000080
 
#define PWM_0_GENB_ACTCMPAD_ONE   0x000000C0
 
#define PWM_0_GENB_ACTCMPAU_M   0x00000030
 
#define PWM_0_GENB_ACTCMPAU_NONE    0x00000000
 
#define PWM_0_GENB_ACTCMPAU_INV   0x00000010
 
#define PWM_0_GENB_ACTCMPAU_ZERO    0x00000020
 
#define PWM_0_GENB_ACTCMPAU_ONE   0x00000030
 
#define PWM_0_GENB_ACTLOAD_M   0x0000000C
 
#define PWM_0_GENB_ACTLOAD_NONE   0x00000000
 
#define PWM_0_GENB_ACTLOAD_INV   0x00000004
 
#define PWM_0_GENB_ACTLOAD_ZERO   0x00000008
 
#define PWM_0_GENB_ACTLOAD_ONE   0x0000000C
 
#define PWM_0_GENB_ACTZERO_M   0x00000003
 
#define PWM_0_GENB_ACTZERO_NONE   0x00000000
 
#define PWM_0_GENB_ACTZERO_INV   0x00000001
 
#define PWM_0_GENB_ACTZERO_ZERO   0x00000002
 
#define PWM_0_GENB_ACTZERO_ONE   0x00000003
 
#define PWM_0_DBCTL_ENABLE   0x00000001
 
#define PWM_0_DBRISE_DELAY_M   0x00000FFF
 
#define PWM_0_DBRISE_DELAY_S   0
 
#define PWM_0_DBFALL_DELAY_M   0x00000FFF
 
#define PWM_0_DBFALL_DELAY_S   0
 
#define PWM_0_FLTSRC0_FAULT1   0x00000002
 
#define PWM_0_FLTSRC0_FAULT0   0x00000001
 
#define PWM_0_FLTSRC1_DCMP7   0x00000080
 
#define PWM_0_FLTSRC1_DCMP6   0x00000040
 
#define PWM_0_FLTSRC1_DCMP5   0x00000020
 
#define PWM_0_FLTSRC1_DCMP4   0x00000010
 
#define PWM_0_FLTSRC1_DCMP3   0x00000008
 
#define PWM_0_FLTSRC1_DCMP2   0x00000004
 
#define PWM_0_FLTSRC1_DCMP1   0x00000002
 
#define PWM_0_FLTSRC1_DCMP0   0x00000001
 
#define PWM_0_MINFLTPER_M   0x0000FFFF
 
#define PWM_0_MINFLTPER_S   0
 
#define PWM_1_CTL_LATCH   0x00040000
 
#define PWM_1_CTL_MINFLTPER   0x00020000
 
#define PWM_1_CTL_FLTSRC   0x00010000
 
#define PWM_1_CTL_DBFALLUPD_M   0x0000C000
 
#define PWM_1_CTL_DBFALLUPD_I   0x00000000
 
#define PWM_1_CTL_DBFALLUPD_LS   0x00008000
 
#define PWM_1_CTL_DBFALLUPD_GS   0x0000C000
 
#define PWM_1_CTL_DBRISEUPD_M   0x00003000
 
#define PWM_1_CTL_DBRISEUPD_I   0x00000000
 
#define PWM_1_CTL_DBRISEUPD_LS   0x00002000
 
#define PWM_1_CTL_DBRISEUPD_GS   0x00003000
 
#define PWM_1_CTL_DBCTLUPD_M   0x00000C00
 
#define PWM_1_CTL_DBCTLUPD_I   0x00000000
 
#define PWM_1_CTL_DBCTLUPD_LS   0x00000800
 
#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00
 
#define PWM_1_CTL_GENBUPD_M   0x00000300
 
#define PWM_1_CTL_GENBUPD_I   0x00000000
 
#define PWM_1_CTL_GENBUPD_LS   0x00000200
 
#define PWM_1_CTL_GENBUPD_GS   0x00000300
 
#define PWM_1_CTL_GENAUPD_M   0x000000C0
 
#define PWM_1_CTL_GENAUPD_I   0x00000000
 
#define PWM_1_CTL_GENAUPD_LS   0x00000080
 
#define PWM_1_CTL_GENAUPD_GS   0x000000C0
 
#define PWM_1_CTL_CMPBUPD   0x00000020
 
#define PWM_1_CTL_CMPAUPD   0x00000010
 
#define PWM_1_CTL_LOADUPD   0x00000008
 
#define PWM_1_CTL_DEBUG   0x00000004
 
#define PWM_1_CTL_MODE   0x00000002
 
#define PWM_1_CTL_ENABLE   0x00000001
 
#define PWM_1_INTEN_TRCMPBD   0x00002000
 
#define PWM_1_INTEN_TRCMPBU   0x00001000
 
#define PWM_1_INTEN_TRCMPAD   0x00000800
 
#define PWM_1_INTEN_TRCMPAU   0x00000400
 
#define PWM_1_INTEN_TRCNTLOAD   0x00000200
 
#define PWM_1_INTEN_TRCNTZERO   0x00000100
 
#define PWM_1_INTEN_INTCMPBD   0x00000020
 
#define PWM_1_INTEN_INTCMPBU   0x00000010
 
#define PWM_1_INTEN_INTCMPAD   0x00000008
 
#define PWM_1_INTEN_INTCMPAU   0x00000004
 
#define PWM_1_INTEN_INTCNTLOAD   0x00000002
 
#define PWM_1_INTEN_INTCNTZERO   0x00000001
 
#define PWM_1_RIS_INTCMPBD   0x00000020
 
#define PWM_1_RIS_INTCMPBU   0x00000010
 
#define PWM_1_RIS_INTCMPAD   0x00000008
 
#define PWM_1_RIS_INTCMPAU   0x00000004
 
#define PWM_1_RIS_INTCNTLOAD   0x00000002
 
#define PWM_1_RIS_INTCNTZERO   0x00000001
 
#define PWM_1_ISC_INTCMPBD   0x00000020
 
#define PWM_1_ISC_INTCMPBU   0x00000010
 
#define PWM_1_ISC_INTCMPAD   0x00000008
 
#define PWM_1_ISC_INTCMPAU   0x00000004
 
#define PWM_1_ISC_INTCNTLOAD   0x00000002
 
#define PWM_1_ISC_INTCNTZERO   0x00000001
 
#define PWM_1_LOAD_LOAD_M   0x0000FFFF
 
#define PWM_1_LOAD_LOAD_S   0
 
#define PWM_1_COUNT_COUNT_M   0x0000FFFF
 
#define PWM_1_COUNT_COUNT_S   0
 
#define PWM_1_CMPA_COMPA_M   0x0000FFFF
 
#define PWM_1_CMPA_COMPA_S   0
 
#define PWM_1_CMPB_COMPB_M   0x0000FFFF
 
#define PWM_1_CMPB_COMPB_S   0
 
#define PWM_1_GENA_ACTCMPBD_M   0x00000C00
 
#define PWM_1_GENA_ACTCMPBD_NONE    0x00000000
 
#define PWM_1_GENA_ACTCMPBD_INV   0x00000400
 
#define PWM_1_GENA_ACTCMPBD_ZERO    0x00000800
 
#define PWM_1_GENA_ACTCMPBD_ONE   0x00000C00
 
#define PWM_1_GENA_ACTCMPBU_M   0x00000300
 
#define PWM_1_GENA_ACTCMPBU_NONE    0x00000000
 
#define PWM_1_GENA_ACTCMPBU_INV   0x00000100
 
#define PWM_1_GENA_ACTCMPBU_ZERO    0x00000200
 
#define PWM_1_GENA_ACTCMPBU_ONE   0x00000300
 
#define PWM_1_GENA_ACTCMPAD_M   0x000000C0
 
#define PWM_1_GENA_ACTCMPAD_NONE    0x00000000
 
#define PWM_1_GENA_ACTCMPAD_INV   0x00000040
 
#define PWM_1_GENA_ACTCMPAD_ZERO    0x00000080
 
#define PWM_1_GENA_ACTCMPAD_ONE   0x000000C0
 
#define PWM_1_GENA_ACTCMPAU_M   0x00000030
 
#define PWM_1_GENA_ACTCMPAU_NONE    0x00000000
 
#define PWM_1_GENA_ACTCMPAU_INV   0x00000010
 
#define PWM_1_GENA_ACTCMPAU_ZERO    0x00000020
 
#define PWM_1_GENA_ACTCMPAU_ONE   0x00000030
 
#define PWM_1_GENA_ACTLOAD_M   0x0000000C
 
#define PWM_1_GENA_ACTLOAD_NONE   0x00000000
 
#define PWM_1_GENA_ACTLOAD_INV   0x00000004
 
#define PWM_1_GENA_ACTLOAD_ZERO   0x00000008
 
#define PWM_1_GENA_ACTLOAD_ONE   0x0000000C
 
#define PWM_1_GENA_ACTZERO_M   0x00000003
 
#define PWM_1_GENA_ACTZERO_NONE   0x00000000
 
#define PWM_1_GENA_ACTZERO_INV   0x00000001
 
#define PWM_1_GENA_ACTZERO_ZERO   0x00000002
 
#define PWM_1_GENA_ACTZERO_ONE   0x00000003
 
#define PWM_1_GENB_ACTCMPBD_M   0x00000C00
 
#define PWM_1_GENB_ACTCMPBD_NONE    0x00000000
 
#define PWM_1_GENB_ACTCMPBD_INV   0x00000400
 
#define PWM_1_GENB_ACTCMPBD_ZERO    0x00000800
 
#define PWM_1_GENB_ACTCMPBD_ONE   0x00000C00
 
#define PWM_1_GENB_ACTCMPBU_M   0x00000300
 
#define PWM_1_GENB_ACTCMPBU_NONE    0x00000000
 
#define PWM_1_GENB_ACTCMPBU_INV   0x00000100
 
#define PWM_1_GENB_ACTCMPBU_ZERO    0x00000200
 
#define PWM_1_GENB_ACTCMPBU_ONE   0x00000300
 
#define PWM_1_GENB_ACTCMPAD_M   0x000000C0
 
#define PWM_1_GENB_ACTCMPAD_NONE    0x00000000
 
#define PWM_1_GENB_ACTCMPAD_INV   0x00000040
 
#define PWM_1_GENB_ACTCMPAD_ZERO    0x00000080
 
#define PWM_1_GENB_ACTCMPAD_ONE   0x000000C0
 
#define PWM_1_GENB_ACTCMPAU_M   0x00000030
 
#define PWM_1_GENB_ACTCMPAU_NONE    0x00000000
 
#define PWM_1_GENB_ACTCMPAU_INV   0x00000010
 
#define PWM_1_GENB_ACTCMPAU_ZERO    0x00000020
 
#define PWM_1_GENB_ACTCMPAU_ONE   0x00000030
 
#define PWM_1_GENB_ACTLOAD_M   0x0000000C
 
#define PWM_1_GENB_ACTLOAD_NONE   0x00000000
 
#define PWM_1_GENB_ACTLOAD_INV   0x00000004
 
#define PWM_1_GENB_ACTLOAD_ZERO   0x00000008
 
#define PWM_1_GENB_ACTLOAD_ONE   0x0000000C
 
#define PWM_1_GENB_ACTZERO_M   0x00000003
 
#define PWM_1_GENB_ACTZERO_NONE   0x00000000
 
#define PWM_1_GENB_ACTZERO_INV   0x00000001
 
#define PWM_1_GENB_ACTZERO_ZERO   0x00000002
 
#define PWM_1_GENB_ACTZERO_ONE   0x00000003
 
#define PWM_1_DBCTL_ENABLE   0x00000001
 
#define PWM_1_DBRISE_RISEDELAY_M    0x00000FFF
 
#define PWM_1_DBRISE_RISEDELAY_S    0
 
#define PWM_1_DBFALL_FALLDELAY_M    0x00000FFF
 
#define PWM_1_DBFALL_FALLDELAY_S    0
 
#define PWM_1_FLTSRC0_FAULT1   0x00000002
 
#define PWM_1_FLTSRC0_FAULT0   0x00000001
 
#define PWM_1_FLTSRC1_DCMP7   0x00000080
 
#define PWM_1_FLTSRC1_DCMP6   0x00000040
 
#define PWM_1_FLTSRC1_DCMP5   0x00000020
 
#define PWM_1_FLTSRC1_DCMP4   0x00000010
 
#define PWM_1_FLTSRC1_DCMP3   0x00000008
 
#define PWM_1_FLTSRC1_DCMP2   0x00000004
 
#define PWM_1_FLTSRC1_DCMP1   0x00000002
 
#define PWM_1_FLTSRC1_DCMP0   0x00000001
 
#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF
 
#define PWM_1_MINFLTPER_MFP_S   0
 
#define PWM_2_CTL_LATCH   0x00040000
 
#define PWM_2_CTL_MINFLTPER   0x00020000
 
#define PWM_2_CTL_FLTSRC   0x00010000
 
#define PWM_2_CTL_DBFALLUPD_M   0x0000C000
 
#define PWM_2_CTL_DBFALLUPD_I   0x00000000
 
#define PWM_2_CTL_DBFALLUPD_LS   0x00008000
 
#define PWM_2_CTL_DBFALLUPD_GS   0x0000C000
 
#define PWM_2_CTL_DBRISEUPD_M   0x00003000
 
#define PWM_2_CTL_DBRISEUPD_I   0x00000000
 
#define PWM_2_CTL_DBRISEUPD_LS   0x00002000
 
#define PWM_2_CTL_DBRISEUPD_GS   0x00003000
 
#define PWM_2_CTL_DBCTLUPD_M   0x00000C00
 
#define PWM_2_CTL_DBCTLUPD_I   0x00000000
 
#define PWM_2_CTL_DBCTLUPD_LS   0x00000800
 
#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00
 
#define PWM_2_CTL_GENBUPD_M   0x00000300
 
#define PWM_2_CTL_GENBUPD_I   0x00000000
 
#define PWM_2_CTL_GENBUPD_LS   0x00000200
 
#define PWM_2_CTL_GENBUPD_GS   0x00000300
 
#define PWM_2_CTL_GENAUPD_M   0x000000C0
 
#define PWM_2_CTL_GENAUPD_I   0x00000000
 
#define PWM_2_CTL_GENAUPD_LS   0x00000080
 
#define PWM_2_CTL_GENAUPD_GS   0x000000C0
 
#define PWM_2_CTL_CMPBUPD   0x00000020
 
#define PWM_2_CTL_CMPAUPD   0x00000010
 
#define PWM_2_CTL_LOADUPD   0x00000008
 
#define PWM_2_CTL_DEBUG   0x00000004
 
#define PWM_2_CTL_MODE   0x00000002
 
#define PWM_2_CTL_ENABLE   0x00000001
 
#define PWM_2_INTEN_TRCMPBD   0x00002000
 
#define PWM_2_INTEN_TRCMPBU   0x00001000
 
#define PWM_2_INTEN_TRCMPAD   0x00000800
 
#define PWM_2_INTEN_TRCMPAU   0x00000400
 
#define PWM_2_INTEN_TRCNTLOAD   0x00000200
 
#define PWM_2_INTEN_TRCNTZERO   0x00000100
 
#define PWM_2_INTEN_INTCMPBD   0x00000020
 
#define PWM_2_INTEN_INTCMPBU   0x00000010
 
#define PWM_2_INTEN_INTCMPAD   0x00000008
 
#define PWM_2_INTEN_INTCMPAU   0x00000004
 
#define PWM_2_INTEN_INTCNTLOAD   0x00000002
 
#define PWM_2_INTEN_INTCNTZERO   0x00000001
 
#define PWM_2_RIS_INTCMPBD   0x00000020
 
#define PWM_2_RIS_INTCMPBU   0x00000010
 
#define PWM_2_RIS_INTCMPAD   0x00000008
 
#define PWM_2_RIS_INTCMPAU   0x00000004
 
#define PWM_2_RIS_INTCNTLOAD   0x00000002
 
#define PWM_2_RIS_INTCNTZERO   0x00000001
 
#define PWM_2_ISC_INTCMPBD   0x00000020
 
#define PWM_2_ISC_INTCMPBU   0x00000010
 
#define PWM_2_ISC_INTCMPAD   0x00000008
 
#define PWM_2_ISC_INTCMPAU   0x00000004
 
#define PWM_2_ISC_INTCNTLOAD   0x00000002
 
#define PWM_2_ISC_INTCNTZERO   0x00000001
 
#define PWM_2_LOAD_LOAD_M   0x0000FFFF
 
#define PWM_2_LOAD_LOAD_S   0
 
#define PWM_2_COUNT_COUNT_M   0x0000FFFF
 
#define PWM_2_COUNT_COUNT_S   0
 
#define PWM_2_CMPA_COMPA_M   0x0000FFFF
 
#define PWM_2_CMPA_COMPA_S   0
 
#define PWM_2_CMPB_COMPB_M   0x0000FFFF
 
#define PWM_2_CMPB_COMPB_S   0
 
#define PWM_2_GENA_ACTCMPBD_M   0x00000C00
 
#define PWM_2_GENA_ACTCMPBD_NONE    0x00000000
 
#define PWM_2_GENA_ACTCMPBD_INV   0x00000400
 
#define PWM_2_GENA_ACTCMPBD_ZERO    0x00000800
 
#define PWM_2_GENA_ACTCMPBD_ONE   0x00000C00
 
#define PWM_2_GENA_ACTCMPBU_M   0x00000300
 
#define PWM_2_GENA_ACTCMPBU_NONE    0x00000000
 
#define PWM_2_GENA_ACTCMPBU_INV   0x00000100
 
#define PWM_2_GENA_ACTCMPBU_ZERO    0x00000200
 
#define PWM_2_GENA_ACTCMPBU_ONE   0x00000300
 
#define PWM_2_GENA_ACTCMPAD_M   0x000000C0
 
#define PWM_2_GENA_ACTCMPAD_NONE    0x00000000
 
#define PWM_2_GENA_ACTCMPAD_INV   0x00000040
 
#define PWM_2_GENA_ACTCMPAD_ZERO    0x00000080
 
#define PWM_2_GENA_ACTCMPAD_ONE   0x000000C0
 
#define PWM_2_GENA_ACTCMPAU_M   0x00000030
 
#define PWM_2_GENA_ACTCMPAU_NONE    0x00000000
 
#define PWM_2_GENA_ACTCMPAU_INV   0x00000010
 
#define PWM_2_GENA_ACTCMPAU_ZERO    0x00000020
 
#define PWM_2_GENA_ACTCMPAU_ONE   0x00000030
 
#define PWM_2_GENA_ACTLOAD_M   0x0000000C
 
#define PWM_2_GENA_ACTLOAD_NONE   0x00000000
 
#define PWM_2_GENA_ACTLOAD_INV   0x00000004
 
#define PWM_2_GENA_ACTLOAD_ZERO   0x00000008
 
#define PWM_2_GENA_ACTLOAD_ONE   0x0000000C
 
#define PWM_2_GENA_ACTZERO_M   0x00000003
 
#define PWM_2_GENA_ACTZERO_NONE   0x00000000
 
#define PWM_2_GENA_ACTZERO_INV   0x00000001
 
#define PWM_2_GENA_ACTZERO_ZERO   0x00000002
 
#define PWM_2_GENA_ACTZERO_ONE   0x00000003
 
#define PWM_2_GENB_ACTCMPBD_M   0x00000C00
 
#define PWM_2_GENB_ACTCMPBD_NONE    0x00000000
 
#define PWM_2_GENB_ACTCMPBD_INV   0x00000400
 
#define PWM_2_GENB_ACTCMPBD_ZERO    0x00000800
 
#define PWM_2_GENB_ACTCMPBD_ONE   0x00000C00
 
#define PWM_2_GENB_ACTCMPBU_M   0x00000300
 
#define PWM_2_GENB_ACTCMPBU_NONE    0x00000000
 
#define PWM_2_GENB_ACTCMPBU_INV   0x00000100
 
#define PWM_2_GENB_ACTCMPBU_ZERO    0x00000200
 
#define PWM_2_GENB_ACTCMPBU_ONE   0x00000300
 
#define PWM_2_GENB_ACTCMPAD_M   0x000000C0
 
#define PWM_2_GENB_ACTCMPAD_NONE    0x00000000
 
#define PWM_2_GENB_ACTCMPAD_INV   0x00000040
 
#define PWM_2_GENB_ACTCMPAD_ZERO    0x00000080
 
#define PWM_2_GENB_ACTCMPAD_ONE   0x000000C0
 
#define PWM_2_GENB_ACTCMPAU_M   0x00000030
 
#define PWM_2_GENB_ACTCMPAU_NONE    0x00000000
 
#define PWM_2_GENB_ACTCMPAU_INV   0x00000010
 
#define PWM_2_GENB_ACTCMPAU_ZERO    0x00000020
 
#define PWM_2_GENB_ACTCMPAU_ONE   0x00000030
 
#define PWM_2_GENB_ACTLOAD_M   0x0000000C
 
#define PWM_2_GENB_ACTLOAD_NONE   0x00000000
 
#define PWM_2_GENB_ACTLOAD_INV   0x00000004
 
#define PWM_2_GENB_ACTLOAD_ZERO   0x00000008
 
#define PWM_2_GENB_ACTLOAD_ONE   0x0000000C
 
#define PWM_2_GENB_ACTZERO_M   0x00000003
 
#define PWM_2_GENB_ACTZERO_NONE   0x00000000
 
#define PWM_2_GENB_ACTZERO_INV   0x00000001
 
#define PWM_2_GENB_ACTZERO_ZERO   0x00000002
 
#define PWM_2_GENB_ACTZERO_ONE   0x00000003
 
#define PWM_2_DBCTL_ENABLE   0x00000001
 
#define PWM_2_DBRISE_RISEDELAY_M    0x00000FFF
 
#define PWM_2_DBRISE_RISEDELAY_S    0
 
#define PWM_2_DBFALL_FALLDELAY_M    0x00000FFF
 
#define PWM_2_DBFALL_FALLDELAY_S    0
 
#define PWM_2_FLTSRC0_FAULT1   0x00000002
 
#define PWM_2_FLTSRC0_FAULT0   0x00000001
 
#define PWM_2_FLTSRC1_DCMP7   0x00000080
 
#define PWM_2_FLTSRC1_DCMP6   0x00000040
 
#define PWM_2_FLTSRC1_DCMP5   0x00000020
 
#define PWM_2_FLTSRC1_DCMP4   0x00000010
 
#define PWM_2_FLTSRC1_DCMP3   0x00000008
 
#define PWM_2_FLTSRC1_DCMP2   0x00000004
 
#define PWM_2_FLTSRC1_DCMP1   0x00000002
 
#define PWM_2_FLTSRC1_DCMP0   0x00000001
 
#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF
 
#define PWM_2_MINFLTPER_MFP_S   0
 
#define PWM_3_CTL_LATCH   0x00040000
 
#define PWM_3_CTL_MINFLTPER   0x00020000
 
#define PWM_3_CTL_FLTSRC   0x00010000
 
#define PWM_3_CTL_DBFALLUPD_M   0x0000C000
 
#define PWM_3_CTL_DBFALLUPD_I   0x00000000
 
#define PWM_3_CTL_DBFALLUPD_LS   0x00008000
 
#define PWM_3_CTL_DBFALLUPD_GS   0x0000C000
 
#define PWM_3_CTL_DBRISEUPD_M   0x00003000
 
#define PWM_3_CTL_DBRISEUPD_I   0x00000000
 
#define PWM_3_CTL_DBRISEUPD_LS   0x00002000
 
#define PWM_3_CTL_DBRISEUPD_GS   0x00003000
 
#define PWM_3_CTL_DBCTLUPD_M   0x00000C00
 
#define PWM_3_CTL_DBCTLUPD_I   0x00000000
 
#define PWM_3_CTL_DBCTLUPD_LS   0x00000800
 
#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00
 
#define PWM_3_CTL_GENBUPD_M   0x00000300
 
#define PWM_3_CTL_GENBUPD_I   0x00000000
 
#define PWM_3_CTL_GENBUPD_LS   0x00000200
 
#define PWM_3_CTL_GENBUPD_GS   0x00000300
 
#define PWM_3_CTL_GENAUPD_M   0x000000C0
 
#define PWM_3_CTL_GENAUPD_I   0x00000000
 
#define PWM_3_CTL_GENAUPD_LS   0x00000080
 
#define PWM_3_CTL_GENAUPD_GS   0x000000C0
 
#define PWM_3_CTL_CMPBUPD   0x00000020
 
#define PWM_3_CTL_CMPAUPD   0x00000010
 
#define PWM_3_CTL_LOADUPD   0x00000008
 
#define PWM_3_CTL_DEBUG   0x00000004
 
#define PWM_3_CTL_MODE   0x00000002
 
#define PWM_3_CTL_ENABLE   0x00000001
 
#define PWM_3_INTEN_TRCMPBD   0x00002000
 
#define PWM_3_INTEN_TRCMPBU   0x00001000
 
#define PWM_3_INTEN_TRCMPAD   0x00000800
 
#define PWM_3_INTEN_TRCMPAU   0x00000400
 
#define PWM_3_INTEN_TRCNTLOAD   0x00000200
 
#define PWM_3_INTEN_TRCNTZERO   0x00000100
 
#define PWM_3_INTEN_INTCMPBD   0x00000020
 
#define PWM_3_INTEN_INTCMPBU   0x00000010
 
#define PWM_3_INTEN_INTCMPAD   0x00000008
 
#define PWM_3_INTEN_INTCMPAU   0x00000004
 
#define PWM_3_INTEN_INTCNTLOAD   0x00000002
 
#define PWM_3_INTEN_INTCNTZERO   0x00000001
 
#define PWM_3_RIS_INTCMPBD   0x00000020
 
#define PWM_3_RIS_INTCMPBU   0x00000010
 
#define PWM_3_RIS_INTCMPAD   0x00000008
 
#define PWM_3_RIS_INTCMPAU   0x00000004
 
#define PWM_3_RIS_INTCNTLOAD   0x00000002
 
#define PWM_3_RIS_INTCNTZERO   0x00000001
 
#define PWM_3_ISC_INTCMPBD   0x00000020
 
#define PWM_3_ISC_INTCMPBU   0x00000010
 
#define PWM_3_ISC_INTCMPAD   0x00000008
 
#define PWM_3_ISC_INTCMPAU   0x00000004
 
#define PWM_3_ISC_INTCNTLOAD   0x00000002
 
#define PWM_3_ISC_INTCNTZERO   0x00000001
 
#define PWM_3_LOAD_LOAD_M   0x0000FFFF
 
#define PWM_3_LOAD_LOAD_S   0
 
#define PWM_3_COUNT_COUNT_M   0x0000FFFF
 
#define PWM_3_COUNT_COUNT_S   0
 
#define PWM_3_CMPA_COMPA_M   0x0000FFFF
 
#define PWM_3_CMPA_COMPA_S   0
 
#define PWM_3_CMPB_COMPB_M   0x0000FFFF
 
#define PWM_3_CMPB_COMPB_S   0
 
#define PWM_3_GENA_ACTCMPBD_M   0x00000C00
 
#define PWM_3_GENA_ACTCMPBD_NONE    0x00000000
 
#define PWM_3_GENA_ACTCMPBD_INV   0x00000400
 
#define PWM_3_GENA_ACTCMPBD_ZERO    0x00000800
 
#define PWM_3_GENA_ACTCMPBD_ONE   0x00000C00
 
#define PWM_3_GENA_ACTCMPBU_M   0x00000300
 
#define PWM_3_GENA_ACTCMPBU_NONE    0x00000000
 
#define PWM_3_GENA_ACTCMPBU_INV   0x00000100
 
#define PWM_3_GENA_ACTCMPBU_ZERO    0x00000200
 
#define PWM_3_GENA_ACTCMPBU_ONE   0x00000300
 
#define PWM_3_GENA_ACTCMPAD_M   0x000000C0
 
#define PWM_3_GENA_ACTCMPAD_NONE    0x00000000
 
#define PWM_3_GENA_ACTCMPAD_INV   0x00000040
 
#define PWM_3_GENA_ACTCMPAD_ZERO    0x00000080
 
#define PWM_3_GENA_ACTCMPAD_ONE   0x000000C0
 
#define PWM_3_GENA_ACTCMPAU_M   0x00000030
 
#define PWM_3_GENA_ACTCMPAU_NONE    0x00000000
 
#define PWM_3_GENA_ACTCMPAU_INV   0x00000010
 
#define PWM_3_GENA_ACTCMPAU_ZERO    0x00000020
 
#define PWM_3_GENA_ACTCMPAU_ONE   0x00000030
 
#define PWM_3_GENA_ACTLOAD_M   0x0000000C
 
#define PWM_3_GENA_ACTLOAD_NONE   0x00000000
 
#define PWM_3_GENA_ACTLOAD_INV   0x00000004
 
#define PWM_3_GENA_ACTLOAD_ZERO   0x00000008
 
#define PWM_3_GENA_ACTLOAD_ONE   0x0000000C
 
#define PWM_3_GENA_ACTZERO_M   0x00000003
 
#define PWM_3_GENA_ACTZERO_NONE   0x00000000
 
#define PWM_3_GENA_ACTZERO_INV   0x00000001
 
#define PWM_3_GENA_ACTZERO_ZERO   0x00000002
 
#define PWM_3_GENA_ACTZERO_ONE   0x00000003
 
#define PWM_3_GENB_ACTCMPBD_M   0x00000C00
 
#define PWM_3_GENB_ACTCMPBD_NONE    0x00000000
 
#define PWM_3_GENB_ACTCMPBD_INV   0x00000400
 
#define PWM_3_GENB_ACTCMPBD_ZERO    0x00000800
 
#define PWM_3_GENB_ACTCMPBD_ONE   0x00000C00
 
#define PWM_3_GENB_ACTCMPBU_M   0x00000300
 
#define PWM_3_GENB_ACTCMPBU_NONE    0x00000000
 
#define PWM_3_GENB_ACTCMPBU_INV   0x00000100
 
#define PWM_3_GENB_ACTCMPBU_ZERO    0x00000200
 
#define PWM_3_GENB_ACTCMPBU_ONE   0x00000300
 
#define PWM_3_GENB_ACTCMPAD_M   0x000000C0
 
#define PWM_3_GENB_ACTCMPAD_NONE    0x00000000
 
#define PWM_3_GENB_ACTCMPAD_INV   0x00000040
 
#define PWM_3_GENB_ACTCMPAD_ZERO    0x00000080
 
#define PWM_3_GENB_ACTCMPAD_ONE   0x000000C0
 
#define PWM_3_GENB_ACTCMPAU_M   0x00000030
 
#define PWM_3_GENB_ACTCMPAU_NONE    0x00000000
 
#define PWM_3_GENB_ACTCMPAU_INV   0x00000010
 
#define PWM_3_GENB_ACTCMPAU_ZERO    0x00000020
 
#define PWM_3_GENB_ACTCMPAU_ONE   0x00000030
 
#define PWM_3_GENB_ACTLOAD_M   0x0000000C
 
#define PWM_3_GENB_ACTLOAD_NONE   0x00000000
 
#define PWM_3_GENB_ACTLOAD_INV   0x00000004
 
#define PWM_3_GENB_ACTLOAD_ZERO   0x00000008
 
#define PWM_3_GENB_ACTLOAD_ONE   0x0000000C
 
#define PWM_3_GENB_ACTZERO_M   0x00000003
 
#define PWM_3_GENB_ACTZERO_NONE   0x00000000
 
#define PWM_3_GENB_ACTZERO_INV   0x00000001
 
#define PWM_3_GENB_ACTZERO_ZERO   0x00000002
 
#define PWM_3_GENB_ACTZERO_ONE   0x00000003
 
#define PWM_3_DBCTL_ENABLE   0x00000001
 
#define PWM_3_DBRISE_RISEDELAY_M    0x00000FFF
 
#define PWM_3_DBRISE_RISEDELAY_S    0
 
#define PWM_3_DBFALL_FALLDELAY_M    0x00000FFF
 
#define PWM_3_DBFALL_FALLDELAY_S    0
 
#define PWM_3_FLTSRC0_FAULT1   0x00000002
 
#define PWM_3_FLTSRC0_FAULT0   0x00000001
 
#define PWM_3_FLTSRC1_DCMP7   0x00000080
 
#define PWM_3_FLTSRC1_DCMP6   0x00000040
 
#define PWM_3_FLTSRC1_DCMP5   0x00000020
 
#define PWM_3_FLTSRC1_DCMP4   0x00000010
 
#define PWM_3_FLTSRC1_DCMP3   0x00000008
 
#define PWM_3_FLTSRC1_DCMP2   0x00000004
 
#define PWM_3_FLTSRC1_DCMP1   0x00000002
 
#define PWM_3_FLTSRC1_DCMP0   0x00000001
 
#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF
 
#define PWM_3_MINFLTPER_MFP_S   0
 
#define PWM_0_FLTSEN_FAULT1   0x00000002
 
#define PWM_0_FLTSEN_FAULT0   0x00000001
 
#define PWM_0_FLTSTAT0_FAULT1   0x00000002
 
#define PWM_0_FLTSTAT0_FAULT0   0x00000001
 
#define PWM_0_FLTSTAT1_DCMP7   0x00000080
 
#define PWM_0_FLTSTAT1_DCMP6   0x00000040
 
#define PWM_0_FLTSTAT1_DCMP5   0x00000020
 
#define PWM_0_FLTSTAT1_DCMP4   0x00000010
 
#define PWM_0_FLTSTAT1_DCMP3   0x00000008
 
#define PWM_0_FLTSTAT1_DCMP2   0x00000004
 
#define PWM_0_FLTSTAT1_DCMP1   0x00000002
 
#define PWM_0_FLTSTAT1_DCMP0   0x00000001
 
#define PWM_1_FLTSEN_FAULT1   0x00000002
 
#define PWM_1_FLTSEN_FAULT0   0x00000001
 
#define PWM_1_FLTSTAT0_FAULT1   0x00000002
 
#define PWM_1_FLTSTAT0_FAULT0   0x00000001
 
#define PWM_1_FLTSTAT1_DCMP7   0x00000080
 
#define PWM_1_FLTSTAT1_DCMP6   0x00000040
 
#define PWM_1_FLTSTAT1_DCMP5   0x00000020
 
#define PWM_1_FLTSTAT1_DCMP4   0x00000010
 
#define PWM_1_FLTSTAT1_DCMP3   0x00000008
 
#define PWM_1_FLTSTAT1_DCMP2   0x00000004
 
#define PWM_1_FLTSTAT1_DCMP1   0x00000002
 
#define PWM_1_FLTSTAT1_DCMP0   0x00000001
 
#define PWM_2_FLTSTAT0_FAULT1   0x00000002
 
#define PWM_2_FLTSTAT0_FAULT0   0x00000001
 
#define PWM_2_FLTSTAT1_DCMP7   0x00000080
 
#define PWM_2_FLTSTAT1_DCMP6   0x00000040
 
#define PWM_2_FLTSTAT1_DCMP5   0x00000020
 
#define PWM_2_FLTSTAT1_DCMP4   0x00000010
 
#define PWM_2_FLTSTAT1_DCMP3   0x00000008
 
#define PWM_2_FLTSTAT1_DCMP2   0x00000004
 
#define PWM_2_FLTSTAT1_DCMP1   0x00000002
 
#define PWM_2_FLTSTAT1_DCMP0   0x00000001
 
#define PWM_3_FLTSTAT0_FAULT1   0x00000002
 
#define PWM_3_FLTSTAT0_FAULT0   0x00000001
 
#define PWM_3_FLTSTAT1_DCMP7   0x00000080
 
#define PWM_3_FLTSTAT1_DCMP6   0x00000040
 
#define PWM_3_FLTSTAT1_DCMP5   0x00000020
 
#define PWM_3_FLTSTAT1_DCMP4   0x00000010
 
#define PWM_3_FLTSTAT1_DCMP3   0x00000008
 
#define PWM_3_FLTSTAT1_DCMP2   0x00000004
 
#define PWM_3_FLTSTAT1_DCMP1   0x00000002
 
#define PWM_3_FLTSTAT1_DCMP0   0x00000001
 
#define PWM_PP_ONE   0x00000400
 
#define PWM_PP_EFAULT   0x00000200
 
#define PWM_PP_ESYNC   0x00000100
 
#define PWM_PP_FCNT_M   0x000000F0
 
#define PWM_PP_GCNT_M   0x0000000F
 
#define PWM_PP_FCNT_S   4
 
#define PWM_PP_GCNT_S   0
 
#define QEI_CTL_FILTCNT_M   0x000F0000
 
#define QEI_CTL_FILTEN   0x00002000
 
#define QEI_CTL_STALLEN   0x00001000
 
#define QEI_CTL_INVI   0x00000800
 
#define QEI_CTL_INVB   0x00000400
 
#define QEI_CTL_INVA   0x00000200
 
#define QEI_CTL_VELDIV_M   0x000001C0
 
#define QEI_CTL_VELDIV_1   0x00000000
 
#define QEI_CTL_VELDIV_2   0x00000040
 
#define QEI_CTL_VELDIV_4   0x00000080
 
#define QEI_CTL_VELDIV_8   0x000000C0
 
#define QEI_CTL_VELDIV_16   0x00000100
 
#define QEI_CTL_VELDIV_32   0x00000140
 
#define QEI_CTL_VELDIV_64   0x00000180
 
#define QEI_CTL_VELDIV_128   0x000001C0
 
#define QEI_CTL_VELEN   0x00000020
 
#define QEI_CTL_RESMODE   0x00000010
 
#define QEI_CTL_CAPMODE   0x00000008
 
#define QEI_CTL_SIGMODE   0x00000004
 
#define QEI_CTL_SWAP   0x00000002
 
#define QEI_CTL_ENABLE   0x00000001
 
#define QEI_CTL_FILTCNT_S   16
 
#define QEI_STAT_DIRECTION   0x00000002
 
#define QEI_STAT_ERROR   0x00000001
 
#define QEI_POS_M   0xFFFFFFFF
 
#define QEI_POS_S   0
 
#define QEI_MAXPOS_M   0xFFFFFFFF
 
#define QEI_MAXPOS_S   0
 
#define QEI_LOAD_M   0xFFFFFFFF
 
#define QEI_LOAD_S   0
 
#define QEI_TIME_M   0xFFFFFFFF
 
#define QEI_TIME_S   0
 
#define QEI_COUNT_M   0xFFFFFFFF
 
#define QEI_COUNT_S   0
 
#define QEI_SPEED_M   0xFFFFFFFF
 
#define QEI_SPEED_S   0
 
#define QEI_INTEN_ERROR   0x00000008
 
#define QEI_INTEN_DIR   0x00000004
 
#define QEI_INTEN_TIMER   0x00000002
 
#define QEI_INTEN_INDEX   0x00000001
 
#define QEI_RIS_ERROR   0x00000008
 
#define QEI_RIS_DIR   0x00000004
 
#define QEI_RIS_TIMER   0x00000002
 
#define QEI_RIS_INDEX   0x00000001
 
#define QEI_ISC_ERROR   0x00000008
 
#define QEI_ISC_DIR   0x00000004
 
#define QEI_ISC_TIMER   0x00000002
 
#define QEI_ISC_INDEX   0x00000001
 
#define TIMER_CFG_M   0x00000007
 
#define TIMER_CFG_32_BIT_TIMER   0x00000000
 
#define TIMER_CFG_32_BIT_RTC   0x00000001
 
#define TIMER_CFG_16_BIT   0x00000004
 
#define TIMER_TAMR_TAPLO   0x00000800
 
#define TIMER_TAMR_TAMRSU   0x00000400
 
#define TIMER_TAMR_TAPWMIE   0x00000200
 
#define TIMER_TAMR_TAILD   0x00000100
 
#define TIMER_TAMR_TASNAPS   0x00000080
 
#define TIMER_TAMR_TAWOT   0x00000040
 
#define TIMER_TAMR_TAMIE   0x00000020
 
#define TIMER_TAMR_TACDIR   0x00000010
 
#define TIMER_TAMR_TAAMS   0x00000008
 
#define TIMER_TAMR_TACMR   0x00000004
 
#define TIMER_TAMR_TAMR_M   0x00000003
 
#define TIMER_TAMR_TAMR_1_SHOT   0x00000001
 
#define TIMER_TAMR_TAMR_PERIOD   0x00000002
 
#define TIMER_TAMR_TAMR_CAP   0x00000003
 
#define TIMER_TBMR_TBPLO   0x00000800
 
#define TIMER_TBMR_TBMRSU   0x00000400
 
#define TIMER_TBMR_TBPWMIE   0x00000200
 
#define TIMER_TBMR_TBILD   0x00000100
 
#define TIMER_TBMR_TBSNAPS   0x00000080
 
#define TIMER_TBMR_TBWOT   0x00000040
 
#define TIMER_TBMR_TBMIE   0x00000020
 
#define TIMER_TBMR_TBCDIR   0x00000010
 
#define TIMER_TBMR_TBAMS   0x00000008
 
#define TIMER_TBMR_TBCMR   0x00000004
 
#define TIMER_TBMR_TBMR_M   0x00000003
 
#define TIMER_TBMR_TBMR_1_SHOT   0x00000001
 
#define TIMER_TBMR_TBMR_PERIOD   0x00000002
 
#define TIMER_TBMR_TBMR_CAP   0x00000003
 
#define TIMER_CTL_TBPWML   0x00004000
 
#define TIMER_CTL_TBOTE   0x00002000
 
#define TIMER_CTL_TBEVENT_M   0x00000C00
 
#define TIMER_CTL_TBEVENT_POS   0x00000000
 
#define TIMER_CTL_TBEVENT_NEG   0x00000400
 
#define TIMER_CTL_TBEVENT_BOTH   0x00000C00
 
#define TIMER_CTL_TBSTALL   0x00000200
 
#define TIMER_CTL_TBEN   0x00000100
 
#define TIMER_CTL_TAPWML   0x00000040
 
#define TIMER_CTL_TAOTE   0x00000020
 
#define TIMER_CTL_RTCEN   0x00000010
 
#define TIMER_CTL_TAEVENT_M   0x0000000C
 
#define TIMER_CTL_TAEVENT_POS   0x00000000
 
#define TIMER_CTL_TAEVENT_NEG   0x00000004
 
#define TIMER_CTL_TAEVENT_BOTH   0x0000000C
 
#define TIMER_CTL_TASTALL   0x00000002
 
#define TIMER_CTL_TAEN   0x00000001
 
#define TIMER_SYNC_SYNCWT5_M   0x00C00000
 
#define TIMER_SYNC_SYNCWT5_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT5_TA   0x00400000
 
#define TIMER_SYNC_SYNCWT5_TB   0x00800000
 
#define TIMER_SYNC_SYNCWT5_TATB   0x00C00000
 
#define TIMER_SYNC_SYNCWT4_M   0x00300000
 
#define TIMER_SYNC_SYNCWT4_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT4_TA   0x00100000
 
#define TIMER_SYNC_SYNCWT4_TB   0x00200000
 
#define TIMER_SYNC_SYNCWT4_TATB   0x00300000
 
#define TIMER_SYNC_SYNCWT3_M   0x000C0000
 
#define TIMER_SYNC_SYNCWT3_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT3_TA   0x00040000
 
#define TIMER_SYNC_SYNCWT3_TB   0x00080000
 
#define TIMER_SYNC_SYNCWT3_TATB   0x000C0000
 
#define TIMER_SYNC_SYNCWT2_M   0x00030000
 
#define TIMER_SYNC_SYNCWT2_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT2_TA   0x00010000
 
#define TIMER_SYNC_SYNCWT2_TB   0x00020000
 
#define TIMER_SYNC_SYNCWT2_TATB   0x00030000
 
#define TIMER_SYNC_SYNCWT1_M   0x0000C000
 
#define TIMER_SYNC_SYNCWT1_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT1_TA   0x00004000
 
#define TIMER_SYNC_SYNCWT1_TB   0x00008000
 
#define TIMER_SYNC_SYNCWT1_TATB   0x0000C000
 
#define TIMER_SYNC_SYNCWT0_M   0x00003000
 
#define TIMER_SYNC_SYNCWT0_NONE   0x00000000
 
#define TIMER_SYNC_SYNCWT0_TA   0x00001000
 
#define TIMER_SYNC_SYNCWT0_TB   0x00002000
 
#define TIMER_SYNC_SYNCWT0_TATB   0x00003000
 
#define TIMER_SYNC_SYNCT5_M   0x00000C00
 
#define TIMER_SYNC_SYNCT5_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT5_TA   0x00000400
 
#define TIMER_SYNC_SYNCT5_TB   0x00000800
 
#define TIMER_SYNC_SYNCT5_TATB   0x00000C00
 
#define TIMER_SYNC_SYNCT4_M   0x00000300
 
#define TIMER_SYNC_SYNCT4_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT4_TA   0x00000100
 
#define TIMER_SYNC_SYNCT4_TB   0x00000200
 
#define TIMER_SYNC_SYNCT4_TATB   0x00000300
 
#define TIMER_SYNC_SYNCT3_M   0x000000C0
 
#define TIMER_SYNC_SYNCT3_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT3_TA   0x00000040
 
#define TIMER_SYNC_SYNCT3_TB   0x00000080
 
#define TIMER_SYNC_SYNCT3_TATB   0x000000C0
 
#define TIMER_SYNC_SYNCT2_M   0x00000030
 
#define TIMER_SYNC_SYNCT2_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT2_TA   0x00000010
 
#define TIMER_SYNC_SYNCT2_TB   0x00000020
 
#define TIMER_SYNC_SYNCT2_TATB   0x00000030
 
#define TIMER_SYNC_SYNCT1_M   0x0000000C
 
#define TIMER_SYNC_SYNCT1_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT1_TA   0x00000004
 
#define TIMER_SYNC_SYNCT1_TB   0x00000008
 
#define TIMER_SYNC_SYNCT1_TATB   0x0000000C
 
#define TIMER_SYNC_SYNCT0_M   0x00000003
 
#define TIMER_SYNC_SYNCT0_NONE   0x00000000
 
#define TIMER_SYNC_SYNCT0_TA   0x00000001
 
#define TIMER_SYNC_SYNCT0_TB   0x00000002
 
#define TIMER_SYNC_SYNCT0_TATB   0x00000003
 
#define TIMER_IMR_WUEIM   0x00010000
 
#define TIMER_IMR_TBMIM   0x00000800
 
#define TIMER_IMR_CBEIM   0x00000400
 
#define TIMER_IMR_CBMIM   0x00000200
 
#define TIMER_IMR_TBTOIM   0x00000100
 
#define TIMER_IMR_TAMIM   0x00000010
 
#define TIMER_IMR_RTCIM   0x00000008
 
#define TIMER_IMR_CAEIM   0x00000004
 
#define TIMER_IMR_CAMIM   0x00000002
 
#define TIMER_IMR_TATOIM   0x00000001
 
#define TIMER_RIS_WUERIS   0x00010000
 
#define TIMER_RIS_TBMRIS   0x00000800
 
#define TIMER_RIS_CBERIS   0x00000400
 
#define TIMER_RIS_CBMRIS   0x00000200
 
#define TIMER_RIS_TBTORIS   0x00000100
 
#define TIMER_RIS_TAMRIS   0x00000010
 
#define TIMER_RIS_RTCRIS   0x00000008
 
#define TIMER_RIS_CAERIS   0x00000004
 
#define TIMER_RIS_CAMRIS   0x00000002
 
#define TIMER_RIS_TATORIS   0x00000001
 
#define TIMER_MIS_WUEMIS   0x00010000
 
#define TIMER_MIS_TBMMIS   0x00000800
 
#define TIMER_MIS_CBEMIS   0x00000400
 
#define TIMER_MIS_CBMMIS   0x00000200
 
#define TIMER_MIS_TBTOMIS   0x00000100
 
#define TIMER_MIS_TAMMIS   0x00000010
 
#define TIMER_MIS_RTCMIS   0x00000008
 
#define TIMER_MIS_CAEMIS   0x00000004
 
#define TIMER_MIS_CAMMIS   0x00000002
 
#define TIMER_MIS_TATOMIS   0x00000001
 
#define TIMER_ICR_WUECINT   0x00010000
 
#define TIMER_ICR_TBMCINT   0x00000800
 
#define TIMER_ICR_CBECINT   0x00000400
 
#define TIMER_ICR_CBMCINT   0x00000200
 
#define TIMER_ICR_TBTOCINT   0x00000100
 
#define TIMER_ICR_TAMCINT   0x00000010
 
#define TIMER_ICR_RTCCINT   0x00000008
 
#define TIMER_ICR_CAECINT   0x00000004
 
#define TIMER_ICR_CAMCINT   0x00000002
 
#define TIMER_ICR_TATOCINT   0x00000001
 
#define TIMER_TAILR_M   0xFFFFFFFF
 
#define TIMER_TAILR_S   0
 
#define TIMER_TBILR_M   0xFFFFFFFF
 
#define TIMER_TBILR_S   0
 
#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF
 
#define TIMER_TAMATCHR_TAMR_S   0
 
#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF
 
#define TIMER_TBMATCHR_TBMR_S   0
 
#define TIMER_TAPR_TAPSRH_M   0x0000FF00
 
#define TIMER_TAPR_TAPSR_M   0x000000FF
 
#define TIMER_TAPR_TAPSRH_S   8
 
#define TIMER_TAPR_TAPSR_S   0
 
#define TIMER_TBPR_TBPSRH_M   0x0000FF00
 
#define TIMER_TBPR_TBPSR_M   0x000000FF
 
#define TIMER_TBPR_TBPSRH_S   8
 
#define TIMER_TBPR_TBPSR_S   0
 
#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00
 
#define TIMER_TAPMR_TAPSMR_M   0x000000FF
 
#define TIMER_TAPMR_TAPSMRH_S   8
 
#define TIMER_TAPMR_TAPSMR_S   0
 
#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00
 
#define TIMER_TBPMR_TBPSMR_M   0x000000FF
 
#define TIMER_TBPMR_TBPSMRH_S   8
 
#define TIMER_TBPMR_TBPSMR_S   0
 
#define TIMER_TAR_M   0xFFFFFFFF
 
#define TIMER_TAR_S   0
 
#define TIMER_TBR_M   0xFFFFFFFF
 
#define TIMER_TBR_S   0
 
#define TIMER_TAV_M   0xFFFFFFFF
 
#define TIMER_TAV_S   0
 
#define TIMER_TBV_M   0xFFFFFFFF
 
#define TIMER_TBV_S   0
 
#define TIMER_RTCPD_RTCPD_M   0x0000FFFF
 
#define TIMER_RTCPD_RTCPD_S   0
 
#define TIMER_TAPS_PSS_M   0x0000FFFF
 
#define TIMER_TAPS_PSS_S   0
 
#define TIMER_TBPS_PSS_M   0x0000FFFF
 
#define TIMER_TBPS_PSS_S   0
 
#define TIMER_TAPV_PSV_M   0x0000FFFF
 
#define TIMER_TAPV_PSV_S   0
 
#define TIMER_TBPV_PSV_M   0x0000FFFF
 
#define TIMER_TBPV_PSV_S   0
 
#define TIMER_PP_SIZE_M   0x0000000F
 
#define TIMER_PP_SIZE_16   0x00000000
 
#define TIMER_PP_SIZE_32   0x00000001
 
#define ADC_ACTSS_BUSY   0x00010000
 
#define ADC_ACTSS_ASEN3   0x00000008
 
#define ADC_ACTSS_ASEN2   0x00000004
 
#define ADC_ACTSS_ASEN1   0x00000002
 
#define ADC_ACTSS_ASEN0   0x00000001
 
#define ADC_RIS_INRDC   0x00010000
 
#define ADC_RIS_INR3   0x00000008
 
#define ADC_RIS_INR2   0x00000004
 
#define ADC_RIS_INR1   0x00000002
 
#define ADC_RIS_INR0   0x00000001
 
#define ADC_IM_DCONSS3   0x00080000
 
#define ADC_IM_DCONSS2   0x00040000
 
#define ADC_IM_DCONSS1   0x00020000
 
#define ADC_IM_DCONSS0   0x00010000
 
#define ADC_IM_MASK3   0x00000008
 
#define ADC_IM_MASK2   0x00000004
 
#define ADC_IM_MASK1   0x00000002
 
#define ADC_IM_MASK0   0x00000001
 
#define ADC_ISC_DCINSS3   0x00080000
 
#define ADC_ISC_DCINSS2   0x00040000
 
#define ADC_ISC_DCINSS1   0x00020000
 
#define ADC_ISC_DCINSS0   0x00010000
 
#define ADC_ISC_IN3   0x00000008
 
#define ADC_ISC_IN2   0x00000004
 
#define ADC_ISC_IN1   0x00000002
 
#define ADC_ISC_IN0   0x00000001
 
#define ADC_OSTAT_OV3   0x00000008
 
#define ADC_OSTAT_OV2   0x00000004
 
#define ADC_OSTAT_OV1   0x00000002
 
#define ADC_OSTAT_OV0   0x00000001
 
#define ADC_EMUX_EM3_M   0x0000F000
 
#define ADC_EMUX_EM3_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM3_COMP0   0x00001000
 
#define ADC_EMUX_EM3_COMP1   0x00002000
 
#define ADC_EMUX_EM3_EXTERNAL   0x00004000
 
#define ADC_EMUX_EM3_TIMER   0x00005000
 
#define ADC_EMUX_EM3_PWM0   0x00006000
 
#define ADC_EMUX_EM3_PWM1   0x00007000
 
#define ADC_EMUX_EM3_PWM2   0x00008000
 
#define ADC_EMUX_EM3_PWM3   0x00009000
 
#define ADC_EMUX_EM3_ALWAYS   0x0000F000
 
#define ADC_EMUX_EM2_M   0x00000F00
 
#define ADC_EMUX_EM2_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM2_COMP0   0x00000100
 
#define ADC_EMUX_EM2_COMP1   0x00000200
 
#define ADC_EMUX_EM2_EXTERNAL   0x00000400
 
#define ADC_EMUX_EM2_TIMER   0x00000500
 
#define ADC_EMUX_EM2_PWM0   0x00000600
 
#define ADC_EMUX_EM2_PWM1   0x00000700
 
#define ADC_EMUX_EM2_PWM2   0x00000800
 
#define ADC_EMUX_EM2_PWM3   0x00000900
 
#define ADC_EMUX_EM2_ALWAYS   0x00000F00
 
#define ADC_EMUX_EM1_M   0x000000F0
 
#define ADC_EMUX_EM1_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM1_COMP0   0x00000010
 
#define ADC_EMUX_EM1_COMP1   0x00000020
 
#define ADC_EMUX_EM1_EXTERNAL   0x00000040
 
#define ADC_EMUX_EM1_TIMER   0x00000050
 
#define ADC_EMUX_EM1_PWM0   0x00000060
 
#define ADC_EMUX_EM1_PWM1   0x00000070
 
#define ADC_EMUX_EM1_PWM2   0x00000080
 
#define ADC_EMUX_EM1_PWM3   0x00000090
 
#define ADC_EMUX_EM1_ALWAYS   0x000000F0
 
#define ADC_EMUX_EM0_M   0x0000000F
 
#define ADC_EMUX_EM0_PROCESSOR   0x00000000
 
#define ADC_EMUX_EM0_COMP0   0x00000001
 
#define ADC_EMUX_EM0_COMP1   0x00000002
 
#define ADC_EMUX_EM0_EXTERNAL   0x00000004
 
#define ADC_EMUX_EM0_TIMER   0x00000005
 
#define ADC_EMUX_EM0_PWM0   0x00000006
 
#define ADC_EMUX_EM0_PWM1   0x00000007
 
#define ADC_EMUX_EM0_PWM2   0x00000008
 
#define ADC_EMUX_EM0_PWM3   0x00000009
 
#define ADC_EMUX_EM0_ALWAYS   0x0000000F
 
#define ADC_USTAT_UV3   0x00000008
 
#define ADC_USTAT_UV2   0x00000004
 
#define ADC_USTAT_UV1   0x00000002
 
#define ADC_USTAT_UV0   0x00000001
 
#define ADC_TSSEL_PS3_M   0x30000000
 
#define ADC_TSSEL_PS3_0   0x00000000
 
#define ADC_TSSEL_PS3_1   0x10000000
 
#define ADC_TSSEL_PS2_M   0x00300000
 
#define ADC_TSSEL_PS2_0   0x00000000
 
#define ADC_TSSEL_PS2_1   0x00100000
 
#define ADC_TSSEL_PS1_M   0x00003000
 
#define ADC_TSSEL_PS1_0   0x00000000
 
#define ADC_TSSEL_PS1_1   0x00001000
 
#define ADC_TSSEL_PS0_M   0x00000030
 
#define ADC_TSSEL_PS0_0   0x00000000
 
#define ADC_TSSEL_PS0_1   0x00000010
 
#define ADC_SSPRI_SS3_M   0x00003000
 
#define ADC_SSPRI_SS2_M   0x00000300
 
#define ADC_SSPRI_SS1_M   0x00000030
 
#define ADC_SSPRI_SS0_M   0x00000003
 
#define ADC_SPC_PHASE_M   0x0000000F
 
#define ADC_SPC_PHASE_0   0x00000000
 
#define ADC_SPC_PHASE_22_5   0x00000001
 
#define ADC_SPC_PHASE_45   0x00000002
 
#define ADC_SPC_PHASE_67_5   0x00000003
 
#define ADC_SPC_PHASE_90   0x00000004
 
#define ADC_SPC_PHASE_112_5   0x00000005
 
#define ADC_SPC_PHASE_135   0x00000006
 
#define ADC_SPC_PHASE_157_5   0x00000007
 
#define ADC_SPC_PHASE_180   0x00000008
 
#define ADC_SPC_PHASE_202_5   0x00000009
 
#define ADC_SPC_PHASE_225   0x0000000A
 
#define ADC_SPC_PHASE_247_5   0x0000000B
 
#define ADC_SPC_PHASE_270   0x0000000C
 
#define ADC_SPC_PHASE_292_5   0x0000000D
 
#define ADC_SPC_PHASE_315   0x0000000E
 
#define ADC_SPC_PHASE_337_5   0x0000000F
 
#define ADC_PSSI_GSYNC   0x80000000
 
#define ADC_PSSI_SYNCWAIT   0x08000000
 
#define ADC_PSSI_SS3   0x00000008
 
#define ADC_PSSI_SS2   0x00000004
 
#define ADC_PSSI_SS1   0x00000002
 
#define ADC_PSSI_SS0   0x00000001
 
#define ADC_SAC_AVG_M   0x00000007
 
#define ADC_SAC_AVG_OFF   0x00000000
 
#define ADC_SAC_AVG_2X   0x00000001
 
#define ADC_SAC_AVG_4X   0x00000002
 
#define ADC_SAC_AVG_8X   0x00000003
 
#define ADC_SAC_AVG_16X   0x00000004
 
#define ADC_SAC_AVG_32X   0x00000005
 
#define ADC_SAC_AVG_64X   0x00000006
 
#define ADC_DCISC_DCINT7   0x00000080
 
#define ADC_DCISC_DCINT6   0x00000040
 
#define ADC_DCISC_DCINT5   0x00000020
 
#define ADC_DCISC_DCINT4   0x00000010
 
#define ADC_DCISC_DCINT3   0x00000008
 
#define ADC_DCISC_DCINT2   0x00000004
 
#define ADC_DCISC_DCINT1   0x00000002
 
#define ADC_DCISC_DCINT0   0x00000001
 
#define ADC_CTL_DITHER   0x00000040
 
#define ADC_CTL_VREF_M   0x00000001
 
#define ADC_CTL_VREF_INTERNAL   0x00000000
 
#define ADC_SSMUX0_MUX7_M   0xF0000000
 
#define ADC_SSMUX0_MUX6_M   0x0F000000
 
#define ADC_SSMUX0_MUX5_M   0x00F00000
 
#define ADC_SSMUX0_MUX4_M   0x000F0000
 
#define ADC_SSMUX0_MUX3_M   0x0000F000
 
#define ADC_SSMUX0_MUX2_M   0x00000F00
 
#define ADC_SSMUX0_MUX1_M   0x000000F0
 
#define ADC_SSMUX0_MUX0_M   0x0000000F
 
#define ADC_SSMUX0_MUX7_S   28
 
#define ADC_SSMUX0_MUX6_S   24
 
#define ADC_SSMUX0_MUX5_S   20
 
#define ADC_SSMUX0_MUX4_S   16
 
#define ADC_SSMUX0_MUX3_S   12
 
#define ADC_SSMUX0_MUX2_S   8
 
#define ADC_SSMUX0_MUX1_S   4
 
#define ADC_SSMUX0_MUX0_S   0
 
#define ADC_SSCTL0_TS7   0x80000000
 
#define ADC_SSCTL0_IE7   0x40000000
 
#define ADC_SSCTL0_END7   0x20000000
 
#define ADC_SSCTL0_D7   0x10000000
 
#define ADC_SSCTL0_TS6   0x08000000
 
#define ADC_SSCTL0_IE6   0x04000000
 
#define ADC_SSCTL0_END6   0x02000000
 
#define ADC_SSCTL0_D6   0x01000000
 
#define ADC_SSCTL0_TS5   0x00800000
 
#define ADC_SSCTL0_IE5   0x00400000
 
#define ADC_SSCTL0_END5   0x00200000
 
#define ADC_SSCTL0_D5   0x00100000
 
#define ADC_SSCTL0_TS4   0x00080000
 
#define ADC_SSCTL0_IE4   0x00040000
 
#define ADC_SSCTL0_END4   0x00020000
 
#define ADC_SSCTL0_D4   0x00010000
 
#define ADC_SSCTL0_TS3   0x00008000
 
#define ADC_SSCTL0_IE3   0x00004000
 
#define ADC_SSCTL0_END3   0x00002000
 
#define ADC_SSCTL0_D3   0x00001000
 
#define ADC_SSCTL0_TS2   0x00000800
 
#define ADC_SSCTL0_IE2   0x00000400
 
#define ADC_SSCTL0_END2   0x00000200
 
#define ADC_SSCTL0_D2   0x00000100
 
#define ADC_SSCTL0_TS1   0x00000080
 
#define ADC_SSCTL0_IE1   0x00000040
 
#define ADC_SSCTL0_END1   0x00000020
 
#define ADC_SSCTL0_D1   0x00000010
 
#define ADC_SSCTL0_TS0   0x00000008
 
#define ADC_SSCTL0_IE0   0x00000004
 
#define ADC_SSCTL0_END0   0x00000002
 
#define ADC_SSCTL0_D0   0x00000001
 
#define ADC_SSFIFO0_DATA_M   0x00000FFF
 
#define ADC_SSFIFO0_DATA_S   0
 
#define ADC_SSFSTAT0_FULL   0x00001000
 
#define ADC_SSFSTAT0_EMPTY   0x00000100
 
#define ADC_SSFSTAT0_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT0_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT0_HPTR_S   4
 
#define ADC_SSFSTAT0_TPTR_S   0
 
#define ADC_SSOP0_S7DCOP   0x10000000
 
#define ADC_SSOP0_S6DCOP   0x01000000
 
#define ADC_SSOP0_S5DCOP   0x00100000
 
#define ADC_SSOP0_S4DCOP   0x00010000
 
#define ADC_SSOP0_S3DCOP   0x00001000
 
#define ADC_SSOP0_S2DCOP   0x00000100
 
#define ADC_SSOP0_S1DCOP   0x00000010
 
#define ADC_SSOP0_S0DCOP   0x00000001
 
#define ADC_SSDC0_S7DCSEL_M   0xF0000000
 
#define ADC_SSDC0_S6DCSEL_M   0x0F000000
 
#define ADC_SSDC0_S5DCSEL_M   0x00F00000
 
#define ADC_SSDC0_S4DCSEL_M   0x000F0000
 
#define ADC_SSDC0_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC0_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC0_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC0_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC0_S6DCSEL_S   24
 
#define ADC_SSDC0_S5DCSEL_S   20
 
#define ADC_SSDC0_S4DCSEL_S   16
 
#define ADC_SSDC0_S3DCSEL_S   12
 
#define ADC_SSDC0_S2DCSEL_S   8
 
#define ADC_SSDC0_S1DCSEL_S   4
 
#define ADC_SSDC0_S0DCSEL_S   0
 
#define ADC_SSMUX1_MUX3_M   0x0000F000
 
#define ADC_SSMUX1_MUX2_M   0x00000F00
 
#define ADC_SSMUX1_MUX1_M   0x000000F0
 
#define ADC_SSMUX1_MUX0_M   0x0000000F
 
#define ADC_SSMUX1_MUX3_S   12
 
#define ADC_SSMUX1_MUX2_S   8
 
#define ADC_SSMUX1_MUX1_S   4
 
#define ADC_SSMUX1_MUX0_S   0
 
#define ADC_SSCTL1_TS3   0x00008000
 
#define ADC_SSCTL1_IE3   0x00004000
 
#define ADC_SSCTL1_END3   0x00002000
 
#define ADC_SSCTL1_D3   0x00001000
 
#define ADC_SSCTL1_TS2   0x00000800
 
#define ADC_SSCTL1_IE2   0x00000400
 
#define ADC_SSCTL1_END2   0x00000200
 
#define ADC_SSCTL1_D2   0x00000100
 
#define ADC_SSCTL1_TS1   0x00000080
 
#define ADC_SSCTL1_IE1   0x00000040
 
#define ADC_SSCTL1_END1   0x00000020
 
#define ADC_SSCTL1_D1   0x00000010
 
#define ADC_SSCTL1_TS0   0x00000008
 
#define ADC_SSCTL1_IE0   0x00000004
 
#define ADC_SSCTL1_END0   0x00000002
 
#define ADC_SSCTL1_D0   0x00000001
 
#define ADC_SSFIFO1_DATA_M   0x00000FFF
 
#define ADC_SSFIFO1_DATA_S   0
 
#define ADC_SSFSTAT1_FULL   0x00001000
 
#define ADC_SSFSTAT1_EMPTY   0x00000100
 
#define ADC_SSFSTAT1_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT1_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT1_HPTR_S   4
 
#define ADC_SSFSTAT1_TPTR_S   0
 
#define ADC_SSOP1_S3DCOP   0x00001000
 
#define ADC_SSOP1_S2DCOP   0x00000100
 
#define ADC_SSOP1_S1DCOP   0x00000010
 
#define ADC_SSOP1_S0DCOP   0x00000001
 
#define ADC_SSDC1_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC1_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC1_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC1_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC1_S2DCSEL_S   8
 
#define ADC_SSDC1_S1DCSEL_S   4
 
#define ADC_SSDC1_S0DCSEL_S   0
 
#define ADC_SSMUX2_MUX3_M   0x0000F000
 
#define ADC_SSMUX2_MUX2_M   0x00000F00
 
#define ADC_SSMUX2_MUX1_M   0x000000F0
 
#define ADC_SSMUX2_MUX0_M   0x0000000F
 
#define ADC_SSMUX2_MUX3_S   12
 
#define ADC_SSMUX2_MUX2_S   8
 
#define ADC_SSMUX2_MUX1_S   4
 
#define ADC_SSMUX2_MUX0_S   0
 
#define ADC_SSCTL2_TS3   0x00008000
 
#define ADC_SSCTL2_IE3   0x00004000
 
#define ADC_SSCTL2_END3   0x00002000
 
#define ADC_SSCTL2_D3   0x00001000
 
#define ADC_SSCTL2_TS2   0x00000800
 
#define ADC_SSCTL2_IE2   0x00000400
 
#define ADC_SSCTL2_END2   0x00000200
 
#define ADC_SSCTL2_D2   0x00000100
 
#define ADC_SSCTL2_TS1   0x00000080
 
#define ADC_SSCTL2_IE1   0x00000040
 
#define ADC_SSCTL2_END1   0x00000020
 
#define ADC_SSCTL2_D1   0x00000010
 
#define ADC_SSCTL2_TS0   0x00000008
 
#define ADC_SSCTL2_IE0   0x00000004
 
#define ADC_SSCTL2_END0   0x00000002
 
#define ADC_SSCTL2_D0   0x00000001
 
#define ADC_SSFIFO2_DATA_M   0x00000FFF
 
#define ADC_SSFIFO2_DATA_S   0
 
#define ADC_SSFSTAT2_FULL   0x00001000
 
#define ADC_SSFSTAT2_EMPTY   0x00000100
 
#define ADC_SSFSTAT2_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT2_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT2_HPTR_S   4
 
#define ADC_SSFSTAT2_TPTR_S   0
 
#define ADC_SSOP2_S3DCOP   0x00001000
 
#define ADC_SSOP2_S2DCOP   0x00000100
 
#define ADC_SSOP2_S1DCOP   0x00000010
 
#define ADC_SSOP2_S0DCOP   0x00000001
 
#define ADC_SSDC2_S3DCSEL_M   0x0000F000
 
#define ADC_SSDC2_S2DCSEL_M   0x00000F00
 
#define ADC_SSDC2_S1DCSEL_M   0x000000F0
 
#define ADC_SSDC2_S0DCSEL_M   0x0000000F
 
#define ADC_SSDC2_S2DCSEL_S   8
 
#define ADC_SSDC2_S1DCSEL_S   4
 
#define ADC_SSDC2_S0DCSEL_S   0
 
#define ADC_SSMUX3_MUX0_M   0x0000000F
 
#define ADC_SSMUX3_MUX0_S   0
 
#define ADC_SSCTL3_TS0   0x00000008
 
#define ADC_SSCTL3_IE0   0x00000004
 
#define ADC_SSCTL3_END0   0x00000002
 
#define ADC_SSCTL3_D0   0x00000001
 
#define ADC_SSFIFO3_DATA_M   0x00000FFF
 
#define ADC_SSFIFO3_DATA_S   0
 
#define ADC_SSFSTAT3_FULL   0x00001000
 
#define ADC_SSFSTAT3_EMPTY   0x00000100
 
#define ADC_SSFSTAT3_HPTR_M   0x000000F0
 
#define ADC_SSFSTAT3_TPTR_M   0x0000000F
 
#define ADC_SSFSTAT3_HPTR_S   4
 
#define ADC_SSFSTAT3_TPTR_S   0
 
#define ADC_SSOP3_S0DCOP   0x00000001
 
#define ADC_SSDC3_S0DCSEL_M   0x0000000F
 
#define ADC_DCRIC_DCTRIG7   0x00800000
 
#define ADC_DCRIC_DCTRIG6   0x00400000
 
#define ADC_DCRIC_DCTRIG5   0x00200000
 
#define ADC_DCRIC_DCTRIG4   0x00100000
 
#define ADC_DCRIC_DCTRIG3   0x00080000
 
#define ADC_DCRIC_DCTRIG2   0x00040000
 
#define ADC_DCRIC_DCTRIG1   0x00020000
 
#define ADC_DCRIC_DCTRIG0   0x00010000
 
#define ADC_DCRIC_DCINT7   0x00000080
 
#define ADC_DCRIC_DCINT6   0x00000040
 
#define ADC_DCRIC_DCINT5   0x00000020
 
#define ADC_DCRIC_DCINT4   0x00000010
 
#define ADC_DCRIC_DCINT3   0x00000008
 
#define ADC_DCRIC_DCINT2   0x00000004
 
#define ADC_DCRIC_DCINT1   0x00000002
 
#define ADC_DCRIC_DCINT0   0x00000001
 
#define ADC_DCCTL0_CTE   0x00001000
 
#define ADC_DCCTL0_CTC_M   0x00000C00
 
#define ADC_DCCTL0_CTC_LOW   0x00000000
 
#define ADC_DCCTL0_CTC_MID   0x00000400
 
#define ADC_DCCTL0_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL0_CTM_M   0x00000300
 
#define ADC_DCCTL0_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL0_CTM_ONCE   0x00000100
 
#define ADC_DCCTL0_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL0_CTM_HONCE   0x00000300
 
#define ADC_DCCTL0_CIE   0x00000010
 
#define ADC_DCCTL0_CIC_M   0x0000000C
 
#define ADC_DCCTL0_CIC_LOW   0x00000000
 
#define ADC_DCCTL0_CIC_MID   0x00000004
 
#define ADC_DCCTL0_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL0_CIM_M   0x00000003
 
#define ADC_DCCTL0_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL0_CIM_ONCE   0x00000001
 
#define ADC_DCCTL0_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL0_CIM_HONCE   0x00000003
 
#define ADC_DCCTL1_CTE   0x00001000
 
#define ADC_DCCTL1_CTC_M   0x00000C00
 
#define ADC_DCCTL1_CTC_LOW   0x00000000
 
#define ADC_DCCTL1_CTC_MID   0x00000400
 
#define ADC_DCCTL1_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL1_CTM_M   0x00000300
 
#define ADC_DCCTL1_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL1_CTM_ONCE   0x00000100
 
#define ADC_DCCTL1_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL1_CTM_HONCE   0x00000300
 
#define ADC_DCCTL1_CIE   0x00000010
 
#define ADC_DCCTL1_CIC_M   0x0000000C
 
#define ADC_DCCTL1_CIC_LOW   0x00000000
 
#define ADC_DCCTL1_CIC_MID   0x00000004
 
#define ADC_DCCTL1_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL1_CIM_M   0x00000003
 
#define ADC_DCCTL1_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL1_CIM_ONCE   0x00000001
 
#define ADC_DCCTL1_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL1_CIM_HONCE   0x00000003
 
#define ADC_DCCTL2_CTE   0x00001000
 
#define ADC_DCCTL2_CTC_M   0x00000C00
 
#define ADC_DCCTL2_CTC_LOW   0x00000000
 
#define ADC_DCCTL2_CTC_MID   0x00000400
 
#define ADC_DCCTL2_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL2_CTM_M   0x00000300
 
#define ADC_DCCTL2_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL2_CTM_ONCE   0x00000100
 
#define ADC_DCCTL2_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL2_CTM_HONCE   0x00000300
 
#define ADC_DCCTL2_CIE   0x00000010
 
#define ADC_DCCTL2_CIC_M   0x0000000C
 
#define ADC_DCCTL2_CIC_LOW   0x00000000
 
#define ADC_DCCTL2_CIC_MID   0x00000004
 
#define ADC_DCCTL2_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL2_CIM_M   0x00000003
 
#define ADC_DCCTL2_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL2_CIM_ONCE   0x00000001
 
#define ADC_DCCTL2_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL2_CIM_HONCE   0x00000003
 
#define ADC_DCCTL3_CTE   0x00001000
 
#define ADC_DCCTL3_CTC_M   0x00000C00
 
#define ADC_DCCTL3_CTC_LOW   0x00000000
 
#define ADC_DCCTL3_CTC_MID   0x00000400
 
#define ADC_DCCTL3_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL3_CTM_M   0x00000300
 
#define ADC_DCCTL3_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL3_CTM_ONCE   0x00000100
 
#define ADC_DCCTL3_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL3_CTM_HONCE   0x00000300
 
#define ADC_DCCTL3_CIE   0x00000010
 
#define ADC_DCCTL3_CIC_M   0x0000000C
 
#define ADC_DCCTL3_CIC_LOW   0x00000000
 
#define ADC_DCCTL3_CIC_MID   0x00000004
 
#define ADC_DCCTL3_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL3_CIM_M   0x00000003
 
#define ADC_DCCTL3_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL3_CIM_ONCE   0x00000001
 
#define ADC_DCCTL3_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL3_CIM_HONCE   0x00000003
 
#define ADC_DCCTL4_CTE   0x00001000
 
#define ADC_DCCTL4_CTC_M   0x00000C00
 
#define ADC_DCCTL4_CTC_LOW   0x00000000
 
#define ADC_DCCTL4_CTC_MID   0x00000400
 
#define ADC_DCCTL4_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL4_CTM_M   0x00000300
 
#define ADC_DCCTL4_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL4_CTM_ONCE   0x00000100
 
#define ADC_DCCTL4_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL4_CTM_HONCE   0x00000300
 
#define ADC_DCCTL4_CIE   0x00000010
 
#define ADC_DCCTL4_CIC_M   0x0000000C
 
#define ADC_DCCTL4_CIC_LOW   0x00000000
 
#define ADC_DCCTL4_CIC_MID   0x00000004
 
#define ADC_DCCTL4_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL4_CIM_M   0x00000003
 
#define ADC_DCCTL4_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL4_CIM_ONCE   0x00000001
 
#define ADC_DCCTL4_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL4_CIM_HONCE   0x00000003
 
#define ADC_DCCTL5_CTE   0x00001000
 
#define ADC_DCCTL5_CTC_M   0x00000C00
 
#define ADC_DCCTL5_CTC_LOW   0x00000000
 
#define ADC_DCCTL5_CTC_MID   0x00000400
 
#define ADC_DCCTL5_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL5_CTM_M   0x00000300
 
#define ADC_DCCTL5_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL5_CTM_ONCE   0x00000100
 
#define ADC_DCCTL5_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL5_CTM_HONCE   0x00000300
 
#define ADC_DCCTL5_CIE   0x00000010
 
#define ADC_DCCTL5_CIC_M   0x0000000C
 
#define ADC_DCCTL5_CIC_LOW   0x00000000
 
#define ADC_DCCTL5_CIC_MID   0x00000004
 
#define ADC_DCCTL5_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL5_CIM_M   0x00000003
 
#define ADC_DCCTL5_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL5_CIM_ONCE   0x00000001
 
#define ADC_DCCTL5_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL5_CIM_HONCE   0x00000003
 
#define ADC_DCCTL6_CTE   0x00001000
 
#define ADC_DCCTL6_CTC_M   0x00000C00
 
#define ADC_DCCTL6_CTC_LOW   0x00000000
 
#define ADC_DCCTL6_CTC_MID   0x00000400
 
#define ADC_DCCTL6_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL6_CTM_M   0x00000300
 
#define ADC_DCCTL6_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL6_CTM_ONCE   0x00000100
 
#define ADC_DCCTL6_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL6_CTM_HONCE   0x00000300
 
#define ADC_DCCTL6_CIE   0x00000010
 
#define ADC_DCCTL6_CIC_M   0x0000000C
 
#define ADC_DCCTL6_CIC_LOW   0x00000000
 
#define ADC_DCCTL6_CIC_MID   0x00000004
 
#define ADC_DCCTL6_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL6_CIM_M   0x00000003
 
#define ADC_DCCTL6_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL6_CIM_ONCE   0x00000001
 
#define ADC_DCCTL6_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL6_CIM_HONCE   0x00000003
 
#define ADC_DCCTL7_CTE   0x00001000
 
#define ADC_DCCTL7_CTC_M   0x00000C00
 
#define ADC_DCCTL7_CTC_LOW   0x00000000
 
#define ADC_DCCTL7_CTC_MID   0x00000400
 
#define ADC_DCCTL7_CTC_HIGH   0x00000C00
 
#define ADC_DCCTL7_CTM_M   0x00000300
 
#define ADC_DCCTL7_CTM_ALWAYS   0x00000000
 
#define ADC_DCCTL7_CTM_ONCE   0x00000100
 
#define ADC_DCCTL7_CTM_HALWAYS   0x00000200
 
#define ADC_DCCTL7_CTM_HONCE   0x00000300
 
#define ADC_DCCTL7_CIE   0x00000010
 
#define ADC_DCCTL7_CIC_M   0x0000000C
 
#define ADC_DCCTL7_CIC_LOW   0x00000000
 
#define ADC_DCCTL7_CIC_MID   0x00000004
 
#define ADC_DCCTL7_CIC_HIGH   0x0000000C
 
#define ADC_DCCTL7_CIM_M   0x00000003
 
#define ADC_DCCTL7_CIM_ALWAYS   0x00000000
 
#define ADC_DCCTL7_CIM_ONCE   0x00000001
 
#define ADC_DCCTL7_CIM_HALWAYS   0x00000002
 
#define ADC_DCCTL7_CIM_HONCE   0x00000003
 
#define ADC_DCCMP0_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP0_COMP0_M   0x00000FFF
 
#define ADC_DCCMP0_COMP1_S   16
 
#define ADC_DCCMP0_COMP0_S   0
 
#define ADC_DCCMP1_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP1_COMP0_M   0x00000FFF
 
#define ADC_DCCMP1_COMP1_S   16
 
#define ADC_DCCMP1_COMP0_S   0
 
#define ADC_DCCMP2_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP2_COMP0_M   0x00000FFF
 
#define ADC_DCCMP2_COMP1_S   16
 
#define ADC_DCCMP2_COMP0_S   0
 
#define ADC_DCCMP3_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP3_COMP0_M   0x00000FFF
 
#define ADC_DCCMP3_COMP1_S   16
 
#define ADC_DCCMP3_COMP0_S   0
 
#define ADC_DCCMP4_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP4_COMP0_M   0x00000FFF
 
#define ADC_DCCMP4_COMP1_S   16
 
#define ADC_DCCMP4_COMP0_S   0
 
#define ADC_DCCMP5_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP5_COMP0_M   0x00000FFF
 
#define ADC_DCCMP5_COMP1_S   16
 
#define ADC_DCCMP5_COMP0_S   0
 
#define ADC_DCCMP6_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP6_COMP0_M   0x00000FFF
 
#define ADC_DCCMP6_COMP1_S   16
 
#define ADC_DCCMP6_COMP0_S   0
 
#define ADC_DCCMP7_COMP1_M   0x0FFF0000
 
#define ADC_DCCMP7_COMP0_M   0x00000FFF
 
#define ADC_DCCMP7_COMP1_S   16
 
#define ADC_DCCMP7_COMP0_S   0
 
#define ADC_PP_TS   0x00800000
 
#define ADC_PP_RSL_M   0x007C0000
 
#define ADC_PP_TYPE_M   0x00030000
 
#define ADC_PP_TYPE_SAR   0x00000000
 
#define ADC_PP_DC_M   0x0000FC00
 
#define ADC_PP_CH_M   0x000003F0
 
#define ADC_PP_MSR_M   0x0000000F
 
#define ADC_PP_MSR_125K   0x00000001
 
#define ADC_PP_MSR_250K   0x00000003
 
#define ADC_PP_MSR_500K   0x00000005
 
#define ADC_PP_MSR_1M   0x00000007
 
#define ADC_PP_RSL_S   18
 
#define ADC_PP_DC_S   10
 
#define ADC_PP_CH_S   4
 
#define ADC_PC_SR_M   0x0000000F
 
#define ADC_PC_SR_125K   0x00000001
 
#define ADC_PC_SR_250K   0x00000003
 
#define ADC_PC_SR_500K   0x00000005
 
#define ADC_PC_SR_1M   0x00000007
 
#define ADC_CC_CS_M   0x0000000F
 
#define ADC_CC_CS_SYSPLL   0x00000000
 
#define ADC_CC_CS_PIOSC   0x00000001
 
#define COMP_ACMIS_IN1   0x00000002
 
#define COMP_ACMIS_IN0   0x00000001
 
#define COMP_ACRIS_IN1   0x00000002
 
#define COMP_ACRIS_IN0   0x00000001
 
#define COMP_ACINTEN_IN1   0x00000002
 
#define COMP_ACINTEN_IN0   0x00000001
 
#define COMP_ACREFCTL_EN   0x00000200
 
#define COMP_ACREFCTL_RNG   0x00000100
 
#define COMP_ACREFCTL_VREF_M   0x0000000F
 
#define COMP_ACREFCTL_VREF_S   0
 
#define COMP_ACSTAT0_OVAL   0x00000002
 
#define COMP_ACCTL0_TOEN   0x00000800
 
#define COMP_ACCTL0_ASRCP_M   0x00000600
 
#define COMP_ACCTL0_ASRCP_PIN   0x00000000
 
#define COMP_ACCTL0_ASRCP_PIN0   0x00000200
 
#define COMP_ACCTL0_ASRCP_REF   0x00000400
 
#define COMP_ACCTL0_TSLVAL   0x00000080
 
#define COMP_ACCTL0_TSEN_M   0x00000060
 
#define COMP_ACCTL0_TSEN_LEVEL   0x00000000
 
#define COMP_ACCTL0_TSEN_FALL   0x00000020
 
#define COMP_ACCTL0_TSEN_RISE   0x00000040
 
#define COMP_ACCTL0_TSEN_BOTH   0x00000060
 
#define COMP_ACCTL0_ISLVAL   0x00000010
 
#define COMP_ACCTL0_ISEN_M   0x0000000C
 
#define COMP_ACCTL0_ISEN_LEVEL   0x00000000
 
#define COMP_ACCTL0_ISEN_FALL   0x00000004
 
#define COMP_ACCTL0_ISEN_RISE   0x00000008
 
#define COMP_ACCTL0_ISEN_BOTH   0x0000000C
 
#define COMP_ACCTL0_CINV   0x00000002
 
#define COMP_ACSTAT1_OVAL   0x00000002
 
#define COMP_ACCTL1_TOEN   0x00000800
 
#define COMP_ACCTL1_ASRCP_M   0x00000600
 
#define COMP_ACCTL1_ASRCP_PIN   0x00000000
 
#define COMP_ACCTL1_ASRCP_PIN0   0x00000200
 
#define COMP_ACCTL1_ASRCP_REF   0x00000400
 
#define COMP_ACCTL1_TSLVAL   0x00000080
 
#define COMP_ACCTL1_TSEN_M   0x00000060
 
#define COMP_ACCTL1_TSEN_LEVEL   0x00000000
 
#define COMP_ACCTL1_TSEN_FALL   0x00000020
 
#define COMP_ACCTL1_TSEN_RISE   0x00000040
 
#define COMP_ACCTL1_TSEN_BOTH   0x00000060
 
#define COMP_ACCTL1_ISLVAL   0x00000010
 
#define COMP_ACCTL1_ISEN_M   0x0000000C
 
#define COMP_ACCTL1_ISEN_LEVEL   0x00000000
 
#define COMP_ACCTL1_ISEN_FALL   0x00000004
 
#define COMP_ACCTL1_ISEN_RISE   0x00000008
 
#define COMP_ACCTL1_ISEN_BOTH   0x0000000C
 
#define COMP_ACCTL1_CINV   0x00000002
 
#define COMP_PP_C1O   0x00020000
 
#define COMP_PP_C0O   0x00010000
 
#define COMP_PP_CMP1   0x00000002
 
#define COMP_PP_CMP0   0x00000001
 
#define CAN_CTL_TEST   0x00000080
 
#define CAN_CTL_CCE   0x00000040
 
#define CAN_CTL_DAR   0x00000020
 
#define CAN_CTL_EIE   0x00000008
 
#define CAN_CTL_SIE   0x00000004
 
#define CAN_CTL_IE   0x00000002
 
#define CAN_CTL_INIT   0x00000001
 
#define CAN_STS_BOFF   0x00000080
 
#define CAN_STS_EWARN   0x00000040
 
#define CAN_STS_EPASS   0x00000020
 
#define CAN_STS_RXOK   0x00000010
 
#define CAN_STS_TXOK   0x00000008
 
#define CAN_STS_LEC_M   0x00000007
 
#define CAN_STS_LEC_NONE   0x00000000
 
#define CAN_STS_LEC_STUFF   0x00000001
 
#define CAN_STS_LEC_FORM   0x00000002
 
#define CAN_STS_LEC_ACK   0x00000003
 
#define CAN_STS_LEC_BIT1   0x00000004
 
#define CAN_STS_LEC_BIT0   0x00000005
 
#define CAN_STS_LEC_CRC   0x00000006
 
#define CAN_STS_LEC_NOEVENT   0x00000007
 
#define CAN_ERR_RP   0x00008000
 
#define CAN_ERR_REC_M   0x00007F00
 
#define CAN_ERR_TEC_M   0x000000FF
 
#define CAN_ERR_REC_S   8
 
#define CAN_ERR_TEC_S   0
 
#define CAN_BIT_TSEG2_M   0x00007000
 
#define CAN_BIT_TSEG1_M   0x00000F00
 
#define CAN_BIT_SJW_M   0x000000C0
 
#define CAN_BIT_BRP_M   0x0000003F
 
#define CAN_BIT_TSEG2_S   12
 
#define CAN_BIT_TSEG1_S   8
 
#define CAN_BIT_SJW_S   6
 
#define CAN_BIT_BRP_S   0
 
#define CAN_INT_INTID_M   0x0000FFFF
 
#define CAN_INT_INTID_NONE   0x00000000
 
#define CAN_INT_INTID_STATUS   0x00008000
 
#define CAN_TST_RX   0x00000080
 
#define CAN_TST_TX_M   0x00000060
 
#define CAN_TST_TX_CANCTL   0x00000000
 
#define CAN_TST_TX_SAMPLE   0x00000020
 
#define CAN_TST_TX_DOMINANT   0x00000040
 
#define CAN_TST_TX_RECESSIVE   0x00000060
 
#define CAN_TST_LBACK   0x00000010
 
#define CAN_TST_SILENT   0x00000008
 
#define CAN_TST_BASIC   0x00000004
 
#define CAN_BRPE_BRPE_M   0x0000000F
 
#define CAN_BRPE_BRPE_S   0
 
#define CAN_IF1CRQ_BUSY   0x00008000
 
#define CAN_IF1CRQ_MNUM_M   0x0000003F
 
#define CAN_IF1CRQ_MNUM_S   0
 
#define CAN_IF1CMSK_WRNRD   0x00000080
 
#define CAN_IF1CMSK_MASK   0x00000040
 
#define CAN_IF1CMSK_ARB   0x00000020
 
#define CAN_IF1CMSK_CONTROL   0x00000010
 
#define CAN_IF1CMSK_CLRINTPND   0x00000008
 
#define CAN_IF1CMSK_NEWDAT   0x00000004
 
#define CAN_IF1CMSK_TXRQST   0x00000004
 
#define CAN_IF1CMSK_DATAA   0x00000002
 
#define CAN_IF1CMSK_DATAB   0x00000001
 
#define CAN_IF1MSK1_IDMSK_M   0x0000FFFF
 
#define CAN_IF1MSK1_IDMSK_S   0
 
#define CAN_IF1MSK2_MXTD   0x00008000
 
#define CAN_IF1MSK2_MDIR   0x00004000
 
#define CAN_IF1MSK2_IDMSK_M   0x00001FFF
 
#define CAN_IF1MSK2_IDMSK_S   0
 
#define CAN_IF1ARB1_ID_M   0x0000FFFF
 
#define CAN_IF1ARB1_ID_S   0
 
#define CAN_IF1ARB2_MSGVAL   0x00008000
 
#define CAN_IF1ARB2_XTD   0x00004000
 
#define CAN_IF1ARB2_DIR   0x00002000
 
#define CAN_IF1ARB2_ID_M   0x00001FFF
 
#define CAN_IF1ARB2_ID_S   0
 
#define CAN_IF1MCTL_NEWDAT   0x00008000
 
#define CAN_IF1MCTL_MSGLST   0x00004000
 
#define CAN_IF1MCTL_INTPND   0x00002000
 
#define CAN_IF1MCTL_UMASK   0x00001000
 
#define CAN_IF1MCTL_TXIE   0x00000800
 
#define CAN_IF1MCTL_RXIE   0x00000400
 
#define CAN_IF1MCTL_RMTEN   0x00000200
 
#define CAN_IF1MCTL_TXRQST   0x00000100
 
#define CAN_IF1MCTL_EOB   0x00000080
 
#define CAN_IF1MCTL_DLC_M   0x0000000F
 
#define CAN_IF1MCTL_DLC_S   0
 
#define CAN_IF1DA1_DATA_M   0x0000FFFF
 
#define CAN_IF1DA1_DATA_S   0
 
#define CAN_IF1DA2_DATA_M   0x0000FFFF
 
#define CAN_IF1DA2_DATA_S   0
 
#define CAN_IF1DB1_DATA_M   0x0000FFFF
 
#define CAN_IF1DB1_DATA_S   0
 
#define CAN_IF1DB2_DATA_M   0x0000FFFF
 
#define CAN_IF1DB2_DATA_S   0
 
#define CAN_IF2CRQ_BUSY   0x00008000
 
#define CAN_IF2CRQ_MNUM_M   0x0000003F
 
#define CAN_IF2CRQ_MNUM_S   0
 
#define CAN_IF2CMSK_WRNRD   0x00000080
 
#define CAN_IF2CMSK_MASK   0x00000040
 
#define CAN_IF2CMSK_ARB   0x00000020
 
#define CAN_IF2CMSK_CONTROL   0x00000010
 
#define CAN_IF2CMSK_CLRINTPND   0x00000008
 
#define CAN_IF2CMSK_NEWDAT   0x00000004
 
#define CAN_IF2CMSK_TXRQST   0x00000004
 
#define CAN_IF2CMSK_DATAA   0x00000002
 
#define CAN_IF2CMSK_DATAB   0x00000001
 
#define CAN_IF2MSK1_IDMSK_M   0x0000FFFF
 
#define CAN_IF2MSK1_IDMSK_S   0
 
#define CAN_IF2MSK2_MXTD   0x00008000
 
#define CAN_IF2MSK2_MDIR   0x00004000
 
#define CAN_IF2MSK2_IDMSK_M   0x00001FFF
 
#define CAN_IF2MSK2_IDMSK_S   0
 
#define CAN_IF2ARB1_ID_M   0x0000FFFF
 
#define CAN_IF2ARB1_ID_S   0
 
#define CAN_IF2ARB2_MSGVAL   0x00008000
 
#define CAN_IF2ARB2_XTD   0x00004000
 
#define CAN_IF2ARB2_DIR   0x00002000
 
#define CAN_IF2ARB2_ID_M   0x00001FFF
 
#define CAN_IF2ARB2_ID_S   0
 
#define CAN_IF2MCTL_NEWDAT   0x00008000
 
#define CAN_IF2MCTL_MSGLST   0x00004000
 
#define CAN_IF2MCTL_INTPND   0x00002000
 
#define CAN_IF2MCTL_UMASK   0x00001000
 
#define CAN_IF2MCTL_TXIE   0x00000800
 
#define CAN_IF2MCTL_RXIE   0x00000400
 
#define CAN_IF2MCTL_RMTEN   0x00000200
 
#define CAN_IF2MCTL_TXRQST   0x00000100
 
#define CAN_IF2MCTL_EOB   0x00000080
 
#define CAN_IF2MCTL_DLC_M   0x0000000F
 
#define CAN_IF2MCTL_DLC_S   0
 
#define CAN_IF2DA1_DATA_M   0x0000FFFF
 
#define CAN_IF2DA1_DATA_S   0
 
#define CAN_IF2DA2_DATA_M   0x0000FFFF
 
#define CAN_IF2DA2_DATA_S   0
 
#define CAN_IF2DB1_DATA_M   0x0000FFFF
 
#define CAN_IF2DB1_DATA_S   0
 
#define CAN_IF2DB2_DATA_M   0x0000FFFF
 
#define CAN_IF2DB2_DATA_S   0
 
#define CAN_TXRQ1_TXRQST_M   0x0000FFFF
 
#define CAN_TXRQ1_TXRQST_S   0
 
#define CAN_TXRQ2_TXRQST_M   0x0000FFFF
 
#define CAN_TXRQ2_TXRQST_S   0
 
#define CAN_NWDA1_NEWDAT_M   0x0000FFFF
 
#define CAN_NWDA1_NEWDAT_S   0
 
#define CAN_NWDA2_NEWDAT_M   0x0000FFFF
 
#define CAN_NWDA2_NEWDAT_S   0
 
#define CAN_MSG1INT_INTPND_M   0x0000FFFF
 
#define CAN_MSG1INT_INTPND_S   0
 
#define CAN_MSG2INT_INTPND_M   0x0000FFFF
 
#define CAN_MSG2INT_INTPND_S   0
 
#define CAN_MSG1VAL_MSGVAL_M   0x0000FFFF
 
#define CAN_MSG1VAL_MSGVAL_S   0
 
#define CAN_MSG2VAL_MSGVAL_M   0x0000FFFF
 
#define CAN_MSG2VAL_MSGVAL_S   0
 
#define USB_FADDR_M   0x0000007F
 
#define USB_FADDR_S   0
 
#define USB_POWER_ISOUP   0x00000080
 
#define USB_POWER_SOFTCONN   0x00000040
 
#define USB_POWER_RESET   0x00000008
 
#define USB_POWER_RESUME   0x00000004
 
#define USB_POWER_SUSPEND   0x00000002
 
#define USB_POWER_PWRDNPHY   0x00000001
 
#define USB_TXIS_EP7   0x00000080
 
#define USB_TXIS_EP6   0x00000040
 
#define USB_TXIS_EP5   0x00000020
 
#define USB_TXIS_EP4   0x00000010
 
#define USB_TXIS_EP3   0x00000008
 
#define USB_TXIS_EP2   0x00000004
 
#define USB_TXIS_EP1   0x00000002
 
#define USB_TXIS_EP0   0x00000001
 
#define USB_RXIS_EP7   0x00000080
 
#define USB_RXIS_EP6   0x00000040
 
#define USB_RXIS_EP5   0x00000020
 
#define USB_RXIS_EP4   0x00000010
 
#define USB_RXIS_EP3   0x00000008
 
#define USB_RXIS_EP2   0x00000004
 
#define USB_RXIS_EP1   0x00000002
 
#define USB_TXIE_EP7   0x00000080
 
#define USB_TXIE_EP6   0x00000040
 
#define USB_TXIE_EP5   0x00000020
 
#define USB_TXIE_EP4   0x00000010
 
#define USB_TXIE_EP3   0x00000008
 
#define USB_TXIE_EP2   0x00000004
 
#define USB_TXIE_EP1   0x00000002
 
#define USB_TXIE_EP0   0x00000001
 
#define USB_RXIE_EP7   0x00000080
 
#define USB_RXIE_EP6   0x00000040
 
#define USB_RXIE_EP5   0x00000020
 
#define USB_RXIE_EP4   0x00000010
 
#define USB_RXIE_EP3   0x00000008
 
#define USB_RXIE_EP2   0x00000004
 
#define USB_RXIE_EP1   0x00000002
 
#define USB_IS_VBUSERR   0x00000080
 
#define USB_IS_SESREQ   0x00000040
 
#define USB_IS_DISCON   0x00000020
 
#define USB_IS_CONN   0x00000010
 
#define USB_IS_SOF   0x00000008
 
#define USB_IS_BABBLE   0x00000004
 
#define USB_IS_RESET   0x00000004
 
#define USB_IS_RESUME   0x00000002
 
#define USB_IS_SUSPEND   0x00000001
 
#define USB_IE_VBUSERR   0x00000080
 
#define USB_IE_SESREQ   0x00000040
 
#define USB_IE_DISCON   0x00000020
 
#define USB_IE_CONN   0x00000010
 
#define USB_IE_SOF   0x00000008
 
#define USB_IE_BABBLE   0x00000004
 
#define USB_IE_RESET   0x00000004
 
#define USB_IE_RESUME   0x00000002
 
#define USB_IE_SUSPND   0x00000001
 
#define USB_FRAME_M   0x000007FF
 
#define USB_FRAME_S   0
 
#define USB_EPIDX_EPIDX_M   0x0000000F
 
#define USB_EPIDX_EPIDX_S   0
 
#define USB_TEST_FORCEH   0x00000080
 
#define USB_TEST_FIFOACC   0x00000040
 
#define USB_TEST_FORCEFS   0x00000020
 
#define USB_FIFO0_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO0_EPDATA_S   0
 
#define USB_FIFO1_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO1_EPDATA_S   0
 
#define USB_FIFO2_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO2_EPDATA_S   0
 
#define USB_FIFO3_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO3_EPDATA_S   0
 
#define USB_FIFO4_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO4_EPDATA_S   0
 
#define USB_FIFO5_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO5_EPDATA_S   0
 
#define USB_FIFO6_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO6_EPDATA_S   0
 
#define USB_FIFO7_EPDATA_M   0xFFFFFFFF
 
#define USB_FIFO7_EPDATA_S   0
 
#define USB_DEVCTL_DEV   0x00000080
 
#define USB_DEVCTL_FSDEV   0x00000040
 
#define USB_DEVCTL_LSDEV   0x00000020
 
#define USB_DEVCTL_VBUS_M   0x00000018
 
#define USB_DEVCTL_VBUS_NONE   0x00000000
 
#define USB_DEVCTL_VBUS_SEND   0x00000008
 
#define USB_DEVCTL_VBUS_AVALID   0x00000010
 
#define USB_DEVCTL_VBUS_VALID   0x00000018
 
#define USB_DEVCTL_HOST   0x00000004
 
#define USB_DEVCTL_HOSTREQ   0x00000002
 
#define USB_DEVCTL_SESSION   0x00000001
 
#define USB_TXFIFOSZ_DPB   0x00000010
 
#define USB_TXFIFOSZ_SIZE_M   0x0000000F
 
#define USB_TXFIFOSZ_SIZE_8   0x00000000
 
#define USB_TXFIFOSZ_SIZE_16   0x00000001
 
#define USB_TXFIFOSZ_SIZE_32   0x00000002
 
#define USB_TXFIFOSZ_SIZE_64   0x00000003
 
#define USB_TXFIFOSZ_SIZE_128   0x00000004
 
#define USB_TXFIFOSZ_SIZE_256   0x00000005
 
#define USB_TXFIFOSZ_SIZE_512   0x00000006
 
#define USB_TXFIFOSZ_SIZE_1024   0x00000007
 
#define USB_TXFIFOSZ_SIZE_2048   0x00000008
 
#define USB_RXFIFOSZ_DPB   0x00000010
 
#define USB_RXFIFOSZ_SIZE_M   0x0000000F
 
#define USB_RXFIFOSZ_SIZE_8   0x00000000
 
#define USB_RXFIFOSZ_SIZE_16   0x00000001
 
#define USB_RXFIFOSZ_SIZE_32   0x00000002
 
#define USB_RXFIFOSZ_SIZE_64   0x00000003
 
#define USB_RXFIFOSZ_SIZE_128   0x00000004
 
#define USB_RXFIFOSZ_SIZE_256   0x00000005
 
#define USB_RXFIFOSZ_SIZE_512   0x00000006
 
#define USB_RXFIFOSZ_SIZE_1024   0x00000007
 
#define USB_RXFIFOSZ_SIZE_2048   0x00000008
 
#define USB_TXFIFOADD_ADDR_M   0x000001FF
 
#define USB_TXFIFOADD_ADDR_S   0
 
#define USB_RXFIFOADD_ADDR_M   0x000001FF
 
#define USB_RXFIFOADD_ADDR_S   0
 
#define USB_CONTIM_WTCON_M   0x000000F0
 
#define USB_CONTIM_WTID_M   0x0000000F
 
#define USB_CONTIM_WTCON_S   4
 
#define USB_CONTIM_WTID_S   0
 
#define USB_VPLEN_VPLEN_M   0x000000FF
 
#define USB_VPLEN_VPLEN_S   0
 
#define USB_FSEOF_FSEOFG_M   0x000000FF
 
#define USB_FSEOF_FSEOFG_S   0
 
#define USB_LSEOF_LSEOFG_M   0x000000FF
 
#define USB_LSEOF_LSEOFG_S   0
 
#define USB_TXFUNCADDR0_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR0_ADDR_S   0
 
#define USB_TXHUBADDR0_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR0_ADDR_S   0
 
#define USB_TXHUBPORT0_PORT_M   0x0000007F
 
#define USB_TXHUBPORT0_PORT_S   0
 
#define USB_TXFUNCADDR1_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR1_ADDR_S   0
 
#define USB_TXHUBADDR1_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR1_ADDR_S   0
 
#define USB_TXHUBPORT1_PORT_M   0x0000007F
 
#define USB_TXHUBPORT1_PORT_S   0
 
#define USB_RXFUNCADDR1_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR1_ADDR_S   0
 
#define USB_RXHUBADDR1_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR1_ADDR_S   0
 
#define USB_RXHUBPORT1_PORT_M   0x0000007F
 
#define USB_RXHUBPORT1_PORT_S   0
 
#define USB_TXFUNCADDR2_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR2_ADDR_S   0
 
#define USB_TXHUBADDR2_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR2_ADDR_S   0
 
#define USB_TXHUBPORT2_PORT_M   0x0000007F
 
#define USB_TXHUBPORT2_PORT_S   0
 
#define USB_RXFUNCADDR2_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR2_ADDR_S   0
 
#define USB_RXHUBADDR2_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR2_ADDR_S   0
 
#define USB_RXHUBPORT2_PORT_M   0x0000007F
 
#define USB_RXHUBPORT2_PORT_S   0
 
#define USB_TXFUNCADDR3_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR3_ADDR_S   0
 
#define USB_TXHUBADDR3_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR3_ADDR_S   0
 
#define USB_TXHUBPORT3_PORT_M   0x0000007F
 
#define USB_TXHUBPORT3_PORT_S   0
 
#define USB_RXFUNCADDR3_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR3_ADDR_S   0
 
#define USB_RXHUBADDR3_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR3_ADDR_S   0
 
#define USB_RXHUBPORT3_PORT_M   0x0000007F
 
#define USB_RXHUBPORT3_PORT_S   0
 
#define USB_TXFUNCADDR4_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR4_ADDR_S   0
 
#define USB_TXHUBADDR4_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR4_ADDR_S   0
 
#define USB_TXHUBPORT4_PORT_M   0x0000007F
 
#define USB_TXHUBPORT4_PORT_S   0
 
#define USB_RXFUNCADDR4_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR4_ADDR_S   0
 
#define USB_RXHUBADDR4_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR4_ADDR_S   0
 
#define USB_RXHUBPORT4_PORT_M   0x0000007F
 
#define USB_RXHUBPORT4_PORT_S   0
 
#define USB_TXFUNCADDR5_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR5_ADDR_S   0
 
#define USB_TXHUBADDR5_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR5_ADDR_S   0
 
#define USB_TXHUBPORT5_PORT_M   0x0000007F
 
#define USB_TXHUBPORT5_PORT_S   0
 
#define USB_RXFUNCADDR5_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR5_ADDR_S   0
 
#define USB_RXHUBADDR5_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR5_ADDR_S   0
 
#define USB_RXHUBPORT5_PORT_M   0x0000007F
 
#define USB_RXHUBPORT5_PORT_S   0
 
#define USB_TXFUNCADDR6_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR6_ADDR_S   0
 
#define USB_TXHUBADDR6_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR6_ADDR_S   0
 
#define USB_TXHUBPORT6_PORT_M   0x0000007F
 
#define USB_TXHUBPORT6_PORT_S   0
 
#define USB_RXFUNCADDR6_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR6_ADDR_S   0
 
#define USB_RXHUBADDR6_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR6_ADDR_S   0
 
#define USB_RXHUBPORT6_PORT_M   0x0000007F
 
#define USB_RXHUBPORT6_PORT_S   0
 
#define USB_TXFUNCADDR7_ADDR_M   0x0000007F
 
#define USB_TXFUNCADDR7_ADDR_S   0
 
#define USB_TXHUBADDR7_ADDR_M   0x0000007F
 
#define USB_TXHUBADDR7_ADDR_S   0
 
#define USB_TXHUBPORT7_PORT_M   0x0000007F
 
#define USB_TXHUBPORT7_PORT_S   0
 
#define USB_RXFUNCADDR7_ADDR_M   0x0000007F
 
#define USB_RXFUNCADDR7_ADDR_S   0
 
#define USB_RXHUBADDR7_ADDR_M   0x0000007F
 
#define USB_RXHUBADDR7_ADDR_S   0
 
#define USB_RXHUBPORT7_PORT_M   0x0000007F
 
#define USB_RXHUBPORT7_PORT_S   0
 
#define USB_CSRL0_NAKTO   0x00000080
 
#define USB_CSRL0_SETENDC   0x00000080
 
#define USB_CSRL0_STATUS   0x00000040
 
#define USB_CSRL0_RXRDYC   0x00000040
 
#define USB_CSRL0_REQPKT   0x00000020
 
#define USB_CSRL0_STALL   0x00000020
 
#define USB_CSRL0_SETEND   0x00000010
 
#define USB_CSRL0_ERROR   0x00000010
 
#define USB_CSRL0_DATAEND   0x00000008
 
#define USB_CSRL0_SETUP   0x00000008
 
#define USB_CSRL0_STALLED   0x00000004
 
#define USB_CSRL0_TXRDY   0x00000002
 
#define USB_CSRL0_RXRDY   0x00000001
 
#define USB_CSRH0_DTWE   0x00000004
 
#define USB_CSRH0_DT   0x00000002
 
#define USB_CSRH0_FLUSH   0x00000001
 
#define USB_COUNT0_COUNT_M   0x0000007F
 
#define USB_COUNT0_COUNT_S   0
 
#define USB_TYPE0_SPEED_M   0x000000C0
 
#define USB_TYPE0_SPEED_FULL   0x00000080
 
#define USB_TYPE0_SPEED_LOW   0x000000C0
 
#define USB_NAKLMT_NAKLMT_M   0x0000001F
 
#define USB_NAKLMT_NAKLMT_S   0
 
#define USB_TXMAXP1_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP1_MAXLOAD_S   0
 
#define USB_TXCSRL1_NAKTO   0x00000080
 
#define USB_TXCSRL1_CLRDT   0x00000040
 
#define USB_TXCSRL1_STALLED   0x00000020
 
#define USB_TXCSRL1_STALL   0x00000010
 
#define USB_TXCSRL1_SETUP   0x00000010
 
#define USB_TXCSRL1_FLUSH   0x00000008
 
#define USB_TXCSRL1_ERROR   0x00000004
 
#define USB_TXCSRL1_UNDRN   0x00000004
 
#define USB_TXCSRL1_FIFONE   0x00000002
 
#define USB_TXCSRL1_TXRDY   0x00000001
 
#define USB_TXCSRH1_AUTOSET   0x00000080
 
#define USB_TXCSRH1_ISO   0x00000040
 
#define USB_TXCSRH1_MODE   0x00000020
 
#define USB_TXCSRH1_DMAEN   0x00000010
 
#define USB_TXCSRH1_FDT   0x00000008
 
#define USB_TXCSRH1_DMAMOD   0x00000004
 
#define USB_TXCSRH1_DTWE   0x00000002
 
#define USB_TXCSRH1_DT   0x00000001
 
#define USB_RXMAXP1_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP1_MAXLOAD_S   0
 
#define USB_RXCSRL1_CLRDT   0x00000080
 
#define USB_RXCSRL1_STALLED   0x00000040
 
#define USB_RXCSRL1_STALL   0x00000020
 
#define USB_RXCSRL1_REQPKT   0x00000020
 
#define USB_RXCSRL1_FLUSH   0x00000010
 
#define USB_RXCSRL1_DATAERR   0x00000008
 
#define USB_RXCSRL1_NAKTO   0x00000008
 
#define USB_RXCSRL1_OVER   0x00000004
 
#define USB_RXCSRL1_ERROR   0x00000004
 
#define USB_RXCSRL1_FULL   0x00000002
 
#define USB_RXCSRL1_RXRDY   0x00000001
 
#define USB_RXCSRH1_AUTOCL   0x00000080
 
#define USB_RXCSRH1_AUTORQ   0x00000040
 
#define USB_RXCSRH1_ISO   0x00000040
 
#define USB_RXCSRH1_DMAEN   0x00000020
 
#define USB_RXCSRH1_DISNYET   0x00000010
 
#define USB_RXCSRH1_PIDERR   0x00000010
 
#define USB_RXCSRH1_DMAMOD   0x00000008
 
#define USB_RXCSRH1_DTWE   0x00000004
 
#define USB_RXCSRH1_DT   0x00000002
 
#define USB_RXCOUNT1_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT1_COUNT_S   0
 
#define USB_TXTYPE1_SPEED_M   0x000000C0
 
#define USB_TXTYPE1_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE1_SPEED_FULL   0x00000080
 
#define USB_TXTYPE1_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE1_PROTO_M   0x00000030
 
#define USB_TXTYPE1_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE1_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE1_PROTO_BULK   0x00000020
 
#define USB_TXTYPE1_PROTO_INT   0x00000030
 
#define USB_TXTYPE1_TEP_M   0x0000000F
 
#define USB_TXTYPE1_TEP_S   0
 
#define USB_TXINTERVAL1_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL1_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL1_TXPOLL_S    0
 
#define USB_TXINTERVAL1_NAKLMT_S    0
 
#define USB_RXTYPE1_SPEED_M   0x000000C0
 
#define USB_RXTYPE1_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE1_SPEED_FULL   0x00000080
 
#define USB_RXTYPE1_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE1_PROTO_M   0x00000030
 
#define USB_RXTYPE1_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE1_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE1_PROTO_BULK   0x00000020
 
#define USB_RXTYPE1_PROTO_INT   0x00000030
 
#define USB_RXTYPE1_TEP_M   0x0000000F
 
#define USB_RXTYPE1_TEP_S   0
 
#define USB_RXINTERVAL1_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL1_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL1_TXPOLL_S    0
 
#define USB_RXINTERVAL1_NAKLMT_S    0
 
#define USB_TXMAXP2_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP2_MAXLOAD_S   0
 
#define USB_TXCSRL2_NAKTO   0x00000080
 
#define USB_TXCSRL2_CLRDT   0x00000040
 
#define USB_TXCSRL2_STALLED   0x00000020
 
#define USB_TXCSRL2_SETUP   0x00000010
 
#define USB_TXCSRL2_STALL   0x00000010
 
#define USB_TXCSRL2_FLUSH   0x00000008
 
#define USB_TXCSRL2_ERROR   0x00000004
 
#define USB_TXCSRL2_UNDRN   0x00000004
 
#define USB_TXCSRL2_FIFONE   0x00000002
 
#define USB_TXCSRL2_TXRDY   0x00000001
 
#define USB_TXCSRH2_AUTOSET   0x00000080
 
#define USB_TXCSRH2_ISO   0x00000040
 
#define USB_TXCSRH2_MODE   0x00000020
 
#define USB_TXCSRH2_DMAEN   0x00000010
 
#define USB_TXCSRH2_FDT   0x00000008
 
#define USB_TXCSRH2_DMAMOD   0x00000004
 
#define USB_TXCSRH2_DTWE   0x00000002
 
#define USB_TXCSRH2_DT   0x00000001
 
#define USB_RXMAXP2_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP2_MAXLOAD_S   0
 
#define USB_RXCSRL2_CLRDT   0x00000080
 
#define USB_RXCSRL2_STALLED   0x00000040
 
#define USB_RXCSRL2_REQPKT   0x00000020
 
#define USB_RXCSRL2_STALL   0x00000020
 
#define USB_RXCSRL2_FLUSH   0x00000010
 
#define USB_RXCSRL2_DATAERR   0x00000008
 
#define USB_RXCSRL2_NAKTO   0x00000008
 
#define USB_RXCSRL2_ERROR   0x00000004
 
#define USB_RXCSRL2_OVER   0x00000004
 
#define USB_RXCSRL2_FULL   0x00000002
 
#define USB_RXCSRL2_RXRDY   0x00000001
 
#define USB_RXCSRH2_AUTOCL   0x00000080
 
#define USB_RXCSRH2_AUTORQ   0x00000040
 
#define USB_RXCSRH2_ISO   0x00000040
 
#define USB_RXCSRH2_DMAEN   0x00000020
 
#define USB_RXCSRH2_DISNYET   0x00000010
 
#define USB_RXCSRH2_PIDERR   0x00000010
 
#define USB_RXCSRH2_DMAMOD   0x00000008
 
#define USB_RXCSRH2_DTWE   0x00000004
 
#define USB_RXCSRH2_DT   0x00000002
 
#define USB_RXCOUNT2_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT2_COUNT_S   0
 
#define USB_TXTYPE2_SPEED_M   0x000000C0
 
#define USB_TXTYPE2_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE2_SPEED_FULL   0x00000080
 
#define USB_TXTYPE2_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE2_PROTO_M   0x00000030
 
#define USB_TXTYPE2_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE2_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE2_PROTO_BULK   0x00000020
 
#define USB_TXTYPE2_PROTO_INT   0x00000030
 
#define USB_TXTYPE2_TEP_M   0x0000000F
 
#define USB_TXTYPE2_TEP_S   0
 
#define USB_TXINTERVAL2_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL2_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL2_NAKLMT_S    0
 
#define USB_TXINTERVAL2_TXPOLL_S    0
 
#define USB_RXTYPE2_SPEED_M   0x000000C0
 
#define USB_RXTYPE2_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE2_SPEED_FULL   0x00000080
 
#define USB_RXTYPE2_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE2_PROTO_M   0x00000030
 
#define USB_RXTYPE2_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE2_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE2_PROTO_BULK   0x00000020
 
#define USB_RXTYPE2_PROTO_INT   0x00000030
 
#define USB_RXTYPE2_TEP_M   0x0000000F
 
#define USB_RXTYPE2_TEP_S   0
 
#define USB_RXINTERVAL2_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL2_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL2_TXPOLL_S    0
 
#define USB_RXINTERVAL2_NAKLMT_S    0
 
#define USB_TXMAXP3_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP3_MAXLOAD_S   0
 
#define USB_TXCSRL3_NAKTO   0x00000080
 
#define USB_TXCSRL3_CLRDT   0x00000040
 
#define USB_TXCSRL3_STALLED   0x00000020
 
#define USB_TXCSRL3_SETUP   0x00000010
 
#define USB_TXCSRL3_STALL   0x00000010
 
#define USB_TXCSRL3_FLUSH   0x00000008
 
#define USB_TXCSRL3_ERROR   0x00000004
 
#define USB_TXCSRL3_UNDRN   0x00000004
 
#define USB_TXCSRL3_FIFONE   0x00000002
 
#define USB_TXCSRL3_TXRDY   0x00000001
 
#define USB_TXCSRH3_AUTOSET   0x00000080
 
#define USB_TXCSRH3_ISO   0x00000040
 
#define USB_TXCSRH3_MODE   0x00000020
 
#define USB_TXCSRH3_DMAEN   0x00000010
 
#define USB_TXCSRH3_FDT   0x00000008
 
#define USB_TXCSRH3_DMAMOD   0x00000004
 
#define USB_TXCSRH3_DTWE   0x00000002
 
#define USB_TXCSRH3_DT   0x00000001
 
#define USB_RXMAXP3_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP3_MAXLOAD_S   0
 
#define USB_RXCSRL3_CLRDT   0x00000080
 
#define USB_RXCSRL3_STALLED   0x00000040
 
#define USB_RXCSRL3_STALL   0x00000020
 
#define USB_RXCSRL3_REQPKT   0x00000020
 
#define USB_RXCSRL3_FLUSH   0x00000010
 
#define USB_RXCSRL3_DATAERR   0x00000008
 
#define USB_RXCSRL3_NAKTO   0x00000008
 
#define USB_RXCSRL3_ERROR   0x00000004
 
#define USB_RXCSRL3_OVER   0x00000004
 
#define USB_RXCSRL3_FULL   0x00000002
 
#define USB_RXCSRL3_RXRDY   0x00000001
 
#define USB_RXCSRH3_AUTOCL   0x00000080
 
#define USB_RXCSRH3_AUTORQ   0x00000040
 
#define USB_RXCSRH3_ISO   0x00000040
 
#define USB_RXCSRH3_DMAEN   0x00000020
 
#define USB_RXCSRH3_DISNYET   0x00000010
 
#define USB_RXCSRH3_PIDERR   0x00000010
 
#define USB_RXCSRH3_DMAMOD   0x00000008
 
#define USB_RXCSRH3_DTWE   0x00000004
 
#define USB_RXCSRH3_DT   0x00000002
 
#define USB_RXCOUNT3_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT3_COUNT_S   0
 
#define USB_TXTYPE3_SPEED_M   0x000000C0
 
#define USB_TXTYPE3_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE3_SPEED_FULL   0x00000080
 
#define USB_TXTYPE3_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE3_PROTO_M   0x00000030
 
#define USB_TXTYPE3_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE3_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE3_PROTO_BULK   0x00000020
 
#define USB_TXTYPE3_PROTO_INT   0x00000030
 
#define USB_TXTYPE3_TEP_M   0x0000000F
 
#define USB_TXTYPE3_TEP_S   0
 
#define USB_TXINTERVAL3_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL3_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL3_TXPOLL_S    0
 
#define USB_TXINTERVAL3_NAKLMT_S    0
 
#define USB_RXTYPE3_SPEED_M   0x000000C0
 
#define USB_RXTYPE3_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE3_SPEED_FULL   0x00000080
 
#define USB_RXTYPE3_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE3_PROTO_M   0x00000030
 
#define USB_RXTYPE3_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE3_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE3_PROTO_BULK   0x00000020
 
#define USB_RXTYPE3_PROTO_INT   0x00000030
 
#define USB_RXTYPE3_TEP_M   0x0000000F
 
#define USB_RXTYPE3_TEP_S   0
 
#define USB_RXINTERVAL3_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL3_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL3_TXPOLL_S    0
 
#define USB_RXINTERVAL3_NAKLMT_S    0
 
#define USB_TXMAXP4_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP4_MAXLOAD_S   0
 
#define USB_TXCSRL4_NAKTO   0x00000080
 
#define USB_TXCSRL4_CLRDT   0x00000040
 
#define USB_TXCSRL4_STALLED   0x00000020
 
#define USB_TXCSRL4_SETUP   0x00000010
 
#define USB_TXCSRL4_STALL   0x00000010
 
#define USB_TXCSRL4_FLUSH   0x00000008
 
#define USB_TXCSRL4_ERROR   0x00000004
 
#define USB_TXCSRL4_UNDRN   0x00000004
 
#define USB_TXCSRL4_FIFONE   0x00000002
 
#define USB_TXCSRL4_TXRDY   0x00000001
 
#define USB_TXCSRH4_AUTOSET   0x00000080
 
#define USB_TXCSRH4_ISO   0x00000040
 
#define USB_TXCSRH4_MODE   0x00000020
 
#define USB_TXCSRH4_DMAEN   0x00000010
 
#define USB_TXCSRH4_FDT   0x00000008
 
#define USB_TXCSRH4_DMAMOD   0x00000004
 
#define USB_TXCSRH4_DTWE   0x00000002
 
#define USB_TXCSRH4_DT   0x00000001
 
#define USB_RXMAXP4_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP4_MAXLOAD_S   0
 
#define USB_RXCSRL4_CLRDT   0x00000080
 
#define USB_RXCSRL4_STALLED   0x00000040
 
#define USB_RXCSRL4_STALL   0x00000020
 
#define USB_RXCSRL4_REQPKT   0x00000020
 
#define USB_RXCSRL4_FLUSH   0x00000010
 
#define USB_RXCSRL4_NAKTO   0x00000008
 
#define USB_RXCSRL4_DATAERR   0x00000008
 
#define USB_RXCSRL4_OVER   0x00000004
 
#define USB_RXCSRL4_ERROR   0x00000004
 
#define USB_RXCSRL4_FULL   0x00000002
 
#define USB_RXCSRL4_RXRDY   0x00000001
 
#define USB_RXCSRH4_AUTOCL   0x00000080
 
#define USB_RXCSRH4_AUTORQ   0x00000040
 
#define USB_RXCSRH4_ISO   0x00000040
 
#define USB_RXCSRH4_DMAEN   0x00000020
 
#define USB_RXCSRH4_DISNYET   0x00000010
 
#define USB_RXCSRH4_PIDERR   0x00000010
 
#define USB_RXCSRH4_DMAMOD   0x00000008
 
#define USB_RXCSRH4_DTWE   0x00000004
 
#define USB_RXCSRH4_DT   0x00000002
 
#define USB_RXCOUNT4_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT4_COUNT_S   0
 
#define USB_TXTYPE4_SPEED_M   0x000000C0
 
#define USB_TXTYPE4_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE4_SPEED_FULL   0x00000080
 
#define USB_TXTYPE4_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE4_PROTO_M   0x00000030
 
#define USB_TXTYPE4_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE4_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE4_PROTO_BULK   0x00000020
 
#define USB_TXTYPE4_PROTO_INT   0x00000030
 
#define USB_TXTYPE4_TEP_M   0x0000000F
 
#define USB_TXTYPE4_TEP_S   0
 
#define USB_TXINTERVAL4_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL4_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL4_NAKLMT_S    0
 
#define USB_TXINTERVAL4_TXPOLL_S    0
 
#define USB_RXTYPE4_SPEED_M   0x000000C0
 
#define USB_RXTYPE4_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE4_SPEED_FULL   0x00000080
 
#define USB_RXTYPE4_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE4_PROTO_M   0x00000030
 
#define USB_RXTYPE4_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE4_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE4_PROTO_BULK   0x00000020
 
#define USB_RXTYPE4_PROTO_INT   0x00000030
 
#define USB_RXTYPE4_TEP_M   0x0000000F
 
#define USB_RXTYPE4_TEP_S   0
 
#define USB_RXINTERVAL4_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL4_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL4_NAKLMT_S    0
 
#define USB_RXINTERVAL4_TXPOLL_S    0
 
#define USB_TXMAXP5_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP5_MAXLOAD_S   0
 
#define USB_TXCSRL5_NAKTO   0x00000080
 
#define USB_TXCSRL5_CLRDT   0x00000040
 
#define USB_TXCSRL5_STALLED   0x00000020
 
#define USB_TXCSRL5_SETUP   0x00000010
 
#define USB_TXCSRL5_STALL   0x00000010
 
#define USB_TXCSRL5_FLUSH   0x00000008
 
#define USB_TXCSRL5_ERROR   0x00000004
 
#define USB_TXCSRL5_UNDRN   0x00000004
 
#define USB_TXCSRL5_FIFONE   0x00000002
 
#define USB_TXCSRL5_TXRDY   0x00000001
 
#define USB_TXCSRH5_AUTOSET   0x00000080
 
#define USB_TXCSRH5_ISO   0x00000040
 
#define USB_TXCSRH5_MODE   0x00000020
 
#define USB_TXCSRH5_DMAEN   0x00000010
 
#define USB_TXCSRH5_FDT   0x00000008
 
#define USB_TXCSRH5_DMAMOD   0x00000004
 
#define USB_TXCSRH5_DTWE   0x00000002
 
#define USB_TXCSRH5_DT   0x00000001
 
#define USB_RXMAXP5_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP5_MAXLOAD_S   0
 
#define USB_RXCSRL5_CLRDT   0x00000080
 
#define USB_RXCSRL5_STALLED   0x00000040
 
#define USB_RXCSRL5_STALL   0x00000020
 
#define USB_RXCSRL5_REQPKT   0x00000020
 
#define USB_RXCSRL5_FLUSH   0x00000010
 
#define USB_RXCSRL5_NAKTO   0x00000008
 
#define USB_RXCSRL5_DATAERR   0x00000008
 
#define USB_RXCSRL5_ERROR   0x00000004
 
#define USB_RXCSRL5_OVER   0x00000004
 
#define USB_RXCSRL5_FULL   0x00000002
 
#define USB_RXCSRL5_RXRDY   0x00000001
 
#define USB_RXCSRH5_AUTOCL   0x00000080
 
#define USB_RXCSRH5_AUTORQ   0x00000040
 
#define USB_RXCSRH5_ISO   0x00000040
 
#define USB_RXCSRH5_DMAEN   0x00000020
 
#define USB_RXCSRH5_DISNYET   0x00000010
 
#define USB_RXCSRH5_PIDERR   0x00000010
 
#define USB_RXCSRH5_DMAMOD   0x00000008
 
#define USB_RXCSRH5_DTWE   0x00000004
 
#define USB_RXCSRH5_DT   0x00000002
 
#define USB_RXCOUNT5_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT5_COUNT_S   0
 
#define USB_TXTYPE5_SPEED_M   0x000000C0
 
#define USB_TXTYPE5_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE5_SPEED_FULL   0x00000080
 
#define USB_TXTYPE5_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE5_PROTO_M   0x00000030
 
#define USB_TXTYPE5_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE5_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE5_PROTO_BULK   0x00000020
 
#define USB_TXTYPE5_PROTO_INT   0x00000030
 
#define USB_TXTYPE5_TEP_M   0x0000000F
 
#define USB_TXTYPE5_TEP_S   0
 
#define USB_TXINTERVAL5_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL5_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL5_NAKLMT_S    0
 
#define USB_TXINTERVAL5_TXPOLL_S    0
 
#define USB_RXTYPE5_SPEED_M   0x000000C0
 
#define USB_RXTYPE5_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE5_SPEED_FULL   0x00000080
 
#define USB_RXTYPE5_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE5_PROTO_M   0x00000030
 
#define USB_RXTYPE5_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE5_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE5_PROTO_BULK   0x00000020
 
#define USB_RXTYPE5_PROTO_INT   0x00000030
 
#define USB_RXTYPE5_TEP_M   0x0000000F
 
#define USB_RXTYPE5_TEP_S   0
 
#define USB_RXINTERVAL5_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL5_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL5_TXPOLL_S    0
 
#define USB_RXINTERVAL5_NAKLMT_S    0
 
#define USB_TXMAXP6_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP6_MAXLOAD_S   0
 
#define USB_TXCSRL6_NAKTO   0x00000080
 
#define USB_TXCSRL6_CLRDT   0x00000040
 
#define USB_TXCSRL6_STALLED   0x00000020
 
#define USB_TXCSRL6_STALL   0x00000010
 
#define USB_TXCSRL6_SETUP   0x00000010
 
#define USB_TXCSRL6_FLUSH   0x00000008
 
#define USB_TXCSRL6_ERROR   0x00000004
 
#define USB_TXCSRL6_UNDRN   0x00000004
 
#define USB_TXCSRL6_FIFONE   0x00000002
 
#define USB_TXCSRL6_TXRDY   0x00000001
 
#define USB_TXCSRH6_AUTOSET   0x00000080
 
#define USB_TXCSRH6_ISO   0x00000040
 
#define USB_TXCSRH6_MODE   0x00000020
 
#define USB_TXCSRH6_DMAEN   0x00000010
 
#define USB_TXCSRH6_FDT   0x00000008
 
#define USB_TXCSRH6_DMAMOD   0x00000004
 
#define USB_TXCSRH6_DTWE   0x00000002
 
#define USB_TXCSRH6_DT   0x00000001
 
#define USB_RXMAXP6_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP6_MAXLOAD_S   0
 
#define USB_RXCSRL6_CLRDT   0x00000080
 
#define USB_RXCSRL6_STALLED   0x00000040
 
#define USB_RXCSRL6_REQPKT   0x00000020
 
#define USB_RXCSRL6_STALL   0x00000020
 
#define USB_RXCSRL6_FLUSH   0x00000010
 
#define USB_RXCSRL6_NAKTO   0x00000008
 
#define USB_RXCSRL6_DATAERR   0x00000008
 
#define USB_RXCSRL6_ERROR   0x00000004
 
#define USB_RXCSRL6_OVER   0x00000004
 
#define USB_RXCSRL6_FULL   0x00000002
 
#define USB_RXCSRL6_RXRDY   0x00000001
 
#define USB_RXCSRH6_AUTOCL   0x00000080
 
#define USB_RXCSRH6_AUTORQ   0x00000040
 
#define USB_RXCSRH6_ISO   0x00000040
 
#define USB_RXCSRH6_DMAEN   0x00000020
 
#define USB_RXCSRH6_DISNYET   0x00000010
 
#define USB_RXCSRH6_PIDERR   0x00000010
 
#define USB_RXCSRH6_DMAMOD   0x00000008
 
#define USB_RXCSRH6_DTWE   0x00000004
 
#define USB_RXCSRH6_DT   0x00000002
 
#define USB_RXCOUNT6_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT6_COUNT_S   0
 
#define USB_TXTYPE6_SPEED_M   0x000000C0
 
#define USB_TXTYPE6_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE6_SPEED_FULL   0x00000080
 
#define USB_TXTYPE6_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE6_PROTO_M   0x00000030
 
#define USB_TXTYPE6_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE6_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE6_PROTO_BULK   0x00000020
 
#define USB_TXTYPE6_PROTO_INT   0x00000030
 
#define USB_TXTYPE6_TEP_M   0x0000000F
 
#define USB_TXTYPE6_TEP_S   0
 
#define USB_TXINTERVAL6_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL6_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL6_TXPOLL_S    0
 
#define USB_TXINTERVAL6_NAKLMT_S    0
 
#define USB_RXTYPE6_SPEED_M   0x000000C0
 
#define USB_RXTYPE6_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE6_SPEED_FULL   0x00000080
 
#define USB_RXTYPE6_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE6_PROTO_M   0x00000030
 
#define USB_RXTYPE6_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE6_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE6_PROTO_BULK   0x00000020
 
#define USB_RXTYPE6_PROTO_INT   0x00000030
 
#define USB_RXTYPE6_TEP_M   0x0000000F
 
#define USB_RXTYPE6_TEP_S   0
 
#define USB_RXINTERVAL6_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL6_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL6_NAKLMT_S    0
 
#define USB_RXINTERVAL6_TXPOLL_S    0
 
#define USB_TXMAXP7_MAXLOAD_M   0x000007FF
 
#define USB_TXMAXP7_MAXLOAD_S   0
 
#define USB_TXCSRL7_NAKTO   0x00000080
 
#define USB_TXCSRL7_CLRDT   0x00000040
 
#define USB_TXCSRL7_STALLED   0x00000020
 
#define USB_TXCSRL7_STALL   0x00000010
 
#define USB_TXCSRL7_SETUP   0x00000010
 
#define USB_TXCSRL7_FLUSH   0x00000008
 
#define USB_TXCSRL7_ERROR   0x00000004
 
#define USB_TXCSRL7_UNDRN   0x00000004
 
#define USB_TXCSRL7_FIFONE   0x00000002
 
#define USB_TXCSRL7_TXRDY   0x00000001
 
#define USB_TXCSRH7_AUTOSET   0x00000080
 
#define USB_TXCSRH7_ISO   0x00000040
 
#define USB_TXCSRH7_MODE   0x00000020
 
#define USB_TXCSRH7_DMAEN   0x00000010
 
#define USB_TXCSRH7_FDT   0x00000008
 
#define USB_TXCSRH7_DMAMOD   0x00000004
 
#define USB_TXCSRH7_DTWE   0x00000002
 
#define USB_TXCSRH7_DT   0x00000001
 
#define USB_RXMAXP7_MAXLOAD_M   0x000007FF
 
#define USB_RXMAXP7_MAXLOAD_S   0
 
#define USB_RXCSRL7_CLRDT   0x00000080
 
#define USB_RXCSRL7_STALLED   0x00000040
 
#define USB_RXCSRL7_REQPKT   0x00000020
 
#define USB_RXCSRL7_STALL   0x00000020
 
#define USB_RXCSRL7_FLUSH   0x00000010
 
#define USB_RXCSRL7_DATAERR   0x00000008
 
#define USB_RXCSRL7_NAKTO   0x00000008
 
#define USB_RXCSRL7_ERROR   0x00000004
 
#define USB_RXCSRL7_OVER   0x00000004
 
#define USB_RXCSRL7_FULL   0x00000002
 
#define USB_RXCSRL7_RXRDY   0x00000001
 
#define USB_RXCSRH7_AUTOCL   0x00000080
 
#define USB_RXCSRH7_ISO   0x00000040
 
#define USB_RXCSRH7_AUTORQ   0x00000040
 
#define USB_RXCSRH7_DMAEN   0x00000020
 
#define USB_RXCSRH7_PIDERR   0x00000010
 
#define USB_RXCSRH7_DISNYET   0x00000010
 
#define USB_RXCSRH7_DMAMOD   0x00000008
 
#define USB_RXCSRH7_DTWE   0x00000004
 
#define USB_RXCSRH7_DT   0x00000002
 
#define USB_RXCOUNT7_COUNT_M   0x00001FFF
 
#define USB_RXCOUNT7_COUNT_S   0
 
#define USB_TXTYPE7_SPEED_M   0x000000C0
 
#define USB_TXTYPE7_SPEED_DFLT   0x00000000
 
#define USB_TXTYPE7_SPEED_FULL   0x00000080
 
#define USB_TXTYPE7_SPEED_LOW   0x000000C0
 
#define USB_TXTYPE7_PROTO_M   0x00000030
 
#define USB_TXTYPE7_PROTO_CTRL   0x00000000
 
#define USB_TXTYPE7_PROTO_ISOC   0x00000010
 
#define USB_TXTYPE7_PROTO_BULK   0x00000020
 
#define USB_TXTYPE7_PROTO_INT   0x00000030
 
#define USB_TXTYPE7_TEP_M   0x0000000F
 
#define USB_TXTYPE7_TEP_S   0
 
#define USB_TXINTERVAL7_TXPOLL_M    0x000000FF
 
#define USB_TXINTERVAL7_NAKLMT_M    0x000000FF
 
#define USB_TXINTERVAL7_NAKLMT_S    0
 
#define USB_TXINTERVAL7_TXPOLL_S    0
 
#define USB_RXTYPE7_SPEED_M   0x000000C0
 
#define USB_RXTYPE7_SPEED_DFLT   0x00000000
 
#define USB_RXTYPE7_SPEED_FULL   0x00000080
 
#define USB_RXTYPE7_SPEED_LOW   0x000000C0
 
#define USB_RXTYPE7_PROTO_M   0x00000030
 
#define USB_RXTYPE7_PROTO_CTRL   0x00000000
 
#define USB_RXTYPE7_PROTO_ISOC   0x00000010
 
#define USB_RXTYPE7_PROTO_BULK   0x00000020
 
#define USB_RXTYPE7_PROTO_INT   0x00000030
 
#define USB_RXTYPE7_TEP_M   0x0000000F
 
#define USB_RXTYPE7_TEP_S   0
 
#define USB_RXINTERVAL7_TXPOLL_M    0x000000FF
 
#define USB_RXINTERVAL7_NAKLMT_M    0x000000FF
 
#define USB_RXINTERVAL7_NAKLMT_S    0
 
#define USB_RXINTERVAL7_TXPOLL_S    0
 
#define USB_RQPKTCOUNT1_M   0x0000FFFF
 
#define USB_RQPKTCOUNT1_S   0
 
#define USB_RQPKTCOUNT2_M   0x0000FFFF
 
#define USB_RQPKTCOUNT2_S   0
 
#define USB_RQPKTCOUNT3_M   0x0000FFFF
 
#define USB_RQPKTCOUNT3_S   0
 
#define USB_RQPKTCOUNT4_COUNT_M   0x0000FFFF
 
#define USB_RQPKTCOUNT4_COUNT_S   0
 
#define USB_RQPKTCOUNT5_COUNT_M   0x0000FFFF
 
#define USB_RQPKTCOUNT5_COUNT_S   0
 
#define USB_RQPKTCOUNT6_COUNT_M   0x0000FFFF
 
#define USB_RQPKTCOUNT6_COUNT_S   0
 
#define USB_RQPKTCOUNT7_COUNT_M   0x0000FFFF
 
#define USB_RQPKTCOUNT7_COUNT_S   0
 
#define USB_RXDPKTBUFDIS_EP7   0x00000080
 
#define USB_RXDPKTBUFDIS_EP6   0x00000040
 
#define USB_RXDPKTBUFDIS_EP5   0x00000020
 
#define USB_RXDPKTBUFDIS_EP4   0x00000010
 
#define USB_RXDPKTBUFDIS_EP3   0x00000008
 
#define USB_RXDPKTBUFDIS_EP2   0x00000004
 
#define USB_RXDPKTBUFDIS_EP1   0x00000002
 
#define USB_TXDPKTBUFDIS_EP7   0x00000080
 
#define USB_TXDPKTBUFDIS_EP6   0x00000040
 
#define USB_TXDPKTBUFDIS_EP5   0x00000020
 
#define USB_TXDPKTBUFDIS_EP4   0x00000010
 
#define USB_TXDPKTBUFDIS_EP3   0x00000008
 
#define USB_TXDPKTBUFDIS_EP2   0x00000004
 
#define USB_TXDPKTBUFDIS_EP1   0x00000002
 
#define USB_EPC_PFLTACT_M   0x00000300
 
#define USB_EPC_PFLTACT_UNCHG   0x00000000
 
#define USB_EPC_PFLTACT_TRIS   0x00000100
 
#define USB_EPC_PFLTACT_LOW   0x00000200
 
#define USB_EPC_PFLTACT_HIGH   0x00000300
 
#define USB_EPC_PFLTAEN   0x00000040
 
#define USB_EPC_PFLTSEN_HIGH   0x00000020
 
#define USB_EPC_PFLTEN   0x00000010
 
#define USB_EPC_EPENDE   0x00000004
 
#define USB_EPC_EPEN_M   0x00000003
 
#define USB_EPC_EPEN_LOW   0x00000000
 
#define USB_EPC_EPEN_HIGH   0x00000001
 
#define USB_EPC_EPEN_VBLOW   0x00000002
 
#define USB_EPC_EPEN_VBHIGH   0x00000003
 
#define USB_EPCRIS_PF   0x00000001
 
#define USB_EPCIM_PF   0x00000001
 
#define USB_EPCISC_PF   0x00000001
 
#define USB_DRRIS_RESUME   0x00000001
 
#define USB_DRIM_RESUME   0x00000001
 
#define USB_DRISC_RESUME   0x00000001
 
#define USB_GPCS_DEVMODOTG   0x00000002
 
#define USB_GPCS_DEVMOD   0x00000001
 
#define USB_VDC_VBDEN   0x00000001
 
#define USB_VDCRIS_VD   0x00000001
 
#define USB_VDCIM_VD   0x00000001
 
#define USB_VDCISC_VD   0x00000001
 
#define USB_IDVRIS_ID   0x00000001
 
#define USB_IDVIM_ID   0x00000001
 
#define USB_IDVISC_ID   0x00000001
 
#define USB_DMASEL_DMACTX_M   0x00F00000
 
#define USB_DMASEL_DMACRX_M   0x000F0000
 
#define USB_DMASEL_DMABTX_M   0x0000F000
 
#define USB_DMASEL_DMABRX_M   0x00000F00
 
#define USB_DMASEL_DMAATX_M   0x000000F0
 
#define USB_DMASEL_DMAARX_M   0x0000000F
 
#define USB_DMASEL_DMACTX_S   20
 
#define USB_DMASEL_DMACRX_S   16
 
#define USB_DMASEL_DMABTX_S   12
 
#define USB_DMASEL_DMABRX_S   8
 
#define USB_DMASEL_DMAATX_S   4
 
#define USB_DMASEL_DMAARX_S   0
 
#define USB_PP_ECNT_M   0x0000FF00
 
#define USB_PP_USB_M   0x000000C0
 
#define USB_PP_USB_DEVICE   0x00000040
 
#define USB_PP_USB_HOSTDEVICE   0x00000080
 
#define USB_PP_USB_OTG   0x000000C0
 
#define USB_PP_PHY   0x00000010
 
#define USB_PP_TYPE_M   0x0000000F
 
#define USB_PP_TYPE_0   0x00000000
 
#define USB_PP_ECNT_S   8
 
#define EEPROM_EESIZE_BLKCNT_M   0x07FF0000
 
#define EEPROM_EESIZE_WORDCNT_M   0x0000FFFF
 
#define EEPROM_EESIZE_BLKCNT_S   16
 
#define EEPROM_EESIZE_WORDCNT_S   0
 
#define EEPROM_EEBLOCK_BLOCK_M   0x0000FFFF
 
#define EEPROM_EEBLOCK_BLOCK_S   0
 
#define EEPROM_EEOFFSET_OFFSET_M    0x0000000F
 
#define EEPROM_EEOFFSET_OFFSET_S    0
 
#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF
 
#define EEPROM_EERDWR_VALUE_S   0
 
#define EEPROM_EERDWRINC_VALUE_M    0xFFFFFFFF
 
#define EEPROM_EERDWRINC_VALUE_S    0
 
#define EEPROM_EEDONE_WRBUSY   0x00000020
 
#define EEPROM_EEDONE_NOPERM   0x00000010
 
#define EEPROM_EEDONE_WKCOPY   0x00000008
 
#define EEPROM_EEDONE_WKERASE   0x00000004
 
#define EEPROM_EEDONE_WORKING   0x00000001
 
#define EEPROM_EESUPP_PRETRY   0x00000008
 
#define EEPROM_EESUPP_ERETRY   0x00000004
 
#define EEPROM_EEUNLOCK_UNLOCK_M    0xFFFFFFFF
 
#define EEPROM_EEPROT_ACC   0x00000008
 
#define EEPROM_EEPROT_PROT_M   0x00000007
 
#define EEPROM_EEPROT_PROT_RWNPW    0x00000000
 
#define EEPROM_EEPROT_PROT_RWPW   0x00000001
 
#define EEPROM_EEPROT_PROT_RONPW    0x00000002
 
#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF
 
#define EEPROM_EEPASS0_PASS_S   0
 
#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF
 
#define EEPROM_EEPASS1_PASS_S   0
 
#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF
 
#define EEPROM_EEPASS2_PASS_S   0
 
#define EEPROM_EEINT_INT   0x00000001
 
#define EEPROM_EEHIDE_HN_M   0xFFFFFFFE
 
#define EEPROM_EEDBGME_KEY_M   0xFFFF0000
 
#define EEPROM_EEDBGME_ME   0x00000001
 
#define EEPROM_EEDBGME_KEY_S   16
 
#define EEPROM_PP_SIZE_M   0x0000001F
 
#define EEPROM_PP_SIZE_S   0
 
#define SYSEXC_RIS_FPIXCRIS   0x00000020
 
#define SYSEXC_RIS_FPOFCRIS   0x00000010
 
#define SYSEXC_RIS_FPUFCRIS   0x00000008
 
#define SYSEXC_RIS_FPIOCRIS   0x00000004
 
#define SYSEXC_RIS_FPDZCRIS   0x00000002
 
#define SYSEXC_RIS_FPIDCRIS   0x00000001
 
#define SYSEXC_IM_FPIXCIM   0x00000020
 
#define SYSEXC_IM_FPOFCIM   0x00000010
 
#define SYSEXC_IM_FPUFCIM   0x00000008
 
#define SYSEXC_IM_FPIOCIM   0x00000004
 
#define SYSEXC_IM_FPDZCIM   0x00000002
 
#define SYSEXC_IM_FPIDCIM   0x00000001
 
#define SYSEXC_MIS_FPIXCMIS   0x00000020
 
#define SYSEXC_MIS_FPOFCMIS   0x00000010
 
#define SYSEXC_MIS_FPUFCMIS   0x00000008
 
#define SYSEXC_MIS_FPIOCMIS   0x00000004
 
#define SYSEXC_MIS_FPDZCMIS   0x00000002
 
#define SYSEXC_MIS_FPIDCMIS   0x00000001
 
#define SYSEXC_IC_FPIXCIC   0x00000020
 
#define SYSEXC_IC_FPOFCIC   0x00000010
 
#define SYSEXC_IC_FPUFCIC   0x00000008
 
#define SYSEXC_IC_FPIOCIC   0x00000004
 
#define SYSEXC_IC_FPDZCIC   0x00000002
 
#define SYSEXC_IC_FPIDCIC   0x00000001
 
#define HIB_RTCC_M   0xFFFFFFFF
 
#define HIB_RTCC_S   0
 
#define HIB_RTCM0_M   0xFFFFFFFF
 
#define HIB_RTCM0_S   0
 
#define HIB_RTCLD_M   0xFFFFFFFF
 
#define HIB_RTCLD_S   0
 
#define HIB_CTL_WRC   0x80000000
 
#define HIB_CTL_OSCDRV   0x00020000
 
#define HIB_CTL_OSCBYP   0x00010000
 
#define HIB_CTL_VBATSEL_M   0x00006000
 
#define HIB_CTL_VBATSEL_1_9V   0x00000000
 
#define HIB_CTL_VBATSEL_2_1V   0x00002000
 
#define HIB_CTL_VBATSEL_2_3V   0x00004000
 
#define HIB_CTL_VBATSEL_2_5V   0x00006000
 
#define HIB_CTL_BATCHK   0x00000400
 
#define HIB_CTL_BATWKEN   0x00000200
 
#define HIB_CTL_VDD3ON   0x00000100
 
#define HIB_CTL_VABORT   0x00000080
 
#define HIB_CTL_CLK32EN   0x00000040
 
#define HIB_CTL_PINWEN   0x00000010
 
#define HIB_CTL_RTCWEN   0x00000008
 
#define HIB_CTL_HIBREQ   0x00000002
 
#define HIB_CTL_RTCEN   0x00000001
 
#define HIB_IM_WC   0x00000010
 
#define HIB_IM_EXTW   0x00000008
 
#define HIB_IM_LOWBAT   0x00000004
 
#define HIB_IM_RTCALT0   0x00000001
 
#define HIB_RIS_WC   0x00000010
 
#define HIB_RIS_EXTW   0x00000008
 
#define HIB_RIS_LOWBAT   0x00000004
 
#define HIB_RIS_RTCALT0   0x00000001
 
#define HIB_MIS_WC   0x00000010
 
#define HIB_MIS_EXTW   0x00000008
 
#define HIB_MIS_LOWBAT   0x00000004
 
#define HIB_MIS_RTCALT0   0x00000001
 
#define HIB_IC_WC   0x00000010
 
#define HIB_IC_EXTW   0x00000008
 
#define HIB_IC_LOWBAT   0x00000004
 
#define HIB_IC_RTCALT0   0x00000001
 
#define HIB_RTCT_TRIM_M   0x0000FFFF
 
#define HIB_RTCT_TRIM_S   0
 
#define HIB_RTCSS_RTCSSM_M   0x7FFF0000
 
#define HIB_RTCSS_RTCSSC_M   0x00007FFF
 
#define HIB_RTCSS_RTCSSM_S   16
 
#define HIB_RTCSS_RTCSSC_S   0
 
#define HIB_DATA_RTD_M   0xFFFFFFFF
 
#define HIB_DATA_RTD_S   0
 
#define FLASH_FMA_OFFSET_M   0x0003FFFF
 
#define FLASH_FMA_OFFSET_S   0
 
#define FLASH_FMD_DATA_M   0xFFFFFFFF
 
#define FLASH_FMD_DATA_S   0
 
#define FLASH_FMC_WRKEY   0xA4420000
 
#define FLASH_FMC_COMT   0x00000008
 
#define FLASH_FMC_MERASE   0x00000004
 
#define FLASH_FMC_ERASE   0x00000002
 
#define FLASH_FMC_WRITE   0x00000001
 
#define FLASH_FCRIS_PROGRIS   0x00002000
 
#define FLASH_FCRIS_ERRIS   0x00000800
 
#define FLASH_FCRIS_INVDRIS   0x00000400
 
#define FLASH_FCRIS_VOLTRIS   0x00000200
 
#define FLASH_FCRIS_ERIS   0x00000004
 
#define FLASH_FCRIS_PRIS   0x00000002
 
#define FLASH_FCRIS_ARIS   0x00000001
 
#define FLASH_FCIM_PROGMASK   0x00002000
 
#define FLASH_FCIM_ERMASK   0x00000800
 
#define FLASH_FCIM_INVDMASK   0x00000400
 
#define FLASH_FCIM_VOLTMASK   0x00000200
 
#define FLASH_FCIM_EMASK   0x00000004
 
#define FLASH_FCIM_PMASK   0x00000002
 
#define FLASH_FCIM_AMASK   0x00000001
 
#define FLASH_FCMISC_PROGMISC   0x00002000
 
#define FLASH_FCMISC_ERMISC   0x00000800
 
#define FLASH_FCMISC_INVDMISC   0x00000400
 
#define FLASH_FCMISC_VOLTMISC   0x00000200
 
#define FLASH_FCMISC_EMISC   0x00000004
 
#define FLASH_FCMISC_PMISC   0x00000002
 
#define FLASH_FCMISC_AMISC   0x00000001
 
#define FLASH_FMC2_WRBUF   0x00000001
 
#define FLASH_FWBVAL_FWB_M   0xFFFFFFFF
 
#define FLASH_FWBN_DATA_M   0xFFFFFFFF
 
#define FLASH_FSIZE_SIZE_M   0x0000FFFF
 
#define FLASH_FSIZE_SIZE_256KB   0x0000007F
 
#define FLASH_SSIZE_SIZE_M   0x0000FFFF
 
#define FLASH_SSIZE_SIZE_32KB   0x0000007F
 
#define FLASH_ROMSWMAP_SAFERTOS   0x00000001
 
#define FLASH_RMCTL_BA   0x00000001
 
#define FLASH_BOOTCFG_NW   0x80000000
 
#define FLASH_BOOTCFG_PORT_M   0x0000E000
 
#define FLASH_BOOTCFG_PORT_A   0x00000000
 
#define FLASH_BOOTCFG_PORT_B   0x00002000
 
#define FLASH_BOOTCFG_PORT_C   0x00004000
 
#define FLASH_BOOTCFG_PORT_D   0x00006000
 
#define FLASH_BOOTCFG_PORT_E   0x00008000
 
#define FLASH_BOOTCFG_PORT_F   0x0000A000
 
#define FLASH_BOOTCFG_PORT_G   0x0000C000
 
#define FLASH_BOOTCFG_PORT_H   0x0000E000
 
#define FLASH_BOOTCFG_PIN_M   0x00001C00
 
#define FLASH_BOOTCFG_PIN_0   0x00000000
 
#define FLASH_BOOTCFG_PIN_1   0x00000400
 
#define FLASH_BOOTCFG_PIN_2   0x00000800
 
#define FLASH_BOOTCFG_PIN_3   0x00000C00
 
#define FLASH_BOOTCFG_PIN_4   0x00001000
 
#define FLASH_BOOTCFG_PIN_5   0x00001400
 
#define FLASH_BOOTCFG_PIN_6   0x00001800
 
#define FLASH_BOOTCFG_PIN_7   0x00001C00
 
#define FLASH_BOOTCFG_POL   0x00000200
 
#define FLASH_BOOTCFG_EN   0x00000100
 
#define FLASH_BOOTCFG_KEY   0x00000010
 
#define FLASH_BOOTCFG_DBG1   0x00000002
 
#define FLASH_BOOTCFG_DBG0   0x00000001
 
#define FLASH_USERREG0_DATA_M   0xFFFFFFFF
 
#define FLASH_USERREG0_DATA_S   0
 
#define FLASH_USERREG1_DATA_M   0xFFFFFFFF
 
#define FLASH_USERREG1_DATA_S   0
 
#define FLASH_USERREG2_DATA_M   0xFFFFFFFF
 
#define FLASH_USERREG2_DATA_S   0
 
#define FLASH_USERREG3_DATA_M   0xFFFFFFFF
 
#define FLASH_USERREG3_DATA_S   0
 
#define SYSCTL_DID0_VER_M   0x70000000
 
#define SYSCTL_DID0_VER_1   0x10000000
 
#define SYSCTL_DID0_CLASS_M   0x00FF0000
 
#define SYSCTL_DID0_CLASS_TM4C123    0x00050000
 
#define SYSCTL_DID0_MAJ_M   0x0000FF00
 
#define SYSCTL_DID0_MAJ_REVA   0x00000000
 
#define SYSCTL_DID0_MAJ_REVB   0x00000100
 
#define SYSCTL_DID0_MAJ_REVC   0x00000200
 
#define SYSCTL_DID0_MIN_M   0x000000FF
 
#define SYSCTL_DID0_MIN_0   0x00000000
 
#define SYSCTL_DID0_MIN_1   0x00000001
 
#define SYSCTL_DID0_MIN_2   0x00000002
 
#define SYSCTL_DID1_VER_M   0xF0000000
 
#define SYSCTL_DID1_VER_1   0x10000000
 
#define SYSCTL_DID1_FAM_M   0x0F000000
 
#define SYSCTL_DID1_FAM_TIVA   0x00000000
 
#define SYSCTL_DID1_PRTNO_M   0x00FF0000
 
#define SYSCTL_DID1_PRTNO_TM4C123GH6PM    0x00A10000
 
#define SYSCTL_DID1_PINCNT_M   0x0000E000
 
#define SYSCTL_DID1_PINCNT_100   0x00004000
 
#define SYSCTL_DID1_PINCNT_64   0x00006000
 
#define SYSCTL_DID1_PINCNT_144   0x00008000
 
#define SYSCTL_DID1_PINCNT_157   0x0000A000
 
#define SYSCTL_DID1_PINCNT_128   0x0000C000
 
#define SYSCTL_DID1_TEMP_M   0x000000E0
 
#define SYSCTL_DID1_TEMP_I   0x00000020
 
#define SYSCTL_DID1_TEMP_E   0x00000040
 
#define SYSCTL_DID1_TEMP_IE   0x00000060
 
#define SYSCTL_DID1_PKG_M   0x00000018
 
#define SYSCTL_DID1_PKG_QFP   0x00000008
 
#define SYSCTL_DID1_PKG_BGA   0x00000010
 
#define SYSCTL_DID1_ROHS   0x00000004
 
#define SYSCTL_DID1_QUAL_M   0x00000003
 
#define SYSCTL_DID1_QUAL_ES   0x00000000
 
#define SYSCTL_DID1_QUAL_PP   0x00000001
 
#define SYSCTL_DID1_QUAL_FQ   0x00000002
 
#define SYSCTL_DC0_SRAMSZ_M   0xFFFF0000
 
#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000
 
#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000
 
#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000
 
#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000
 
#define SYSCTL_DC0_SRAMSZ_12KB   0x002F0000
 
#define SYSCTL_DC0_SRAMSZ_16KB   0x003F0000
 
#define SYSCTL_DC0_SRAMSZ_20KB   0x004F0000
 
#define SYSCTL_DC0_SRAMSZ_24KB   0x005F0000
 
#define SYSCTL_DC0_SRAMSZ_32KB   0x007F0000
 
#define SYSCTL_DC0_FLASHSZ_M   0x0000FFFF
 
#define SYSCTL_DC0_FLASHSZ_8KB   0x00000003
 
#define SYSCTL_DC0_FLASHSZ_16KB   0x00000007
 
#define SYSCTL_DC0_FLASHSZ_32KB   0x0000000F
 
#define SYSCTL_DC0_FLASHSZ_64KB   0x0000001F
 
#define SYSCTL_DC0_FLASHSZ_96KB   0x0000002F
 
#define SYSCTL_DC0_FLASHSZ_128K   0x0000003F
 
#define SYSCTL_DC0_FLASHSZ_192K   0x0000005F
 
#define SYSCTL_DC0_FLASHSZ_256K   0x0000007F
 
#define SYSCTL_DC1_WDT1   0x10000000
 
#define SYSCTL_DC1_CAN1   0x02000000
 
#define SYSCTL_DC1_CAN0   0x01000000
 
#define SYSCTL_DC1_PWM1   0x00200000
 
#define SYSCTL_DC1_PWM0   0x00100000
 
#define SYSCTL_DC1_ADC1   0x00020000
 
#define SYSCTL_DC1_ADC0   0x00010000
 
#define SYSCTL_DC1_MINSYSDIV_M   0x0000F000
 
#define SYSCTL_DC1_MINSYSDIV_80   0x00001000
 
#define SYSCTL_DC1_MINSYSDIV_66   0x00002000
 
#define SYSCTL_DC1_MINSYSDIV_50   0x00003000
 
#define SYSCTL_DC1_MINSYSDIV_40   0x00004000
 
#define SYSCTL_DC1_MINSYSDIV_25   0x00007000
 
#define SYSCTL_DC1_MINSYSDIV_20   0x00009000
 
#define SYSCTL_DC1_ADC1SPD_M   0x00000C00
 
#define SYSCTL_DC1_ADC1SPD_125K   0x00000000
 
#define SYSCTL_DC1_ADC1SPD_250K   0x00000400
 
#define SYSCTL_DC1_ADC1SPD_500K   0x00000800
 
#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00
 
#define SYSCTL_DC1_ADC0SPD_M   0x00000300
 
#define SYSCTL_DC1_ADC0SPD_125K   0x00000000
 
#define SYSCTL_DC1_ADC0SPD_250K   0x00000100
 
#define SYSCTL_DC1_ADC0SPD_500K   0x00000200
 
#define SYSCTL_DC1_ADC0SPD_1M   0x00000300
 
#define SYSCTL_DC1_MPU   0x00000080
 
#define SYSCTL_DC1_HIB   0x00000040
 
#define SYSCTL_DC1_TEMP   0x00000020
 
#define SYSCTL_DC1_PLL   0x00000010
 
#define SYSCTL_DC1_WDT0   0x00000008
 
#define SYSCTL_DC1_SWO   0x00000004
 
#define SYSCTL_DC1_SWD   0x00000002
 
#define SYSCTL_DC1_JTAG   0x00000001
 
#define SYSCTL_DC2_EPI0   0x40000000
 
#define SYSCTL_DC2_I2S0   0x10000000
 
#define SYSCTL_DC2_COMP2   0x04000000
 
#define SYSCTL_DC2_COMP1   0x02000000
 
#define SYSCTL_DC2_COMP0   0x01000000
 
#define SYSCTL_DC2_TIMER3   0x00080000
 
#define SYSCTL_DC2_TIMER2   0x00040000
 
#define SYSCTL_DC2_TIMER1   0x00020000
 
#define SYSCTL_DC2_TIMER0   0x00010000
 
#define SYSCTL_DC2_I2C1HS   0x00008000
 
#define SYSCTL_DC2_I2C1   0x00004000
 
#define SYSCTL_DC2_I2C0HS   0x00002000
 
#define SYSCTL_DC2_I2C0   0x00001000
 
#define SYSCTL_DC2_QEI1   0x00000200
 
#define SYSCTL_DC2_QEI0   0x00000100
 
#define SYSCTL_DC2_SSI1   0x00000020
 
#define SYSCTL_DC2_SSI0   0x00000010
 
#define SYSCTL_DC2_UART2   0x00000004
 
#define SYSCTL_DC2_UART1   0x00000002
 
#define SYSCTL_DC2_UART0   0x00000001
 
#define SYSCTL_DC3_32KHZ   0x80000000
 
#define SYSCTL_DC3_CCP5   0x20000000
 
#define SYSCTL_DC3_CCP4   0x10000000
 
#define SYSCTL_DC3_CCP3   0x08000000
 
#define SYSCTL_DC3_CCP2   0x04000000
 
#define SYSCTL_DC3_CCP1   0x02000000
 
#define SYSCTL_DC3_CCP0   0x01000000
 
#define SYSCTL_DC3_ADC0AIN7   0x00800000
 
#define SYSCTL_DC3_ADC0AIN6   0x00400000
 
#define SYSCTL_DC3_ADC0AIN5   0x00200000
 
#define SYSCTL_DC3_ADC0AIN4   0x00100000
 
#define SYSCTL_DC3_ADC0AIN3   0x00080000
 
#define SYSCTL_DC3_ADC0AIN2   0x00040000
 
#define SYSCTL_DC3_ADC0AIN1   0x00020000
 
#define SYSCTL_DC3_ADC0AIN0   0x00010000
 
#define SYSCTL_DC3_PWMFAULT   0x00008000
 
#define SYSCTL_DC3_C2O   0x00004000
 
#define SYSCTL_DC3_C2PLUS   0x00002000
 
#define SYSCTL_DC3_C2MINUS   0x00001000
 
#define SYSCTL_DC3_C1O   0x00000800
 
#define SYSCTL_DC3_C1PLUS   0x00000400
 
#define SYSCTL_DC3_C1MINUS   0x00000200
 
#define SYSCTL_DC3_C0O   0x00000100
 
#define SYSCTL_DC3_C0PLUS   0x00000080
 
#define SYSCTL_DC3_C0MINUS   0x00000040
 
#define SYSCTL_DC3_PWM5   0x00000020
 
#define SYSCTL_DC3_PWM4   0x00000010
 
#define SYSCTL_DC3_PWM3   0x00000008
 
#define SYSCTL_DC3_PWM2   0x00000004
 
#define SYSCTL_DC3_PWM1   0x00000002
 
#define SYSCTL_DC3_PWM0   0x00000001
 
#define SYSCTL_DC4_EPHY0   0x40000000
 
#define SYSCTL_DC4_EMAC0   0x10000000
 
#define SYSCTL_DC4_E1588   0x01000000
 
#define SYSCTL_DC4_PICAL   0x00040000
 
#define SYSCTL_DC4_CCP7   0x00008000
 
#define SYSCTL_DC4_CCP6   0x00004000
 
#define SYSCTL_DC4_UDMA   0x00002000
 
#define SYSCTL_DC4_ROM   0x00001000
 
#define SYSCTL_DC4_GPIOJ   0x00000100
 
#define SYSCTL_DC4_GPIOH   0x00000080
 
#define SYSCTL_DC4_GPIOG   0x00000040
 
#define SYSCTL_DC4_GPIOF   0x00000020
 
#define SYSCTL_DC4_GPIOE   0x00000010
 
#define SYSCTL_DC4_GPIOD   0x00000008
 
#define SYSCTL_DC4_GPIOC   0x00000004
 
#define SYSCTL_DC4_GPIOB   0x00000002
 
#define SYSCTL_DC4_GPIOA   0x00000001
 
#define SYSCTL_DC5_PWMFAULT3   0x08000000
 
#define SYSCTL_DC5_PWMFAULT2   0x04000000
 
#define SYSCTL_DC5_PWMFAULT1   0x02000000
 
#define SYSCTL_DC5_PWMFAULT0   0x01000000
 
#define SYSCTL_DC5_PWMEFLT   0x00200000
 
#define SYSCTL_DC5_PWMESYNC   0x00100000
 
#define SYSCTL_DC5_PWM7   0x00000080
 
#define SYSCTL_DC5_PWM6   0x00000040
 
#define SYSCTL_DC5_PWM5   0x00000020
 
#define SYSCTL_DC5_PWM4   0x00000010
 
#define SYSCTL_DC5_PWM3   0x00000008
 
#define SYSCTL_DC5_PWM2   0x00000004
 
#define SYSCTL_DC5_PWM1   0x00000002
 
#define SYSCTL_DC5_PWM0   0x00000001
 
#define SYSCTL_DC6_USB0PHY   0x00000010
 
#define SYSCTL_DC6_USB0_M   0x00000003
 
#define SYSCTL_DC6_USB0_DEV   0x00000001
 
#define SYSCTL_DC6_USB0_HOSTDEV   0x00000002
 
#define SYSCTL_DC6_USB0_OTG   0x00000003
 
#define SYSCTL_DC7_DMACH30   0x40000000
 
#define SYSCTL_DC7_DMACH29   0x20000000
 
#define SYSCTL_DC7_DMACH28   0x10000000
 
#define SYSCTL_DC7_DMACH27   0x08000000
 
#define SYSCTL_DC7_DMACH26   0x04000000
 
#define SYSCTL_DC7_DMACH25   0x02000000
 
#define SYSCTL_DC7_DMACH24   0x01000000
 
#define SYSCTL_DC7_DMACH23   0x00800000
 
#define SYSCTL_DC7_DMACH22   0x00400000
 
#define SYSCTL_DC7_DMACH21   0x00200000
 
#define SYSCTL_DC7_DMACH20   0x00100000
 
#define SYSCTL_DC7_DMACH19   0x00080000
 
#define SYSCTL_DC7_DMACH18   0x00040000
 
#define SYSCTL_DC7_DMACH17   0x00020000
 
#define SYSCTL_DC7_DMACH16   0x00010000
 
#define SYSCTL_DC7_DMACH15   0x00008000
 
#define SYSCTL_DC7_DMACH14   0x00004000
 
#define SYSCTL_DC7_DMACH13   0x00002000
 
#define SYSCTL_DC7_DMACH12   0x00001000
 
#define SYSCTL_DC7_DMACH11   0x00000800
 
#define SYSCTL_DC7_DMACH10   0x00000400
 
#define SYSCTL_DC7_DMACH9   0x00000200
 
#define SYSCTL_DC7_DMACH8   0x00000100
 
#define SYSCTL_DC7_DMACH7   0x00000080
 
#define SYSCTL_DC7_DMACH6   0x00000040
 
#define SYSCTL_DC7_DMACH5   0x00000020
 
#define SYSCTL_DC7_DMACH4   0x00000010
 
#define SYSCTL_DC7_DMACH3   0x00000008
 
#define SYSCTL_DC7_DMACH2   0x00000004
 
#define SYSCTL_DC7_DMACH1   0x00000002
 
#define SYSCTL_DC7_DMACH0   0x00000001
 
#define SYSCTL_DC8_ADC1AIN15   0x80000000
 
#define SYSCTL_DC8_ADC1AIN14   0x40000000
 
#define SYSCTL_DC8_ADC1AIN13   0x20000000
 
#define SYSCTL_DC8_ADC1AIN12   0x10000000
 
#define SYSCTL_DC8_ADC1AIN11   0x08000000
 
#define SYSCTL_DC8_ADC1AIN10   0x04000000
 
#define SYSCTL_DC8_ADC1AIN9   0x02000000
 
#define SYSCTL_DC8_ADC1AIN8   0x01000000
 
#define SYSCTL_DC8_ADC1AIN7   0x00800000
 
#define SYSCTL_DC8_ADC1AIN6   0x00400000
 
#define SYSCTL_DC8_ADC1AIN5   0x00200000
 
#define SYSCTL_DC8_ADC1AIN4   0x00100000
 
#define SYSCTL_DC8_ADC1AIN3   0x00080000
 
#define SYSCTL_DC8_ADC1AIN2   0x00040000
 
#define SYSCTL_DC8_ADC1AIN1   0x00020000
 
#define SYSCTL_DC8_ADC1AIN0   0x00010000
 
#define SYSCTL_DC8_ADC0AIN15   0x00008000
 
#define SYSCTL_DC8_ADC0AIN14   0x00004000
 
#define SYSCTL_DC8_ADC0AIN13   0x00002000
 
#define SYSCTL_DC8_ADC0AIN12   0x00001000
 
#define SYSCTL_DC8_ADC0AIN11   0x00000800
 
#define SYSCTL_DC8_ADC0AIN10   0x00000400
 
#define SYSCTL_DC8_ADC0AIN9   0x00000200
 
#define SYSCTL_DC8_ADC0AIN8   0x00000100
 
#define SYSCTL_DC8_ADC0AIN7   0x00000080
 
#define SYSCTL_DC8_ADC0AIN6   0x00000040
 
#define SYSCTL_DC8_ADC0AIN5   0x00000020
 
#define SYSCTL_DC8_ADC0AIN4   0x00000010
 
#define SYSCTL_DC8_ADC0AIN3   0x00000008
 
#define SYSCTL_DC8_ADC0AIN2   0x00000004
 
#define SYSCTL_DC8_ADC0AIN1   0x00000002
 
#define SYSCTL_DC8_ADC0AIN0   0x00000001
 
#define SYSCTL_PBORCTL_BOR0   0x00000004
 
#define SYSCTL_PBORCTL_BOR1   0x00000002
 
#define SYSCTL_SRCR0_WDT1   0x10000000
 
#define SYSCTL_SRCR0_CAN1   0x02000000
 
#define SYSCTL_SRCR0_CAN0   0x01000000
 
#define SYSCTL_SRCR0_PWM0   0x00100000
 
#define SYSCTL_SRCR0_ADC1   0x00020000
 
#define SYSCTL_SRCR0_ADC0   0x00010000
 
#define SYSCTL_SRCR0_HIB   0x00000040
 
#define SYSCTL_SRCR0_WDT0   0x00000008
 
#define SYSCTL_SRCR1_COMP1   0x02000000
 
#define SYSCTL_SRCR1_COMP0   0x01000000
 
#define SYSCTL_SRCR1_TIMER3   0x00080000
 
#define SYSCTL_SRCR1_TIMER2   0x00040000
 
#define SYSCTL_SRCR1_TIMER1   0x00020000
 
#define SYSCTL_SRCR1_TIMER0   0x00010000
 
#define SYSCTL_SRCR1_I2C1   0x00004000
 
#define SYSCTL_SRCR1_I2C0   0x00001000
 
#define SYSCTL_SRCR1_QEI1   0x00000200
 
#define SYSCTL_SRCR1_QEI0   0x00000100
 
#define SYSCTL_SRCR1_SSI1   0x00000020
 
#define SYSCTL_SRCR1_SSI0   0x00000010
 
#define SYSCTL_SRCR1_UART2   0x00000004
 
#define SYSCTL_SRCR1_UART1   0x00000002
 
#define SYSCTL_SRCR1_UART0   0x00000001
 
#define SYSCTL_SRCR2_USB0   0x00010000
 
#define SYSCTL_SRCR2_UDMA   0x00002000
 
#define SYSCTL_SRCR2_GPIOF   0x00000020
 
#define SYSCTL_SRCR2_GPIOE   0x00000010
 
#define SYSCTL_SRCR2_GPIOD   0x00000008
 
#define SYSCTL_SRCR2_GPIOC   0x00000004
 
#define SYSCTL_SRCR2_GPIOB   0x00000002
 
#define SYSCTL_SRCR2_GPIOA   0x00000001
 
#define SYSCTL_RIS_BOR0RIS   0x00000800
 
#define SYSCTL_RIS_VDDARIS   0x00000400
 
#define SYSCTL_RIS_MOSCPUPRIS   0x00000100
 
#define SYSCTL_RIS_USBPLLLRIS   0x00000080
 
#define SYSCTL_RIS_PLLLRIS   0x00000040
 
#define SYSCTL_RIS_MOFRIS   0x00000008
 
#define SYSCTL_RIS_BOR1RIS   0x00000002
 
#define SYSCTL_IMC_BOR0IM   0x00000800
 
#define SYSCTL_IMC_VDDAIM   0x00000400
 
#define SYSCTL_IMC_MOSCPUPIM   0x00000100
 
#define SYSCTL_IMC_USBPLLLIM   0x00000080
 
#define SYSCTL_IMC_PLLLIM   0x00000040
 
#define SYSCTL_IMC_MOFIM   0x00000008
 
#define SYSCTL_IMC_BOR1IM   0x00000002
 
#define SYSCTL_MISC_BOR0MIS   0x00000800
 
#define SYSCTL_MISC_VDDAMIS   0x00000400
 
#define SYSCTL_MISC_MOSCPUPMIS   0x00000100
 
#define SYSCTL_MISC_USBPLLLMIS   0x00000080
 
#define SYSCTL_MISC_PLLLMIS   0x00000040
 
#define SYSCTL_MISC_MOFMIS   0x00000008
 
#define SYSCTL_MISC_BOR1MIS   0x00000002
 
#define SYSCTL_RESC_MOSCFAIL   0x00010000
 
#define SYSCTL_RESC_WDT1   0x00000020
 
#define SYSCTL_RESC_SW   0x00000010
 
#define SYSCTL_RESC_WDT0   0x00000008
 
#define SYSCTL_RESC_BOR   0x00000004
 
#define SYSCTL_RESC_POR   0x00000002
 
#define SYSCTL_RESC_EXT   0x00000001
 
#define SYSCTL_RCC_ACG   0x08000000
 
#define SYSCTL_RCC_SYSDIV_M   0x07800000
 
#define SYSCTL_RCC_USESYSDIV   0x00400000
 
#define SYSCTL_RCC_USEPWMDIV   0x00100000
 
#define SYSCTL_RCC_PWMDIV_M   0x000E0000
 
#define SYSCTL_RCC_PWMDIV_2   0x00000000
 
#define SYSCTL_RCC_PWMDIV_4   0x00020000
 
#define SYSCTL_RCC_PWMDIV_8   0x00040000
 
#define SYSCTL_RCC_PWMDIV_16   0x00060000
 
#define SYSCTL_RCC_PWMDIV_32   0x00080000
 
#define SYSCTL_RCC_PWMDIV_64   0x000A0000
 
#define SYSCTL_RCC_PWRDN   0x00002000
 
#define SYSCTL_RCC_BYPASS   0x00000800
 
#define SYSCTL_RCC_XTAL_M   0x000007C0
 
#define SYSCTL_RCC_XTAL_4MHZ   0x00000180
 
#define SYSCTL_RCC_XTAL_4_09MHZ   0x000001C0
 
#define SYSCTL_RCC_XTAL_4_91MHZ   0x00000200
 
#define SYSCTL_RCC_XTAL_5MHZ   0x00000240
 
#define SYSCTL_RCC_XTAL_5_12MHZ   0x00000280
 
#define SYSCTL_RCC_XTAL_6MHZ   0x000002C0
 
#define SYSCTL_RCC_XTAL_6_14MHZ   0x00000300
 
#define SYSCTL_RCC_XTAL_7_37MHZ   0x00000340
 
#define SYSCTL_RCC_XTAL_8MHZ   0x00000380
 
#define SYSCTL_RCC_XTAL_8_19MHZ   0x000003C0
 
#define SYSCTL_RCC_XTAL_10MHZ   0x00000400
 
#define SYSCTL_RCC_XTAL_12MHZ   0x00000440
 
#define SYSCTL_RCC_XTAL_12_2MHZ   0x00000480
 
#define SYSCTL_RCC_XTAL_13_5MHZ   0x000004C0
 
#define SYSCTL_RCC_XTAL_14_3MHZ   0x00000500
 
#define SYSCTL_RCC_XTAL_16MHZ   0x00000540
 
#define SYSCTL_RCC_XTAL_16_3MHZ   0x00000580
 
#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0
 
#define SYSCTL_RCC_XTAL_20MHZ   0x00000600
 
#define SYSCTL_RCC_XTAL_24MHZ   0x00000640
 
#define SYSCTL_RCC_XTAL_25MHZ   0x00000680
 
#define SYSCTL_RCC_OSCSRC_M   0x00000030
 
#define SYSCTL_RCC_OSCSRC_MAIN   0x00000000
 
#define SYSCTL_RCC_OSCSRC_INT   0x00000010
 
#define SYSCTL_RCC_OSCSRC_INT4   0x00000020
 
#define SYSCTL_RCC_OSCSRC_30   0x00000030
 
#define SYSCTL_RCC_MOSCDIS   0x00000001
 
#define SYSCTL_RCC_SYSDIV_S   23
 
#define SYSCTL_GPIOHBCTL_PORTF   0x00000020
 
#define SYSCTL_GPIOHBCTL_PORTE   0x00000010
 
#define SYSCTL_GPIOHBCTL_PORTD   0x00000008
 
#define SYSCTL_GPIOHBCTL_PORTC   0x00000004
 
#define SYSCTL_GPIOHBCTL_PORTB   0x00000002
 
#define SYSCTL_GPIOHBCTL_PORTA   0x00000001
 
#define SYSCTL_RCC2_USERCC2   0x80000000
 
#define SYSCTL_RCC2_DIV400   0x40000000
 
#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000
 
#define SYSCTL_RCC2_SYSDIV2LSB   0x00400000
 
#define SYSCTL_RCC2_USBPWRDN   0x00004000
 
#define SYSCTL_RCC2_PWRDN2   0x00002000
 
#define SYSCTL_RCC2_BYPASS2   0x00000800
 
#define SYSCTL_RCC2_OSCSRC2_M   0x00000070
 
#define SYSCTL_RCC2_OSCSRC2_MO   0x00000000
 
#define SYSCTL_RCC2_OSCSRC2_IO   0x00000010
 
#define SYSCTL_RCC2_OSCSRC2_IO4   0x00000020
 
#define SYSCTL_RCC2_OSCSRC2_30   0x00000030
 
#define SYSCTL_RCC2_OSCSRC2_32   0x00000070
 
#define SYSCTL_RCC2_SYSDIV2_S   23
 
#define SYSCTL_MOSCCTL_NOXTAL   0x00000004
 
#define SYSCTL_MOSCCTL_MOSCIM   0x00000002
 
#define SYSCTL_MOSCCTL_CVAL   0x00000001
 
#define SYSCTL_RCGC0_WDT1   0x10000000
 
#define SYSCTL_RCGC0_CAN1   0x02000000
 
#define SYSCTL_RCGC0_CAN0   0x01000000
 
#define SYSCTL_RCGC0_PWM0   0x00100000
 
#define SYSCTL_RCGC0_ADC1   0x00020000
 
#define SYSCTL_RCGC0_ADC0   0x00010000
 
#define SYSCTL_RCGC0_ADC1SPD_M   0x00000C00
 
#define SYSCTL_RCGC0_ADC1SPD_125K    0x00000000
 
#define SYSCTL_RCGC0_ADC1SPD_250K    0x00000400
 
#define SYSCTL_RCGC0_ADC1SPD_500K    0x00000800
 
#define SYSCTL_RCGC0_ADC1SPD_1M   0x00000C00
 
#define SYSCTL_RCGC0_ADC0SPD_M   0x00000300
 
#define SYSCTL_RCGC0_ADC0SPD_125K    0x00000000
 
#define SYSCTL_RCGC0_ADC0SPD_250K    0x00000100
 
#define SYSCTL_RCGC0_ADC0SPD_500K    0x00000200
 
#define SYSCTL_RCGC0_ADC0SPD_1M   0x00000300
 
#define SYSCTL_RCGC0_HIB   0x00000040
 
#define SYSCTL_RCGC0_WDT0   0x00000008
 
#define SYSCTL_RCGC1_COMP1   0x02000000
 
#define SYSCTL_RCGC1_COMP0   0x01000000
 
#define SYSCTL_RCGC1_TIMER3   0x00080000
 
#define SYSCTL_RCGC1_TIMER2   0x00040000
 
#define SYSCTL_RCGC1_TIMER1   0x00020000
 
#define SYSCTL_RCGC1_TIMER0   0x00010000
 
#define SYSCTL_RCGC1_I2C1   0x00004000
 
#define SYSCTL_RCGC1_I2C0   0x00001000
 
#define SYSCTL_RCGC1_QEI1   0x00000200
 
#define SYSCTL_RCGC1_QEI0   0x00000100
 
#define SYSCTL_RCGC1_SSI1   0x00000020
 
#define SYSCTL_RCGC1_SSI0   0x00000010
 
#define SYSCTL_RCGC1_UART2   0x00000004
 
#define SYSCTL_RCGC1_UART1   0x00000002
 
#define SYSCTL_RCGC1_UART0   0x00000001
 
#define SYSCTL_RCGC2_USB0   0x00010000
 
#define SYSCTL_RCGC2_UDMA   0x00002000
 
#define SYSCTL_RCGC2_GPIOF   0x00000020
 
#define SYSCTL_RCGC2_GPIOE   0x00000010
 
#define SYSCTL_RCGC2_GPIOD   0x00000008
 
#define SYSCTL_RCGC2_GPIOC   0x00000004
 
#define SYSCTL_RCGC2_GPIOB   0x00000002
 
#define SYSCTL_RCGC2_GPIOA   0x00000001
 
#define SYSCTL_SCGC0_WDT1   0x10000000
 
#define SYSCTL_SCGC0_CAN1   0x02000000
 
#define SYSCTL_SCGC0_CAN0   0x01000000
 
#define SYSCTL_SCGC0_PWM0   0x00100000
 
#define SYSCTL_SCGC0_ADC1   0x00020000
 
#define SYSCTL_SCGC0_ADC0   0x00010000
 
#define SYSCTL_SCGC0_HIB   0x00000040
 
#define SYSCTL_SCGC0_WDT0   0x00000008
 
#define SYSCTL_SCGC1_COMP1   0x02000000
 
#define SYSCTL_SCGC1_COMP0   0x01000000
 
#define SYSCTL_SCGC1_TIMER3   0x00080000
 
#define SYSCTL_SCGC1_TIMER2   0x00040000
 
#define SYSCTL_SCGC1_TIMER1   0x00020000
 
#define SYSCTL_SCGC1_TIMER0   0x00010000
 
#define SYSCTL_SCGC1_I2C1   0x00004000
 
#define SYSCTL_SCGC1_I2C0   0x00001000
 
#define SYSCTL_SCGC1_QEI1   0x00000200
 
#define SYSCTL_SCGC1_QEI0   0x00000100
 
#define SYSCTL_SCGC1_SSI1   0x00000020
 
#define SYSCTL_SCGC1_SSI0   0x00000010
 
#define SYSCTL_SCGC1_UART2   0x00000004
 
#define SYSCTL_SCGC1_UART1   0x00000002
 
#define SYSCTL_SCGC1_UART0   0x00000001
 
#define SYSCTL_SCGC2_USB0   0x00010000
 
#define SYSCTL_SCGC2_UDMA   0x00002000
 
#define SYSCTL_SCGC2_GPIOF   0x00000020
 
#define SYSCTL_SCGC2_GPIOE   0x00000010
 
#define SYSCTL_SCGC2_GPIOD   0x00000008
 
#define SYSCTL_SCGC2_GPIOC   0x00000004
 
#define SYSCTL_SCGC2_GPIOB   0x00000002
 
#define SYSCTL_SCGC2_GPIOA   0x00000001
 
#define SYSCTL_DCGC0_WDT1   0x10000000
 
#define SYSCTL_DCGC0_CAN1   0x02000000
 
#define SYSCTL_DCGC0_CAN0   0x01000000
 
#define SYSCTL_DCGC0_PWM0   0x00100000
 
#define SYSCTL_DCGC0_ADC1   0x00020000
 
#define SYSCTL_DCGC0_ADC0   0x00010000
 
#define SYSCTL_DCGC0_HIB   0x00000040
 
#define SYSCTL_DCGC0_WDT0   0x00000008
 
#define SYSCTL_DCGC1_COMP1   0x02000000
 
#define SYSCTL_DCGC1_COMP0   0x01000000
 
#define SYSCTL_DCGC1_TIMER3   0x00080000
 
#define SYSCTL_DCGC1_TIMER2   0x00040000
 
#define SYSCTL_DCGC1_TIMER1   0x00020000
 
#define SYSCTL_DCGC1_TIMER0   0x00010000
 
#define SYSCTL_DCGC1_I2C1   0x00004000
 
#define SYSCTL_DCGC1_I2C0   0x00001000
 
#define SYSCTL_DCGC1_QEI1   0x00000200
 
#define SYSCTL_DCGC1_QEI0   0x00000100
 
#define SYSCTL_DCGC1_SSI1   0x00000020
 
#define SYSCTL_DCGC1_SSI0   0x00000010
 
#define SYSCTL_DCGC1_UART2   0x00000004
 
#define SYSCTL_DCGC1_UART1   0x00000002
 
#define SYSCTL_DCGC1_UART0   0x00000001
 
#define SYSCTL_DCGC2_USB0   0x00010000
 
#define SYSCTL_DCGC2_UDMA   0x00002000
 
#define SYSCTL_DCGC2_GPIOF   0x00000020
 
#define SYSCTL_DCGC2_GPIOE   0x00000010
 
#define SYSCTL_DCGC2_GPIOD   0x00000008
 
#define SYSCTL_DCGC2_GPIOC   0x00000004
 
#define SYSCTL_DCGC2_GPIOB   0x00000002
 
#define SYSCTL_DCGC2_GPIOA   0x00000001
 
#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000
 
#define SYSCTL_DSLPCLKCFG_O_M   0x00000070
 
#define SYSCTL_DSLPCLKCFG_O_IGN   0x00000000
 
#define SYSCTL_DSLPCLKCFG_O_IO   0x00000010
 
#define SYSCTL_DSLPCLKCFG_O_30   0x00000030
 
#define SYSCTL_DSLPCLKCFG_O_32   0x00000070
 
#define SYSCTL_DSLPCLKCFG_PIOSCPD    0x00000002
 
#define SYSCTL_DSLPCLKCFG_D_S   23
 
#define SYSCTL_SYSPROP_FPU   0x00000001
 
#define SYSCTL_PIOSCCAL_UTEN   0x80000000
 
#define SYSCTL_PIOSCCAL_CAL   0x00000200
 
#define SYSCTL_PIOSCCAL_UPDATE   0x00000100
 
#define SYSCTL_PIOSCCAL_UT_M   0x0000007F
 
#define SYSCTL_PIOSCCAL_UT_S   0
 
#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000
 
#define SYSCTL_PIOSCSTAT_CR_M   0x00000300
 
#define SYSCTL_PIOSCSTAT_CRNONE   0x00000000
 
#define SYSCTL_PIOSCSTAT_CRPASS   0x00000100
 
#define SYSCTL_PIOSCSTAT_CRFAIL   0x00000200
 
#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F
 
#define SYSCTL_PIOSCSTAT_DT_S   16
 
#define SYSCTL_PIOSCSTAT_CT_S   0
 
#define SYSCTL_PLLFREQ0_MFRAC_M   0x000FFC00
 
#define SYSCTL_PLLFREQ0_MINT_M   0x000003FF
 
#define SYSCTL_PLLFREQ0_MFRAC_S   10
 
#define SYSCTL_PLLFREQ0_MINT_S   0
 
#define SYSCTL_PLLFREQ1_Q_M   0x00001F00
 
#define SYSCTL_PLLFREQ1_N_M   0x0000001F
 
#define SYSCTL_PLLFREQ1_Q_S   8
 
#define SYSCTL_PLLFREQ1_N_S   0
 
#define SYSCTL_PLLSTAT_LOCK   0x00000001
 
#define SYSCTL_SLPPWRCFG_FLASHPM_M    0x00000030
 
#define SYSCTL_SLPPWRCFG_FLASHPM_NRM    0x00000000
 
#define SYSCTL_SLPPWRCFG_FLASHPM_SLP    0x00000020
 
#define SYSCTL_SLPPWRCFG_SRAMPM_M    0x00000003
 
#define SYSCTL_SLPPWRCFG_SRAMPM_NRM    0x00000000
 
#define SYSCTL_SLPPWRCFG_SRAMPM_SBY    0x00000001
 
#define SYSCTL_SLPPWRCFG_SRAMPM_LP    0x00000003
 
#define SYSCTL_DSLPPWRCFG_FLASHPM_M    0x00000030
 
#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM    0x00000000
 
#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP    0x00000020
 
#define SYSCTL_DSLPPWRCFG_SRAMPM_M    0x00000003
 
#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM    0x00000000
 
#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY    0x00000001
 
#define SYSCTL_DSLPPWRCFG_SRAMPM_LP    0x00000003
 
#define SYSCTL_DC9_ADC1DC7   0x00800000
 
#define SYSCTL_DC9_ADC1DC6   0x00400000
 
#define SYSCTL_DC9_ADC1DC5   0x00200000
 
#define SYSCTL_DC9_ADC1DC4   0x00100000
 
#define SYSCTL_DC9_ADC1DC3   0x00080000
 
#define SYSCTL_DC9_ADC1DC2   0x00040000
 
#define SYSCTL_DC9_ADC1DC1   0x00020000
 
#define SYSCTL_DC9_ADC1DC0   0x00010000
 
#define SYSCTL_DC9_ADC0DC7   0x00000080
 
#define SYSCTL_DC9_ADC0DC6   0x00000040
 
#define SYSCTL_DC9_ADC0DC5   0x00000020
 
#define SYSCTL_DC9_ADC0DC4   0x00000010
 
#define SYSCTL_DC9_ADC0DC3   0x00000008
 
#define SYSCTL_DC9_ADC0DC2   0x00000004
 
#define SYSCTL_DC9_ADC0DC1   0x00000002
 
#define SYSCTL_DC9_ADC0DC0   0x00000001
 
#define SYSCTL_NVMSTAT_FWB   0x00000001
 
#define SYSCTL_LDOSPCTL_VADJEN   0x80000000
 
#define SYSCTL_LDOSPCTL_VLDO_M   0x000000FF
 
#define SYSCTL_LDOSPCTL_VLDO_0_90V    0x00000012
 
#define SYSCTL_LDOSPCTL_VLDO_0_95V    0x00000013
 
#define SYSCTL_LDOSPCTL_VLDO_1_00V    0x00000014
 
#define SYSCTL_LDOSPCTL_VLDO_1_05V    0x00000015
 
#define SYSCTL_LDOSPCTL_VLDO_1_10V    0x00000016
 
#define SYSCTL_LDOSPCTL_VLDO_1_15V    0x00000017
 
#define SYSCTL_LDOSPCTL_VLDO_1_20V    0x00000018
 
#define SYSCTL_LDODPCTL_VADJEN   0x80000000
 
#define SYSCTL_LDODPCTL_VLDO_M   0x000000FF
 
#define SYSCTL_LDODPCTL_VLDO_0_90V    0x00000012
 
#define SYSCTL_LDODPCTL_VLDO_0_95V    0x00000013
 
#define SYSCTL_LDODPCTL_VLDO_1_00V    0x00000014
 
#define SYSCTL_LDODPCTL_VLDO_1_05V    0x00000015
 
#define SYSCTL_LDODPCTL_VLDO_1_10V    0x00000016
 
#define SYSCTL_LDODPCTL_VLDO_1_15V    0x00000017
 
#define SYSCTL_LDODPCTL_VLDO_1_20V    0x00000018
 
#define SYSCTL_PPWD_P1   0x00000002
 
#define SYSCTL_PPWD_P0   0x00000001
 
#define SYSCTL_PPTIMER_P5   0x00000020
 
#define SYSCTL_PPTIMER_P4   0x00000010
 
#define SYSCTL_PPTIMER_P3   0x00000008
 
#define SYSCTL_PPTIMER_P2   0x00000004
 
#define SYSCTL_PPTIMER_P1   0x00000002
 
#define SYSCTL_PPTIMER_P0   0x00000001
 
#define SYSCTL_PPGPIO_P14   0x00004000
 
#define SYSCTL_PPGPIO_P13   0x00002000
 
#define SYSCTL_PPGPIO_P12   0x00001000
 
#define SYSCTL_PPGPIO_P11   0x00000800
 
#define SYSCTL_PPGPIO_P10   0x00000400
 
#define SYSCTL_PPGPIO_P9   0x00000200
 
#define SYSCTL_PPGPIO_P8   0x00000100
 
#define SYSCTL_PPGPIO_P7   0x00000080
 
#define SYSCTL_PPGPIO_P6   0x00000040
 
#define SYSCTL_PPGPIO_P5   0x00000020
 
#define SYSCTL_PPGPIO_P4   0x00000010
 
#define SYSCTL_PPGPIO_P3   0x00000008
 
#define SYSCTL_PPGPIO_P2   0x00000004
 
#define SYSCTL_PPGPIO_P1   0x00000002
 
#define SYSCTL_PPGPIO_P0   0x00000001
 
#define SYSCTL_PPDMA_P0   0x00000001
 
#define SYSCTL_PPHIB_P0   0x00000001
 
#define SYSCTL_PPUART_P7   0x00000080
 
#define SYSCTL_PPUART_P6   0x00000040
 
#define SYSCTL_PPUART_P5   0x00000020
 
#define SYSCTL_PPUART_P4   0x00000010
 
#define SYSCTL_PPUART_P3   0x00000008
 
#define SYSCTL_PPUART_P2   0x00000004
 
#define SYSCTL_PPUART_P1   0x00000002
 
#define SYSCTL_PPUART_P0   0x00000001
 
#define SYSCTL_PPSSI_P3   0x00000008
 
#define SYSCTL_PPSSI_P2   0x00000004
 
#define SYSCTL_PPSSI_P1   0x00000002
 
#define SYSCTL_PPSSI_P0   0x00000001
 
#define SYSCTL_PPI2C_P5   0x00000020
 
#define SYSCTL_PPI2C_P4   0x00000010
 
#define SYSCTL_PPI2C_P3   0x00000008
 
#define SYSCTL_PPI2C_P2   0x00000004
 
#define SYSCTL_PPI2C_P1   0x00000002
 
#define SYSCTL_PPI2C_P0   0x00000001
 
#define SYSCTL_PPUSB_P0   0x00000001
 
#define SYSCTL_PPCAN_P1   0x00000002
 
#define SYSCTL_PPCAN_P0   0x00000001
 
#define SYSCTL_PPADC_P1   0x00000002
 
#define SYSCTL_PPADC_P0   0x00000001
 
#define SYSCTL_PPACMP_P0   0x00000001
 
#define SYSCTL_PPPWM_P1   0x00000002
 
#define SYSCTL_PPPWM_P0   0x00000001
 
#define SYSCTL_PPQEI_P1   0x00000002
 
#define SYSCTL_PPQEI_P0   0x00000001
 
#define SYSCTL_PPEEPROM_P0   0x00000001
 
#define SYSCTL_PPWTIMER_P5   0x00000020
 
#define SYSCTL_PPWTIMER_P4   0x00000010
 
#define SYSCTL_PPWTIMER_P3   0x00000008
 
#define SYSCTL_PPWTIMER_P2   0x00000004
 
#define SYSCTL_PPWTIMER_P1   0x00000002
 
#define SYSCTL_PPWTIMER_P0   0x00000001
 
#define SYSCTL_SRWD_R1   0x00000002
 
#define SYSCTL_SRWD_R0   0x00000001
 
#define SYSCTL_SRTIMER_R5   0x00000020
 
#define SYSCTL_SRTIMER_R4   0x00000010
 
#define SYSCTL_SRTIMER_R3   0x00000008
 
#define SYSCTL_SRTIMER_R2   0x00000004
 
#define SYSCTL_SRTIMER_R1   0x00000002
 
#define SYSCTL_SRTIMER_R0   0x00000001
 
#define SYSCTL_SRGPIO_R5   0x00000020
 
#define SYSCTL_SRGPIO_R4   0x00000010
 
#define SYSCTL_SRGPIO_R3   0x00000008
 
#define SYSCTL_SRGPIO_R2   0x00000004
 
#define SYSCTL_SRGPIO_R1   0x00000002
 
#define SYSCTL_SRGPIO_R0   0x00000001
 
#define SYSCTL_SRDMA_R0   0x00000001
 
#define SYSCTL_SRHIB_R0   0x00000001
 
#define SYSCTL_SRUART_R7   0x00000080
 
#define SYSCTL_SRUART_R6   0x00000040
 
#define SYSCTL_SRUART_R5   0x00000020
 
#define SYSCTL_SRUART_R4   0x00000010
 
#define SYSCTL_SRUART_R3   0x00000008
 
#define SYSCTL_SRUART_R2   0x00000004
 
#define SYSCTL_SRUART_R1   0x00000002
 
#define SYSCTL_SRUART_R0   0x00000001
 
#define SYSCTL_SRSSI_R3   0x00000008
 
#define SYSCTL_SRSSI_R2   0x00000004
 
#define SYSCTL_SRSSI_R1   0x00000002
 
#define SYSCTL_SRSSI_R0   0x00000001
 
#define SYSCTL_SRI2C_R3   0x00000008
 
#define SYSCTL_SRI2C_R2   0x00000004
 
#define SYSCTL_SRI2C_R1   0x00000002
 
#define SYSCTL_SRI2C_R0   0x00000001
 
#define SYSCTL_SRUSB_R0   0x00000001
 
#define SYSCTL_SRCAN_R1   0x00000002
 
#define SYSCTL_SRCAN_R0   0x00000001
 
#define SYSCTL_SRADC_R1   0x00000002
 
#define SYSCTL_SRADC_R0   0x00000001
 
#define SYSCTL_SRACMP_R0   0x00000001
 
#define SYSCTL_SRPWM_R1   0x00000002
 
#define SYSCTL_SRPWM_R0   0x00000001
 
#define SYSCTL_SRQEI_R1   0x00000002
 
#define SYSCTL_SRQEI_R0   0x00000001
 
#define SYSCTL_SREEPROM_R0   0x00000001
 
#define SYSCTL_SRWTIMER_R5   0x00000020
 
#define SYSCTL_SRWTIMER_R4   0x00000010
 
#define SYSCTL_SRWTIMER_R3   0x00000008
 
#define SYSCTL_SRWTIMER_R2   0x00000004
 
#define SYSCTL_SRWTIMER_R1   0x00000002
 
#define SYSCTL_SRWTIMER_R0   0x00000001
 
#define SYSCTL_RCGCWD_R1   0x00000002
 
#define SYSCTL_RCGCWD_R0   0x00000001
 
#define SYSCTL_RCGCTIMER_R5   0x00000020
 
#define SYSCTL_RCGCTIMER_R4   0x00000010
 
#define SYSCTL_RCGCTIMER_R3   0x00000008
 
#define SYSCTL_RCGCTIMER_R2   0x00000004
 
#define SYSCTL_RCGCTIMER_R1   0x00000002
 
#define SYSCTL_RCGCTIMER_R0   0x00000001
 
#define SYSCTL_RCGCGPIO_R5   0x00000020
 
#define SYSCTL_RCGCGPIO_R4   0x00000010
 
#define SYSCTL_RCGCGPIO_R3   0x00000008
 
#define SYSCTL_RCGCGPIO_R2   0x00000004
 
#define SYSCTL_RCGCGPIO_R1   0x00000002
 
#define SYSCTL_RCGCGPIO_R0   0x00000001
 
#define SYSCTL_RCGCDMA_R0   0x00000001
 
#define SYSCTL_RCGCHIB_R0   0x00000001
 
#define SYSCTL_RCGCUART_R7   0x00000080
 
#define SYSCTL_RCGCUART_R6   0x00000040
 
#define SYSCTL_RCGCUART_R5   0x00000020
 
#define SYSCTL_RCGCUART_R4   0x00000010
 
#define SYSCTL_RCGCUART_R3   0x00000008
 
#define SYSCTL_RCGCUART_R2   0x00000004
 
#define SYSCTL_RCGCUART_R1   0x00000002
 
#define SYSCTL_RCGCUART_R0   0x00000001
 
#define SYSCTL_RCGCSSI_R3   0x00000008
 
#define SYSCTL_RCGCSSI_R2   0x00000004
 
#define SYSCTL_RCGCSSI_R1   0x00000002
 
#define SYSCTL_RCGCSSI_R0   0x00000001
 
#define SYSCTL_RCGCI2C_R3   0x00000008
 
#define SYSCTL_RCGCI2C_R2   0x00000004
 
#define SYSCTL_RCGCI2C_R1   0x00000002
 
#define SYSCTL_RCGCI2C_R0   0x00000001
 
#define SYSCTL_RCGCUSB_R0   0x00000001
 
#define SYSCTL_RCGCCAN_R1   0x00000002
 
#define SYSCTL_RCGCCAN_R0   0x00000001
 
#define SYSCTL_RCGCADC_R1   0x00000002
 
#define SYSCTL_RCGCADC_R0   0x00000001
 
#define SYSCTL_RCGCACMP_R0   0x00000001
 
#define SYSCTL_RCGCPWM_R1   0x00000002
 
#define SYSCTL_RCGCPWM_R0   0x00000001
 
#define SYSCTL_RCGCQEI_R1   0x00000002
 
#define SYSCTL_RCGCQEI_R0   0x00000001
 
#define SYSCTL_RCGCEEPROM_R0   0x00000001
 
#define SYSCTL_RCGCWTIMER_R5   0x00000020
 
#define SYSCTL_RCGCWTIMER_R4   0x00000010
 
#define SYSCTL_RCGCWTIMER_R3   0x00000008
 
#define SYSCTL_RCGCWTIMER_R2   0x00000004
 
#define SYSCTL_RCGCWTIMER_R1   0x00000002
 
#define SYSCTL_RCGCWTIMER_R0   0x00000001
 
#define SYSCTL_SCGCWD_S1   0x00000002
 
#define SYSCTL_SCGCWD_S0   0x00000001
 
#define SYSCTL_SCGCTIMER_S5   0x00000020
 
#define SYSCTL_SCGCTIMER_S4   0x00000010
 
#define SYSCTL_SCGCTIMER_S3   0x00000008
 
#define SYSCTL_SCGCTIMER_S2   0x00000004
 
#define SYSCTL_SCGCTIMER_S1   0x00000002
 
#define SYSCTL_SCGCTIMER_S0   0x00000001
 
#define SYSCTL_SCGCGPIO_S5   0x00000020
 
#define SYSCTL_SCGCGPIO_S4   0x00000010
 
#define SYSCTL_SCGCGPIO_S3   0x00000008
 
#define SYSCTL_SCGCGPIO_S2   0x00000004
 
#define SYSCTL_SCGCGPIO_S1   0x00000002
 
#define SYSCTL_SCGCGPIO_S0   0x00000001
 
#define SYSCTL_SCGCDMA_S0   0x00000001
 
#define SYSCTL_SCGCHIB_S0   0x00000001
 
#define SYSCTL_SCGCUART_S7   0x00000080
 
#define SYSCTL_SCGCUART_S6   0x00000040
 
#define SYSCTL_SCGCUART_S5   0x00000020
 
#define SYSCTL_SCGCUART_S4   0x00000010
 
#define SYSCTL_SCGCUART_S3   0x00000008
 
#define SYSCTL_SCGCUART_S2   0x00000004
 
#define SYSCTL_SCGCUART_S1   0x00000002
 
#define SYSCTL_SCGCUART_S0   0x00000001
 
#define SYSCTL_SCGCSSI_S3   0x00000008
 
#define SYSCTL_SCGCSSI_S2   0x00000004
 
#define SYSCTL_SCGCSSI_S1   0x00000002
 
#define SYSCTL_SCGCSSI_S0   0x00000001
 
#define SYSCTL_SCGCI2C_S3   0x00000008
 
#define SYSCTL_SCGCI2C_S2   0x00000004
 
#define SYSCTL_SCGCI2C_S1   0x00000002
 
#define SYSCTL_SCGCI2C_S0   0x00000001
 
#define SYSCTL_SCGCUSB_S0   0x00000001
 
#define SYSCTL_SCGCCAN_S1   0x00000002
 
#define SYSCTL_SCGCCAN_S0   0x00000001
 
#define SYSCTL_SCGCADC_S1   0x00000002
 
#define SYSCTL_SCGCADC_S0   0x00000001
 
#define SYSCTL_SCGCACMP_S0   0x00000001
 
#define SYSCTL_SCGCPWM_S1   0x00000002
 
#define SYSCTL_SCGCPWM_S0   0x00000001
 
#define SYSCTL_SCGCQEI_S1   0x00000002
 
#define SYSCTL_SCGCQEI_S0   0x00000001
 
#define SYSCTL_SCGCEEPROM_S0   0x00000001
 
#define SYSCTL_SCGCWTIMER_S5   0x00000020
 
#define SYSCTL_SCGCWTIMER_S4   0x00000010
 
#define SYSCTL_SCGCWTIMER_S3   0x00000008
 
#define SYSCTL_SCGCWTIMER_S2   0x00000004
 
#define SYSCTL_SCGCWTIMER_S1   0x00000002
 
#define SYSCTL_SCGCWTIMER_S0   0x00000001
 
#define SYSCTL_DCGCWD_D1   0x00000002
 
#define SYSCTL_DCGCWD_D0   0x00000001
 
#define SYSCTL_DCGCTIMER_D5   0x00000020
 
#define SYSCTL_DCGCTIMER_D4   0x00000010
 
#define SYSCTL_DCGCTIMER_D3   0x00000008
 
#define SYSCTL_DCGCTIMER_D2   0x00000004
 
#define SYSCTL_DCGCTIMER_D1   0x00000002
 
#define SYSCTL_DCGCTIMER_D0   0x00000001
 
#define SYSCTL_DCGCGPIO_D5   0x00000020
 
#define SYSCTL_DCGCGPIO_D4   0x00000010
 
#define SYSCTL_DCGCGPIO_D3   0x00000008
 
#define SYSCTL_DCGCGPIO_D2   0x00000004
 
#define SYSCTL_DCGCGPIO_D1   0x00000002
 
#define SYSCTL_DCGCGPIO_D0   0x00000001
 
#define SYSCTL_DCGCDMA_D0   0x00000001
 
#define SYSCTL_DCGCHIB_D0   0x00000001
 
#define SYSCTL_DCGCUART_D7   0x00000080
 
#define SYSCTL_DCGCUART_D6   0x00000040
 
#define SYSCTL_DCGCUART_D5   0x00000020
 
#define SYSCTL_DCGCUART_D4   0x00000010
 
#define SYSCTL_DCGCUART_D3   0x00000008
 
#define SYSCTL_DCGCUART_D2   0x00000004
 
#define SYSCTL_DCGCUART_D1   0x00000002
 
#define SYSCTL_DCGCUART_D0   0x00000001
 
#define SYSCTL_DCGCSSI_D3   0x00000008
 
#define SYSCTL_DCGCSSI_D2   0x00000004
 
#define SYSCTL_DCGCSSI_D1   0x00000002
 
#define SYSCTL_DCGCSSI_D0   0x00000001
 
#define SYSCTL_DCGCI2C_D3   0x00000008
 
#define SYSCTL_DCGCI2C_D2   0x00000004
 
#define SYSCTL_DCGCI2C_D1   0x00000002
 
#define SYSCTL_DCGCI2C_D0   0x00000001
 
#define SYSCTL_DCGCUSB_D0   0x00000001
 
#define SYSCTL_DCGCCAN_D1   0x00000002
 
#define SYSCTL_DCGCCAN_D0   0x00000001
 
#define SYSCTL_DCGCADC_D1   0x00000002
 
#define SYSCTL_DCGCADC_D0   0x00000001
 
#define SYSCTL_DCGCACMP_D0   0x00000001
 
#define SYSCTL_DCGCPWM_D1   0x00000002
 
#define SYSCTL_DCGCPWM_D0   0x00000001
 
#define SYSCTL_DCGCQEI_D1   0x00000002
 
#define SYSCTL_DCGCQEI_D0   0x00000001
 
#define SYSCTL_DCGCEEPROM_D0   0x00000001
 
#define SYSCTL_DCGCWTIMER_D5   0x00000020
 
#define SYSCTL_DCGCWTIMER_D4   0x00000010
 
#define SYSCTL_DCGCWTIMER_D3   0x00000008
 
#define SYSCTL_DCGCWTIMER_D2   0x00000004
 
#define SYSCTL_DCGCWTIMER_D1   0x00000002
 
#define SYSCTL_DCGCWTIMER_D0   0x00000001
 
#define SYSCTL_PRWD_R1   0x00000002
 
#define SYSCTL_PRWD_R0   0x00000001
 
#define SYSCTL_PRTIMER_R5   0x00000020
 
#define SYSCTL_PRTIMER_R4   0x00000010
 
#define SYSCTL_PRTIMER_R3   0x00000008
 
#define SYSCTL_PRTIMER_R2   0x00000004
 
#define SYSCTL_PRTIMER_R1   0x00000002
 
#define SYSCTL_PRTIMER_R0   0x00000001
 
#define SYSCTL_PRGPIO_R5   0x00000020
 
#define SYSCTL_PRGPIO_R4   0x00000010
 
#define SYSCTL_PRGPIO_R3   0x00000008
 
#define SYSCTL_PRGPIO_R2   0x00000004
 
#define SYSCTL_PRGPIO_R1   0x00000002
 
#define SYSCTL_PRGPIO_R0   0x00000001
 
#define SYSCTL_PRDMA_R0   0x00000001
 
#define SYSCTL_PRHIB_R0   0x00000001
 
#define SYSCTL_PRUART_R7   0x00000080
 
#define SYSCTL_PRUART_R6   0x00000040
 
#define SYSCTL_PRUART_R5   0x00000020
 
#define SYSCTL_PRUART_R4   0x00000010
 
#define SYSCTL_PRUART_R3   0x00000008
 
#define SYSCTL_PRUART_R2   0x00000004
 
#define SYSCTL_PRUART_R1   0x00000002
 
#define SYSCTL_PRUART_R0   0x00000001
 
#define SYSCTL_PRSSI_R3   0x00000008
 
#define SYSCTL_PRSSI_R2   0x00000004
 
#define SYSCTL_PRSSI_R1   0x00000002
 
#define SYSCTL_PRSSI_R0   0x00000001
 
#define SYSCTL_PRI2C_R3   0x00000008
 
#define SYSCTL_PRI2C_R2   0x00000004
 
#define SYSCTL_PRI2C_R1   0x00000002
 
#define SYSCTL_PRI2C_R0   0x00000001
 
#define SYSCTL_PRUSB_R0   0x00000001
 
#define SYSCTL_PRCAN_R1   0x00000002
 
#define SYSCTL_PRCAN_R0   0x00000001
 
#define SYSCTL_PRADC_R1   0x00000002
 
#define SYSCTL_PRADC_R0   0x00000001
 
#define SYSCTL_PRACMP_R0   0x00000001
 
#define SYSCTL_PRPWM_R1   0x00000002
 
#define SYSCTL_PRPWM_R0   0x00000001
 
#define SYSCTL_PRQEI_R1   0x00000002
 
#define SYSCTL_PRQEI_R0   0x00000001
 
#define SYSCTL_PREEPROM_R0   0x00000001
 
#define SYSCTL_PRWTIMER_R5   0x00000020
 
#define SYSCTL_PRWTIMER_R4   0x00000010
 
#define SYSCTL_PRWTIMER_R3   0x00000008
 
#define SYSCTL_PRWTIMER_R2   0x00000004
 
#define SYSCTL_PRWTIMER_R1   0x00000002
 
#define SYSCTL_PRWTIMER_R0   0x00000001
 
#define UDMA_STAT_DMACHANS_M   0x001F0000
 
#define UDMA_STAT_STATE_M   0x000000F0
 
#define UDMA_STAT_STATE_IDLE   0x00000000
 
#define UDMA_STAT_STATE_RD_CTRL   0x00000010
 
#define UDMA_STAT_STATE_RD_SRCENDP    0x00000020
 
#define UDMA_STAT_STATE_RD_DSTENDP    0x00000030
 
#define UDMA_STAT_STATE_RD_SRCDAT    0x00000040
 
#define UDMA_STAT_STATE_WR_DSTDAT    0x00000050
 
#define UDMA_STAT_STATE_WAIT   0x00000060
 
#define UDMA_STAT_STATE_WR_CTRL   0x00000070
 
#define UDMA_STAT_STATE_STALL   0x00000080
 
#define UDMA_STAT_STATE_DONE   0x00000090
 
#define UDMA_STAT_STATE_UNDEF   0x000000A0
 
#define UDMA_STAT_MASTEN   0x00000001
 
#define UDMA_STAT_DMACHANS_S   16
 
#define UDMA_CFG_MASTEN   0x00000001
 
#define UDMA_CTLBASE_ADDR_M   0xFFFFFC00
 
#define UDMA_CTLBASE_ADDR_S   10
 
#define UDMA_ALTBASE_ADDR_M   0xFFFFFFFF
 
#define UDMA_ALTBASE_ADDR_S   0
 
#define UDMA_WAITSTAT_WAITREQ_M   0xFFFFFFFF
 
#define UDMA_SWREQ_M   0xFFFFFFFF
 
#define UDMA_USEBURSTSET_SET_M   0xFFFFFFFF
 
#define UDMA_USEBURSTCLR_CLR_M   0xFFFFFFFF
 
#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF
 
#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF
 
#define UDMA_ENASET_SET_M   0xFFFFFFFF
 
#define UDMA_ENACLR_CLR_M   0xFFFFFFFF
 
#define UDMA_ALTSET_SET_M   0xFFFFFFFF
 
#define UDMA_ALTCLR_CLR_M   0xFFFFFFFF
 
#define UDMA_PRIOSET_SET_M   0xFFFFFFFF
 
#define UDMA_PRIOCLR_CLR_M   0xFFFFFFFF
 
#define UDMA_ERRCLR_ERRCLR   0x00000001
 
#define UDMA_CHASGN_M   0xFFFFFFFF
 
#define UDMA_CHASGN_PRIMARY   0x00000000
 
#define UDMA_CHASGN_SECONDARY   0x00000001
 
#define UDMA_CHIS_M   0xFFFFFFFF
 
#define UDMA_CHMAP0_CH7SEL_M   0xF0000000
 
#define UDMA_CHMAP0_CH6SEL_M   0x0F000000
 
#define UDMA_CHMAP0_CH5SEL_M   0x00F00000
 
#define UDMA_CHMAP0_CH4SEL_M   0x000F0000
 
#define UDMA_CHMAP0_CH3SEL_M   0x0000F000
 
#define UDMA_CHMAP0_CH2SEL_M   0x00000F00
 
#define UDMA_CHMAP0_CH1SEL_M   0x000000F0
 
#define UDMA_CHMAP0_CH0SEL_M   0x0000000F
 
#define UDMA_CHMAP0_CH7SEL_S   28
 
#define UDMA_CHMAP0_CH6SEL_S   24
 
#define UDMA_CHMAP0_CH5SEL_S   20
 
#define UDMA_CHMAP0_CH4SEL_S   16
 
#define UDMA_CHMAP0_CH3SEL_S   12
 
#define UDMA_CHMAP0_CH2SEL_S   8
 
#define UDMA_CHMAP0_CH1SEL_S   4
 
#define UDMA_CHMAP0_CH0SEL_S   0
 
#define UDMA_CHMAP1_CH15SEL_M   0xF0000000
 
#define UDMA_CHMAP1_CH14SEL_M   0x0F000000
 
#define UDMA_CHMAP1_CH13SEL_M   0x00F00000
 
#define UDMA_CHMAP1_CH12SEL_M   0x000F0000
 
#define UDMA_CHMAP1_CH11SEL_M   0x0000F000
 
#define UDMA_CHMAP1_CH10SEL_M   0x00000F00
 
#define UDMA_CHMAP1_CH9SEL_M   0x000000F0
 
#define UDMA_CHMAP1_CH8SEL_M   0x0000000F
 
#define UDMA_CHMAP1_CH15SEL_S   28
 
#define UDMA_CHMAP1_CH14SEL_S   24
 
#define UDMA_CHMAP1_CH13SEL_S   20
 
#define UDMA_CHMAP1_CH12SEL_S   16
 
#define UDMA_CHMAP1_CH11SEL_S   12
 
#define UDMA_CHMAP1_CH10SEL_S   8
 
#define UDMA_CHMAP1_CH9SEL_S   4
 
#define UDMA_CHMAP1_CH8SEL_S   0
 
#define UDMA_CHMAP2_CH23SEL_M   0xF0000000
 
#define UDMA_CHMAP2_CH22SEL_M   0x0F000000
 
#define UDMA_CHMAP2_CH21SEL_M   0x00F00000
 
#define UDMA_CHMAP2_CH20SEL_M   0x000F0000
 
#define UDMA_CHMAP2_CH19SEL_M   0x0000F000
 
#define UDMA_CHMAP2_CH18SEL_M   0x00000F00
 
#define UDMA_CHMAP2_CH17SEL_M   0x000000F0
 
#define UDMA_CHMAP2_CH16SEL_M   0x0000000F
 
#define UDMA_CHMAP2_CH23SEL_S   28
 
#define UDMA_CHMAP2_CH22SEL_S   24
 
#define UDMA_CHMAP2_CH21SEL_S   20
 
#define UDMA_CHMAP2_CH20SEL_S   16
 
#define UDMA_CHMAP2_CH19SEL_S   12
 
#define UDMA_CHMAP2_CH18SEL_S   8
 
#define UDMA_CHMAP2_CH17SEL_S   4
 
#define UDMA_CHMAP2_CH16SEL_S   0
 
#define UDMA_CHMAP3_CH31SEL_M   0xF0000000
 
#define UDMA_CHMAP3_CH30SEL_M   0x0F000000
 
#define UDMA_CHMAP3_CH29SEL_M   0x00F00000
 
#define UDMA_CHMAP3_CH28SEL_M   0x000F0000
 
#define UDMA_CHMAP3_CH27SEL_M   0x0000F000
 
#define UDMA_CHMAP3_CH26SEL_M   0x00000F00
 
#define UDMA_CHMAP3_CH25SEL_M   0x000000F0
 
#define UDMA_CHMAP3_CH24SEL_M   0x0000000F
 
#define UDMA_CHMAP3_CH31SEL_S   28
 
#define UDMA_CHMAP3_CH30SEL_S   24
 
#define UDMA_CHMAP3_CH29SEL_S   20
 
#define UDMA_CHMAP3_CH28SEL_S   16
 
#define UDMA_CHMAP3_CH27SEL_S   12
 
#define UDMA_CHMAP3_CH26SEL_S   8
 
#define UDMA_CHMAP3_CH25SEL_S   4
 
#define UDMA_CHMAP3_CH24SEL_S   0
 
#define UDMA_SRCENDP_ADDR_M   0xFFFFFFFF
 
#define UDMA_SRCENDP_ADDR_S   0
 
#define UDMA_DSTENDP_ADDR_M   0xFFFFFFFF
 
#define UDMA_DSTENDP_ADDR_S   0
 
#define UDMA_CHCTL_DSTINC_M   0xC0000000
 
#define UDMA_CHCTL_DSTINC_8   0x00000000
 
#define UDMA_CHCTL_DSTINC_16   0x40000000
 
#define UDMA_CHCTL_DSTINC_32   0x80000000
 
#define UDMA_CHCTL_DSTINC_NONE   0xC0000000
 
#define UDMA_CHCTL_DSTSIZE_M   0x30000000
 
#define UDMA_CHCTL_DSTSIZE_8   0x00000000
 
#define UDMA_CHCTL_DSTSIZE_16   0x10000000
 
#define UDMA_CHCTL_DSTSIZE_32   0x20000000
 
#define UDMA_CHCTL_SRCINC_M   0x0C000000
 
#define UDMA_CHCTL_SRCINC_8   0x00000000
 
#define UDMA_CHCTL_SRCINC_16   0x04000000
 
#define UDMA_CHCTL_SRCINC_32   0x08000000
 
#define UDMA_CHCTL_SRCINC_NONE   0x0C000000
 
#define UDMA_CHCTL_SRCSIZE_M   0x03000000
 
#define UDMA_CHCTL_SRCSIZE_8   0x00000000
 
#define UDMA_CHCTL_SRCSIZE_16   0x01000000
 
#define UDMA_CHCTL_SRCSIZE_32   0x02000000
 
#define UDMA_CHCTL_ARBSIZE_M   0x0003C000
 
#define UDMA_CHCTL_ARBSIZE_1   0x00000000
 
#define UDMA_CHCTL_ARBSIZE_2   0x00004000
 
#define UDMA_CHCTL_ARBSIZE_4   0x00008000
 
#define UDMA_CHCTL_ARBSIZE_8   0x0000C000
 
#define UDMA_CHCTL_ARBSIZE_16   0x00010000
 
#define UDMA_CHCTL_ARBSIZE_32   0x00014000
 
#define UDMA_CHCTL_ARBSIZE_64   0x00018000
 
#define UDMA_CHCTL_ARBSIZE_128   0x0001C000
 
#define UDMA_CHCTL_ARBSIZE_256   0x00020000
 
#define UDMA_CHCTL_ARBSIZE_512   0x00024000
 
#define UDMA_CHCTL_ARBSIZE_1024   0x00028000
 
#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0
 
#define UDMA_CHCTL_NXTUSEBURST   0x00000008
 
#define UDMA_CHCTL_XFERMODE_M   0x00000007
 
#define UDMA_CHCTL_XFERMODE_STOP    0x00000000
 
#define UDMA_CHCTL_XFERMODE_BASIC    0x00000001
 
#define UDMA_CHCTL_XFERMODE_AUTO    0x00000002
 
#define UDMA_CHCTL_XFERMODE_PINGPONG    0x00000003
 
#define UDMA_CHCTL_XFERMODE_MEM_SG    0x00000004
 
#define UDMA_CHCTL_XFERMODE_MEM_SGA    0x00000005
 
#define UDMA_CHCTL_XFERMODE_PER_SG    0x00000006
 
#define UDMA_CHCTL_XFERMODE_PER_SGA    0x00000007
 
#define UDMA_CHCTL_XFERSIZE_S   4
 
#define NVIC_ACTLR_DISOOFP   0x00000200
 
#define NVIC_ACTLR_DISFPCA   0x00000100
 
#define NVIC_ACTLR_DISFOLD   0x00000004
 
#define NVIC_ACTLR_DISWBUF   0x00000002
 
#define NVIC_ACTLR_DISMCYC   0x00000001
 
#define NVIC_ST_CTRL_COUNT   0x00010000
 
#define NVIC_ST_CTRL_CLK_SRC   0x00000004
 
#define NVIC_ST_CTRL_INTEN   0x00000002
 
#define NVIC_ST_CTRL_ENABLE   0x00000001
 
#define NVIC_ST_RELOAD_M   0x00FFFFFF
 
#define NVIC_ST_RELOAD_S   0
 
#define NVIC_ST_CURRENT_M   0x00FFFFFF
 
#define NVIC_ST_CURRENT_S   0
 
#define NVIC_EN0_INT_M   0xFFFFFFFF
 
#define NVIC_EN1_INT_M   0xFFFFFFFF
 
#define NVIC_EN2_INT_M   0xFFFFFFFF
 
#define NVIC_EN3_INT_M   0xFFFFFFFF
 
#define NVIC_EN4_INT_M   0x000007FF
 
#define NVIC_DIS0_INT_M   0xFFFFFFFF
 
#define NVIC_DIS1_INT_M   0xFFFFFFFF
 
#define NVIC_DIS2_INT_M   0xFFFFFFFF
 
#define NVIC_DIS3_INT_M   0xFFFFFFFF
 
#define NVIC_DIS4_INT_M   0x000007FF
 
#define NVIC_PEND0_INT_M   0xFFFFFFFF
 
#define NVIC_PEND1_INT_M   0xFFFFFFFF
 
#define NVIC_PEND2_INT_M   0xFFFFFFFF
 
#define NVIC_PEND3_INT_M   0xFFFFFFFF
 
#define NVIC_PEND4_INT_M   0x000007FF
 
#define NVIC_UNPEND0_INT_M   0xFFFFFFFF
 
#define NVIC_UNPEND1_INT_M   0xFFFFFFFF
 
#define NVIC_UNPEND2_INT_M   0xFFFFFFFF
 
#define NVIC_UNPEND3_INT_M   0xFFFFFFFF
 
#define NVIC_UNPEND4_INT_M   0x000007FF
 
#define NVIC_ACTIVE0_INT_M   0xFFFFFFFF
 
#define NVIC_ACTIVE1_INT_M   0xFFFFFFFF
 
#define NVIC_ACTIVE2_INT_M   0xFFFFFFFF
 
#define NVIC_ACTIVE3_INT_M   0xFFFFFFFF
 
#define NVIC_ACTIVE4_INT_M   0x000007FF
 
#define NVIC_PRI0_INT3_M   0xE0000000
 
#define NVIC_PRI0_INT2_M   0x00E00000
 
#define NVIC_PRI0_INT1_M   0x0000E000
 
#define NVIC_PRI0_INT0_M   0x000000E0
 
#define NVIC_PRI0_INT3_S   29
 
#define NVIC_PRI0_INT2_S   21
 
#define NVIC_PRI0_INT1_S   13
 
#define NVIC_PRI0_INT0_S   5
 
#define NVIC_PRI1_INT7_M   0xE0000000
 
#define NVIC_PRI1_INT6_M   0x00E00000
 
#define NVIC_PRI1_INT5_M   0x0000E000
 
#define NVIC_PRI1_INT4_M   0x000000E0
 
#define NVIC_PRI1_INT7_S   29
 
#define NVIC_PRI1_INT6_S   21
 
#define NVIC_PRI1_INT5_S   13
 
#define NVIC_PRI1_INT4_S   5
 
#define NVIC_PRI2_INT11_M   0xE0000000
 
#define NVIC_PRI2_INT10_M   0x00E00000
 
#define NVIC_PRI2_INT9_M   0x0000E000
 
#define NVIC_PRI2_INT8_M   0x000000E0
 
#define NVIC_PRI2_INT11_S   29
 
#define NVIC_PRI2_INT10_S   21
 
#define NVIC_PRI2_INT9_S   13
 
#define NVIC_PRI2_INT8_S   5
 
#define NVIC_PRI3_INT15_M   0xE0000000
 
#define NVIC_PRI3_INT14_M   0x00E00000
 
#define NVIC_PRI3_INT13_M   0x0000E000
 
#define NVIC_PRI3_INT12_M   0x000000E0
 
#define NVIC_PRI3_INT15_S   29
 
#define NVIC_PRI3_INT14_S   21
 
#define NVIC_PRI3_INT13_S   13
 
#define NVIC_PRI3_INT12_S   5
 
#define NVIC_PRI4_INT19_M   0xE0000000
 
#define NVIC_PRI4_INT18_M   0x00E00000
 
#define NVIC_PRI4_INT17_M   0x0000E000
 
#define NVIC_PRI4_INT16_M   0x000000E0
 
#define NVIC_PRI4_INT19_S   29
 
#define NVIC_PRI4_INT18_S   21
 
#define NVIC_PRI4_INT17_S   13
 
#define NVIC_PRI4_INT16_S   5
 
#define NVIC_PRI5_INT23_M   0xE0000000
 
#define NVIC_PRI5_INT22_M   0x00E00000
 
#define NVIC_PRI5_INT21_M   0x0000E000
 
#define NVIC_PRI5_INT20_M   0x000000E0
 
#define NVIC_PRI5_INT23_S   29
 
#define NVIC_PRI5_INT22_S   21
 
#define NVIC_PRI5_INT21_S   13
 
#define NVIC_PRI5_INT20_S   5
 
#define NVIC_PRI6_INT27_M   0xE0000000
 
#define NVIC_PRI6_INT26_M   0x00E00000
 
#define NVIC_PRI6_INT25_M   0x0000E000
 
#define NVIC_PRI6_INT24_M   0x000000E0
 
#define NVIC_PRI6_INT27_S   29
 
#define NVIC_PRI6_INT26_S   21
 
#define NVIC_PRI6_INT25_S   13
 
#define NVIC_PRI6_INT24_S   5
 
#define NVIC_PRI7_INT31_M   0xE0000000
 
#define NVIC_PRI7_INT30_M   0x00E00000
 
#define NVIC_PRI7_INT29_M   0x0000E000
 
#define NVIC_PRI7_INT28_M   0x000000E0
 
#define NVIC_PRI7_INT31_S   29
 
#define NVIC_PRI7_INT30_S   21
 
#define NVIC_PRI7_INT29_S   13
 
#define NVIC_PRI7_INT28_S   5
 
#define NVIC_PRI8_INT35_M   0xE0000000
 
#define NVIC_PRI8_INT34_M   0x00E00000
 
#define NVIC_PRI8_INT33_M   0x0000E000
 
#define NVIC_PRI8_INT32_M   0x000000E0
 
#define NVIC_PRI8_INT35_S   29
 
#define NVIC_PRI8_INT34_S   21
 
#define NVIC_PRI8_INT33_S   13
 
#define NVIC_PRI8_INT32_S   5
 
#define NVIC_PRI9_INT39_M   0xE0000000
 
#define NVIC_PRI9_INT38_M   0x00E00000
 
#define NVIC_PRI9_INT37_M   0x0000E000
 
#define NVIC_PRI9_INT36_M   0x000000E0
 
#define NVIC_PRI9_INT39_S   29
 
#define NVIC_PRI9_INT38_S   21
 
#define NVIC_PRI9_INT37_S   13
 
#define NVIC_PRI9_INT36_S   5
 
#define NVIC_PRI10_INT43_M   0xE0000000
 
#define NVIC_PRI10_INT42_M   0x00E00000
 
#define NVIC_PRI10_INT41_M   0x0000E000
 
#define NVIC_PRI10_INT40_M   0x000000E0
 
#define NVIC_PRI10_INT43_S   29
 
#define NVIC_PRI10_INT42_S   21
 
#define NVIC_PRI10_INT41_S   13
 
#define NVIC_PRI10_INT40_S   5
 
#define NVIC_PRI11_INT47_M   0xE0000000
 
#define NVIC_PRI11_INT46_M   0x00E00000
 
#define NVIC_PRI11_INT45_M   0x0000E000
 
#define NVIC_PRI11_INT44_M   0x000000E0
 
#define NVIC_PRI11_INT47_S   29
 
#define NVIC_PRI11_INT46_S   21
 
#define NVIC_PRI11_INT45_S   13
 
#define NVIC_PRI11_INT44_S   5
 
#define NVIC_PRI12_INT51_M   0xE0000000
 
#define NVIC_PRI12_INT50_M   0x00E00000
 
#define NVIC_PRI12_INT49_M   0x0000E000
 
#define NVIC_PRI12_INT48_M   0x000000E0
 
#define NVIC_PRI12_INT51_S   29
 
#define NVIC_PRI12_INT50_S   21
 
#define NVIC_PRI12_INT49_S   13
 
#define NVIC_PRI12_INT48_S   5
 
#define NVIC_PRI13_INT55_M   0xE0000000
 
#define NVIC_PRI13_INT54_M   0x00E00000
 
#define NVIC_PRI13_INT53_M   0x0000E000
 
#define NVIC_PRI13_INT52_M   0x000000E0
 
#define NVIC_PRI13_INT55_S   29
 
#define NVIC_PRI13_INT54_S   21
 
#define NVIC_PRI13_INT53_S   13
 
#define NVIC_PRI13_INT52_S   5
 
#define NVIC_PRI14_INTD_M   0xE0000000
 
#define NVIC_PRI14_INTC_M   0x00E00000
 
#define NVIC_PRI14_INTB_M   0x0000E000
 
#define NVIC_PRI14_INTA_M   0x000000E0
 
#define NVIC_PRI14_INTD_S   29
 
#define NVIC_PRI14_INTC_S   21
 
#define NVIC_PRI14_INTB_S   13
 
#define NVIC_PRI14_INTA_S   5
 
#define NVIC_PRI15_INTD_M   0xE0000000
 
#define NVIC_PRI15_INTC_M   0x00E00000
 
#define NVIC_PRI15_INTB_M   0x0000E000
 
#define NVIC_PRI15_INTA_M   0x000000E0
 
#define NVIC_PRI15_INTD_S   29
 
#define NVIC_PRI15_INTC_S   21
 
#define NVIC_PRI15_INTB_S   13
 
#define NVIC_PRI15_INTA_S   5
 
#define NVIC_PRI16_INTD_M   0xE0000000
 
#define NVIC_PRI16_INTC_M   0x00E00000
 
#define NVIC_PRI16_INTB_M   0x0000E000
 
#define NVIC_PRI16_INTA_M   0x000000E0
 
#define NVIC_PRI16_INTD_S   29
 
#define NVIC_PRI16_INTC_S   21
 
#define NVIC_PRI16_INTB_S   13
 
#define NVIC_PRI16_INTA_S   5
 
#define NVIC_PRI17_INTD_M   0xE0000000
 
#define NVIC_PRI17_INTC_M   0x00E00000
 
#define NVIC_PRI17_INTB_M   0x0000E000
 
#define NVIC_PRI17_INTA_M   0x000000E0
 
#define NVIC_PRI17_INTD_S   29
 
#define NVIC_PRI17_INTC_S   21
 
#define NVIC_PRI17_INTB_S   13
 
#define NVIC_PRI17_INTA_S   5
 
#define NVIC_PRI18_INTD_M   0xE0000000
 
#define NVIC_PRI18_INTC_M   0x00E00000
 
#define NVIC_PRI18_INTB_M   0x0000E000
 
#define NVIC_PRI18_INTA_M   0x000000E0
 
#define NVIC_PRI18_INTD_S   29
 
#define NVIC_PRI18_INTC_S   21
 
#define NVIC_PRI18_INTB_S   13
 
#define NVIC_PRI18_INTA_S   5
 
#define NVIC_PRI19_INTD_M   0xE0000000
 
#define NVIC_PRI19_INTC_M   0x00E00000
 
#define NVIC_PRI19_INTB_M   0x0000E000
 
#define NVIC_PRI19_INTA_M   0x000000E0
 
#define NVIC_PRI19_INTD_S   29
 
#define NVIC_PRI19_INTC_S   21
 
#define NVIC_PRI19_INTB_S   13
 
#define NVIC_PRI19_INTA_S   5
 
#define NVIC_PRI20_INTD_M   0xE0000000
 
#define NVIC_PRI20_INTC_M   0x00E00000
 
#define NVIC_PRI20_INTB_M   0x0000E000
 
#define NVIC_PRI20_INTA_M   0x000000E0
 
#define NVIC_PRI20_INTD_S   29
 
#define NVIC_PRI20_INTC_S   21
 
#define NVIC_PRI20_INTB_S   13
 
#define NVIC_PRI20_INTA_S   5
 
#define NVIC_PRI21_INTD_M   0xE0000000
 
#define NVIC_PRI21_INTC_M   0x00E00000
 
#define NVIC_PRI21_INTB_M   0x0000E000
 
#define NVIC_PRI21_INTA_M   0x000000E0
 
#define NVIC_PRI21_INTD_S   29
 
#define NVIC_PRI21_INTC_S   21
 
#define NVIC_PRI21_INTB_S   13
 
#define NVIC_PRI21_INTA_S   5
 
#define NVIC_PRI22_INTD_M   0xE0000000
 
#define NVIC_PRI22_INTC_M   0x00E00000
 
#define NVIC_PRI22_INTB_M   0x0000E000
 
#define NVIC_PRI22_INTA_M   0x000000E0
 
#define NVIC_PRI22_INTD_S   29
 
#define NVIC_PRI22_INTC_S   21
 
#define NVIC_PRI22_INTB_S   13
 
#define NVIC_PRI22_INTA_S   5
 
#define NVIC_PRI23_INTD_M   0xE0000000
 
#define NVIC_PRI23_INTC_M   0x00E00000
 
#define NVIC_PRI23_INTB_M   0x0000E000
 
#define NVIC_PRI23_INTA_M   0x000000E0
 
#define NVIC_PRI23_INTD_S   29
 
#define NVIC_PRI23_INTC_S   21
 
#define NVIC_PRI23_INTB_S   13
 
#define NVIC_PRI23_INTA_S   5
 
#define NVIC_PRI24_INTD_M   0xE0000000
 
#define NVIC_PRI24_INTC_M   0x00E00000
 
#define NVIC_PRI24_INTB_M   0x0000E000
 
#define NVIC_PRI24_INTA_M   0x000000E0
 
#define NVIC_PRI24_INTD_S   29
 
#define NVIC_PRI24_INTC_S   21
 
#define NVIC_PRI24_INTB_S   13
 
#define NVIC_PRI24_INTA_S   5
 
#define NVIC_PRI25_INTD_M   0xE0000000
 
#define NVIC_PRI25_INTC_M   0x00E00000
 
#define NVIC_PRI25_INTB_M   0x0000E000
 
#define NVIC_PRI25_INTA_M   0x000000E0
 
#define NVIC_PRI25_INTD_S   29
 
#define NVIC_PRI25_INTC_S   21
 
#define NVIC_PRI25_INTB_S   13
 
#define NVIC_PRI25_INTA_S   5
 
#define NVIC_PRI26_INTD_M   0xE0000000
 
#define NVIC_PRI26_INTC_M   0x00E00000
 
#define NVIC_PRI26_INTB_M   0x0000E000
 
#define NVIC_PRI26_INTA_M   0x000000E0
 
#define NVIC_PRI26_INTD_S   29
 
#define NVIC_PRI26_INTC_S   21
 
#define NVIC_PRI26_INTB_S   13
 
#define NVIC_PRI26_INTA_S   5
 
#define NVIC_PRI27_INTD_M   0xE0000000
 
#define NVIC_PRI27_INTC_M   0x00E00000
 
#define NVIC_PRI27_INTB_M   0x0000E000
 
#define NVIC_PRI27_INTA_M   0x000000E0
 
#define NVIC_PRI27_INTD_S   29
 
#define NVIC_PRI27_INTC_S   21
 
#define NVIC_PRI27_INTB_S   13
 
#define NVIC_PRI27_INTA_S   5
 
#define NVIC_PRI28_INTD_M   0xE0000000
 
#define NVIC_PRI28_INTC_M   0x00E00000
 
#define NVIC_PRI28_INTB_M   0x0000E000
 
#define NVIC_PRI28_INTA_M   0x000000E0
 
#define NVIC_PRI28_INTD_S   29
 
#define NVIC_PRI28_INTC_S   21
 
#define NVIC_PRI28_INTB_S   13
 
#define NVIC_PRI28_INTA_S   5
 
#define NVIC_PRI29_INTD_M   0xE0000000
 
#define NVIC_PRI29_INTC_M   0x00E00000
 
#define NVIC_PRI29_INTB_M   0x0000E000
 
#define NVIC_PRI29_INTA_M   0x000000E0
 
#define NVIC_PRI29_INTD_S   29
 
#define NVIC_PRI29_INTC_S   21
 
#define NVIC_PRI29_INTB_S   13
 
#define NVIC_PRI29_INTA_S   5
 
#define NVIC_PRI30_INTD_M   0xE0000000
 
#define NVIC_PRI30_INTC_M   0x00E00000
 
#define NVIC_PRI30_INTB_M   0x0000E000
 
#define NVIC_PRI30_INTA_M   0x000000E0
 
#define NVIC_PRI30_INTD_S   29
 
#define NVIC_PRI30_INTC_S   21
 
#define NVIC_PRI30_INTB_S   13
 
#define NVIC_PRI30_INTA_S   5
 
#define NVIC_PRI31_INTD_M   0xE0000000
 
#define NVIC_PRI31_INTC_M   0x00E00000
 
#define NVIC_PRI31_INTB_M   0x0000E000
 
#define NVIC_PRI31_INTA_M   0x000000E0
 
#define NVIC_PRI31_INTD_S   29
 
#define NVIC_PRI31_INTC_S   21
 
#define NVIC_PRI31_INTB_S   13
 
#define NVIC_PRI31_INTA_S   5
 
#define NVIC_PRI32_INTD_M   0xE0000000
 
#define NVIC_PRI32_INTC_M   0x00E00000
 
#define NVIC_PRI32_INTB_M   0x0000E000
 
#define NVIC_PRI32_INTA_M   0x000000E0
 
#define NVIC_PRI32_INTD_S   29
 
#define NVIC_PRI32_INTC_S   21
 
#define NVIC_PRI32_INTB_S   13
 
#define NVIC_PRI32_INTA_S   5
 
#define NVIC_PRI33_INTD_M   0xE0000000
 
#define NVIC_PRI33_INTC_M   0x00E00000
 
#define NVIC_PRI33_INTB_M   0x0000E000
 
#define NVIC_PRI33_INTA_M   0x000000E0
 
#define NVIC_PRI33_INTD_S   29
 
#define NVIC_PRI33_INTC_S   21
 
#define NVIC_PRI33_INTB_S   13
 
#define NVIC_PRI33_INTA_S   5
 
#define NVIC_PRI34_INTD_M   0xE0000000
 
#define NVIC_PRI34_INTC_M   0x00E00000
 
#define NVIC_PRI34_INTB_M   0x0000E000
 
#define NVIC_PRI34_INTA_M   0x000000E0
 
#define NVIC_PRI34_INTD_S   29
 
#define NVIC_PRI34_INTC_S   21
 
#define NVIC_PRI34_INTB_S   13
 
#define NVIC_PRI34_INTA_S   5
 
#define NVIC_CPUID_IMP_M   0xFF000000
 
#define NVIC_CPUID_IMP_ARM   0x41000000
 
#define NVIC_CPUID_VAR_M   0x00F00000
 
#define NVIC_CPUID_CON_M   0x000F0000
 
#define NVIC_CPUID_PARTNO_M   0x0000FFF0
 
#define NVIC_CPUID_PARTNO_CM4   0x0000C240
 
#define NVIC_CPUID_REV_M   0x0000000F
 
#define NVIC_INT_CTRL_NMI_SET   0x80000000
 
#define NVIC_INT_CTRL_PEND_SV   0x10000000
 
#define NVIC_INT_CTRL_UNPEND_SV   0x08000000
 
#define NVIC_INT_CTRL_PENDSTSET   0x04000000
 
#define NVIC_INT_CTRL_PENDSTCLR   0x02000000
 
#define NVIC_INT_CTRL_ISR_PRE   0x00800000
 
#define NVIC_INT_CTRL_ISR_PEND   0x00400000
 
#define NVIC_INT_CTRL_VEC_PEN_M   0x000FF000
 
#define NVIC_INT_CTRL_VEC_PEN_NMI    0x00002000
 
#define NVIC_INT_CTRL_VEC_PEN_HARD    0x00003000
 
#define NVIC_INT_CTRL_VEC_PEN_MEM    0x00004000
 
#define NVIC_INT_CTRL_VEC_PEN_BUS    0x00005000
 
#define NVIC_INT_CTRL_VEC_PEN_USG    0x00006000
 
#define NVIC_INT_CTRL_VEC_PEN_SVC    0x0000B000
 
#define NVIC_INT_CTRL_VEC_PEN_PNDSV    0x0000E000
 
#define NVIC_INT_CTRL_VEC_PEN_TICK    0x0000F000
 
#define NVIC_INT_CTRL_RET_BASE   0x00000800
 
#define NVIC_INT_CTRL_VEC_ACT_M   0x000000FF
 
#define NVIC_INT_CTRL_VEC_ACT_S   0
 
#define NVIC_VTABLE_OFFSET_M   0xFFFFFC00
 
#define NVIC_VTABLE_OFFSET_S   10
 
#define NVIC_APINT_VECTKEY_M   0xFFFF0000
 
#define NVIC_APINT_VECTKEY   0x05FA0000
 
#define NVIC_APINT_ENDIANESS   0x00008000
 
#define NVIC_APINT_PRIGROUP_M   0x00000700
 
#define NVIC_APINT_PRIGROUP_7_1   0x00000000
 
#define NVIC_APINT_PRIGROUP_6_2   0x00000100
 
#define NVIC_APINT_PRIGROUP_5_3   0x00000200
 
#define NVIC_APINT_PRIGROUP_4_4   0x00000300
 
#define NVIC_APINT_PRIGROUP_3_5   0x00000400
 
#define NVIC_APINT_PRIGROUP_2_6   0x00000500
 
#define NVIC_APINT_PRIGROUP_1_7   0x00000600
 
#define NVIC_APINT_PRIGROUP_0_8   0x00000700
 
#define NVIC_APINT_SYSRESETREQ   0x00000004
 
#define NVIC_APINT_VECT_CLR_ACT   0x00000002
 
#define NVIC_APINT_VECT_RESET   0x00000001
 
#define NVIC_SYS_CTRL_SEVONPEND   0x00000010
 
#define NVIC_SYS_CTRL_SLEEPDEEP   0x00000004
 
#define NVIC_SYS_CTRL_SLEEPEXIT   0x00000002
 
#define NVIC_CFG_CTRL_STKALIGN   0x00000200
 
#define NVIC_CFG_CTRL_BFHFNMIGN   0x00000100
 
#define NVIC_CFG_CTRL_DIV0   0x00000010
 
#define NVIC_CFG_CTRL_UNALIGNED   0x00000008
 
#define NVIC_CFG_CTRL_MAIN_PEND   0x00000002
 
#define NVIC_CFG_CTRL_BASE_THR   0x00000001
 
#define NVIC_SYS_PRI1_USAGE_M   0x00E00000
 
#define NVIC_SYS_PRI1_BUS_M   0x0000E000
 
#define NVIC_SYS_PRI1_MEM_M   0x000000E0
 
#define NVIC_SYS_PRI1_USAGE_S   21
 
#define NVIC_SYS_PRI1_BUS_S   13
 
#define NVIC_SYS_PRI1_MEM_S   5
 
#define NVIC_SYS_PRI2_SVC_M   0xE0000000
 
#define NVIC_SYS_PRI2_SVC_S   29
 
#define NVIC_SYS_PRI3_TICK_M   0xE0000000
 
#define NVIC_SYS_PRI3_PENDSV_M   0x00E00000
 
#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0
 
#define NVIC_SYS_PRI3_TICK_S   29
 
#define NVIC_SYS_PRI3_PENDSV_S   21
 
#define NVIC_SYS_PRI3_DEBUG_S   5
 
#define NVIC_SYS_HND_CTRL_USAGE   0x00040000
 
#define NVIC_SYS_HND_CTRL_BUS   0x00020000
 
#define NVIC_SYS_HND_CTRL_MEM   0x00010000
 
#define NVIC_SYS_HND_CTRL_SVC   0x00008000
 
#define NVIC_SYS_HND_CTRL_BUSP   0x00004000
 
#define NVIC_SYS_HND_CTRL_MEMP   0x00002000
 
#define NVIC_SYS_HND_CTRL_USAGEP    0x00001000
 
#define NVIC_SYS_HND_CTRL_TICK   0x00000800
 
#define NVIC_SYS_HND_CTRL_PNDSV   0x00000400
 
#define NVIC_SYS_HND_CTRL_MON   0x00000100
 
#define NVIC_SYS_HND_CTRL_SVCA   0x00000080
 
#define NVIC_SYS_HND_CTRL_USGA   0x00000008
 
#define NVIC_SYS_HND_CTRL_BUSA   0x00000002
 
#define NVIC_SYS_HND_CTRL_MEMA   0x00000001
 
#define NVIC_FAULT_STAT_DIV0   0x02000000
 
#define NVIC_FAULT_STAT_UNALIGN   0x01000000
 
#define NVIC_FAULT_STAT_NOCP   0x00080000
 
#define NVIC_FAULT_STAT_INVPC   0x00040000
 
#define NVIC_FAULT_STAT_INVSTAT   0x00020000
 
#define NVIC_FAULT_STAT_UNDEF   0x00010000
 
#define NVIC_FAULT_STAT_BFARV   0x00008000
 
#define NVIC_FAULT_STAT_BLSPERR   0x00002000
 
#define NVIC_FAULT_STAT_BSTKE   0x00001000
 
#define NVIC_FAULT_STAT_BUSTKE   0x00000800
 
#define NVIC_FAULT_STAT_IMPRE   0x00000400
 
#define NVIC_FAULT_STAT_PRECISE   0x00000200
 
#define NVIC_FAULT_STAT_IBUS   0x00000100
 
#define NVIC_FAULT_STAT_MMARV   0x00000080
 
#define NVIC_FAULT_STAT_MLSPERR   0x00000020
 
#define NVIC_FAULT_STAT_MSTKE   0x00000010
 
#define NVIC_FAULT_STAT_MUSTKE   0x00000008
 
#define NVIC_FAULT_STAT_DERR   0x00000002
 
#define NVIC_FAULT_STAT_IERR   0x00000001
 
#define NVIC_HFAULT_STAT_DBG   0x80000000
 
#define NVIC_HFAULT_STAT_FORCED   0x40000000
 
#define NVIC_HFAULT_STAT_VECT   0x00000002
 
#define NVIC_DEBUG_STAT_EXTRNL   0x00000010
 
#define NVIC_DEBUG_STAT_VCATCH   0x00000008
 
#define NVIC_DEBUG_STAT_DWTTRAP   0x00000004
 
#define NVIC_DEBUG_STAT_BKPT   0x00000002
 
#define NVIC_DEBUG_STAT_HALTED   0x00000001
 
#define NVIC_MM_ADDR_M   0xFFFFFFFF
 
#define NVIC_MM_ADDR_S   0
 
#define NVIC_FAULT_ADDR_M   0xFFFFFFFF
 
#define NVIC_FAULT_ADDR_S   0
 
#define NVIC_CPAC_CP11_M   0x00C00000
 
#define NVIC_CPAC_CP11_DIS   0x00000000
 
#define NVIC_CPAC_CP11_PRIV   0x00400000
 
#define NVIC_CPAC_CP11_FULL   0x00C00000
 
#define NVIC_CPAC_CP10_M   0x00300000
 
#define NVIC_CPAC_CP10_DIS   0x00000000
 
#define NVIC_CPAC_CP10_PRIV   0x00100000
 
#define NVIC_CPAC_CP10_FULL   0x00300000
 
#define NVIC_MPU_TYPE_IREGION_M   0x00FF0000
 
#define NVIC_MPU_TYPE_DREGION_M   0x0000FF00
 
#define NVIC_MPU_TYPE_SEPARATE   0x00000001
 
#define NVIC_MPU_TYPE_IREGION_S   16
 
#define NVIC_MPU_TYPE_DREGION_S   8
 
#define NVIC_MPU_CTRL_PRIVDEFEN   0x00000004
 
#define NVIC_MPU_CTRL_HFNMIENA   0x00000002
 
#define NVIC_MPU_CTRL_ENABLE   0x00000001
 
#define NVIC_MPU_NUMBER_M   0x00000007
 
#define NVIC_MPU_NUMBER_S   0
 
#define NVIC_MPU_BASE_ADDR_M   0xFFFFFFE0
 
#define NVIC_MPU_BASE_VALID   0x00000010
 
#define NVIC_MPU_BASE_REGION_M   0x00000007
 
#define NVIC_MPU_BASE_ADDR_S   5
 
#define NVIC_MPU_BASE_REGION_S   0
 
#define NVIC_MPU_ATTR_XN   0x10000000
 
#define NVIC_MPU_ATTR_AP_M   0x07000000
 
#define NVIC_MPU_ATTR_TEX_M   0x00380000
 
#define NVIC_MPU_ATTR_SHAREABLE   0x00040000
 
#define NVIC_MPU_ATTR_CACHEABLE   0x00020000
 
#define NVIC_MPU_ATTR_BUFFRABLE   0x00010000
 
#define NVIC_MPU_ATTR_SRD_M   0x0000FF00
 
#define NVIC_MPU_ATTR_SIZE_M   0x0000003E
 
#define NVIC_MPU_ATTR_ENABLE   0x00000001
 
#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0
 
#define NVIC_MPU_BASE1_VALID   0x00000010
 
#define NVIC_MPU_BASE1_REGION_M   0x00000007
 
#define NVIC_MPU_BASE1_ADDR_S   5
 
#define NVIC_MPU_BASE1_REGION_S   0
 
#define NVIC_MPU_ATTR1_XN   0x10000000
 
#define NVIC_MPU_ATTR1_AP_M   0x07000000
 
#define NVIC_MPU_ATTR1_TEX_M   0x00380000
 
#define NVIC_MPU_ATTR1_SHAREABLE    0x00040000
 
#define NVIC_MPU_ATTR1_CACHEABLE    0x00020000
 
#define NVIC_MPU_ATTR1_BUFFRABLE    0x00010000
 
#define NVIC_MPU_ATTR1_SRD_M   0x0000FF00
 
#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E
 
#define NVIC_MPU_ATTR1_ENABLE   0x00000001
 
#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0
 
#define NVIC_MPU_BASE2_VALID   0x00000010
 
#define NVIC_MPU_BASE2_REGION_M   0x00000007
 
#define NVIC_MPU_BASE2_ADDR_S   5
 
#define NVIC_MPU_BASE2_REGION_S   0
 
#define NVIC_MPU_ATTR2_XN   0x10000000
 
#define NVIC_MPU_ATTR2_AP_M   0x07000000
 
#define NVIC_MPU_ATTR2_TEX_M   0x00380000
 
#define NVIC_MPU_ATTR2_SHAREABLE    0x00040000
 
#define NVIC_MPU_ATTR2_CACHEABLE    0x00020000
 
#define NVIC_MPU_ATTR2_BUFFRABLE    0x00010000
 
#define NVIC_MPU_ATTR2_SRD_M   0x0000FF00
 
#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E
 
#define NVIC_MPU_ATTR2_ENABLE   0x00000001
 
#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0
 
#define NVIC_MPU_BASE3_VALID   0x00000010
 
#define NVIC_MPU_BASE3_REGION_M   0x00000007
 
#define NVIC_MPU_BASE3_ADDR_S   5
 
#define NVIC_MPU_BASE3_REGION_S   0
 
#define NVIC_MPU_ATTR3_XN   0x10000000
 
#define NVIC_MPU_ATTR3_AP_M   0x07000000
 
#define NVIC_MPU_ATTR3_TEX_M   0x00380000
 
#define NVIC_MPU_ATTR3_SHAREABLE    0x00040000
 
#define NVIC_MPU_ATTR3_CACHEABLE    0x00020000
 
#define NVIC_MPU_ATTR3_BUFFRABLE    0x00010000
 
#define NVIC_MPU_ATTR3_SRD_M   0x0000FF00
 
#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E
 
#define NVIC_MPU_ATTR3_ENABLE   0x00000001
 
#define NVIC_DBG_CTRL_DBGKEY_M   0xFFFF0000
 
#define NVIC_DBG_CTRL_DBGKEY   0xA05F0000
 
#define NVIC_DBG_CTRL_S_RESET_ST    0x02000000
 
#define NVIC_DBG_CTRL_S_RETIRE_ST    0x01000000
 
#define NVIC_DBG_CTRL_S_LOCKUP   0x00080000
 
#define NVIC_DBG_CTRL_S_SLEEP   0x00040000
 
#define NVIC_DBG_CTRL_S_HALT   0x00020000
 
#define NVIC_DBG_CTRL_S_REGRDY   0x00010000
 
#define NVIC_DBG_CTRL_C_SNAPSTALL    0x00000020
 
#define NVIC_DBG_CTRL_C_MASKINT   0x00000008
 
#define NVIC_DBG_CTRL_C_STEP   0x00000004
 
#define NVIC_DBG_CTRL_C_HALT   0x00000002
 
#define NVIC_DBG_CTRL_C_DEBUGEN   0x00000001
 
#define NVIC_DBG_XFER_REG_WNR   0x00010000
 
#define NVIC_DBG_XFER_REG_SEL_M   0x0000001F
 
#define NVIC_DBG_XFER_REG_R0   0x00000000
 
#define NVIC_DBG_XFER_REG_R1   0x00000001
 
#define NVIC_DBG_XFER_REG_R2   0x00000002
 
#define NVIC_DBG_XFER_REG_R3   0x00000003
 
#define NVIC_DBG_XFER_REG_R4   0x00000004
 
#define NVIC_DBG_XFER_REG_R5   0x00000005
 
#define NVIC_DBG_XFER_REG_R6   0x00000006
 
#define NVIC_DBG_XFER_REG_R7   0x00000007
 
#define NVIC_DBG_XFER_REG_R8   0x00000008
 
#define NVIC_DBG_XFER_REG_R9   0x00000009
 
#define NVIC_DBG_XFER_REG_R10   0x0000000A
 
#define NVIC_DBG_XFER_REG_R11   0x0000000B
 
#define NVIC_DBG_XFER_REG_R12   0x0000000C
 
#define NVIC_DBG_XFER_REG_R13   0x0000000D
 
#define NVIC_DBG_XFER_REG_R14   0x0000000E
 
#define NVIC_DBG_XFER_REG_R15   0x0000000F
 
#define NVIC_DBG_XFER_REG_FLAGS   0x00000010
 
#define NVIC_DBG_XFER_REG_MSP   0x00000011
 
#define NVIC_DBG_XFER_REG_PSP   0x00000012
 
#define NVIC_DBG_XFER_REG_DSP   0x00000013
 
#define NVIC_DBG_XFER_REG_CFBP   0x00000014
 
#define NVIC_DBG_DATA_M   0xFFFFFFFF
 
#define NVIC_DBG_DATA_S   0
 
#define NVIC_DBG_INT_HARDERR   0x00000400
 
#define NVIC_DBG_INT_INTERR   0x00000200
 
#define NVIC_DBG_INT_BUSERR   0x00000100
 
#define NVIC_DBG_INT_STATERR   0x00000080
 
#define NVIC_DBG_INT_CHKERR   0x00000040
 
#define NVIC_DBG_INT_NOCPERR   0x00000020
 
#define NVIC_DBG_INT_MMERR   0x00000010
 
#define NVIC_DBG_INT_RESET   0x00000008
 
#define NVIC_DBG_INT_RSTPENDCLR   0x00000004
 
#define NVIC_DBG_INT_RSTPENDING   0x00000002
 
#define NVIC_DBG_INT_RSTVCATCH   0x00000001
 
#define NVIC_SW_TRIG_INTID_M   0x000000FF
 
#define NVIC_SW_TRIG_INTID_S   0
 
#define NVIC_FPCC_ASPEN   0x80000000
 
#define NVIC_FPCC_LSPEN   0x40000000
 
#define NVIC_FPCC_MONRDY   0x00000100
 
#define NVIC_FPCC_BFRDY   0x00000040
 
#define NVIC_FPCC_MMRDY   0x00000020
 
#define NVIC_FPCC_HFRDY   0x00000010
 
#define NVIC_FPCC_THREAD   0x00000008
 
#define NVIC_FPCC_USER   0x00000002
 
#define NVIC_FPCC_LSPACT   0x00000001
 
#define NVIC_FPCA_ADDRESS_M   0xFFFFFFF8
 
#define NVIC_FPCA_ADDRESS_S   3
 
#define NVIC_FPDSC_AHP   0x04000000
 
#define NVIC_FPDSC_DN   0x02000000
 
#define NVIC_FPDSC_FZ   0x01000000
 
#define NVIC_FPDSC_RMODE_M   0x00C00000
 
#define NVIC_FPDSC_RMODE_RN   0x00000000
 
#define NVIC_FPDSC_RMODE_RP   0x00400000
 
#define NVIC_FPDSC_RMODE_RM   0x00800000
 
#define NVIC_FPDSC_RMODE_RZ   0x00C00000
 
#define SYSCTL_DID0_CLASS_BLIZZARD    0x00050000
 

Macro Definition Documentation

◆ ADC0_ACTSS_R

#define ADC0_ACTSS_R   (*((volatile u32 *)0x40038000))

◆ ADC0_CC_R

#define ADC0_CC_R   (*((volatile u32 *)0x40038FC8))

◆ ADC0_CTL_R

#define ADC0_CTL_R   (*((volatile u32 *)0x40038038))

◆ ADC0_DCCMP0_R

#define ADC0_DCCMP0_R   (*((volatile u32 *)0x40038E40))

◆ ADC0_DCCMP1_R

#define ADC0_DCCMP1_R   (*((volatile u32 *)0x40038E44))

◆ ADC0_DCCMP2_R

#define ADC0_DCCMP2_R   (*((volatile u32 *)0x40038E48))

◆ ADC0_DCCMP3_R

#define ADC0_DCCMP3_R   (*((volatile u32 *)0x40038E4C))

◆ ADC0_DCCMP4_R

#define ADC0_DCCMP4_R   (*((volatile u32 *)0x40038E50))

◆ ADC0_DCCMP5_R

#define ADC0_DCCMP5_R   (*((volatile u32 *)0x40038E54))

◆ ADC0_DCCMP6_R

#define ADC0_DCCMP6_R   (*((volatile u32 *)0x40038E58))

◆ ADC0_DCCMP7_R

#define ADC0_DCCMP7_R   (*((volatile u32 *)0x40038E5C))

◆ ADC0_DCCTL0_R

#define ADC0_DCCTL0_R   (*((volatile u32 *)0x40038E00))

◆ ADC0_DCCTL1_R

#define ADC0_DCCTL1_R   (*((volatile u32 *)0x40038E04))

◆ ADC0_DCCTL2_R

#define ADC0_DCCTL2_R   (*((volatile u32 *)0x40038E08))

◆ ADC0_DCCTL3_R

#define ADC0_DCCTL3_R   (*((volatile u32 *)0x40038E0C))

◆ ADC0_DCCTL4_R

#define ADC0_DCCTL4_R   (*((volatile u32 *)0x40038E10))

◆ ADC0_DCCTL5_R

#define ADC0_DCCTL5_R   (*((volatile u32 *)0x40038E14))

◆ ADC0_DCCTL6_R

#define ADC0_DCCTL6_R   (*((volatile u32 *)0x40038E18))

◆ ADC0_DCCTL7_R

#define ADC0_DCCTL7_R   (*((volatile u32 *)0x40038E1C))

◆ ADC0_DCISC_R

#define ADC0_DCISC_R   (*((volatile u32 *)0x40038034))

◆ ADC0_DCRIC_R

#define ADC0_DCRIC_R   (*((volatile u32 *)0x40038D00))

◆ ADC0_EMUX_R

#define ADC0_EMUX_R   (*((volatile u32 *)0x40038014))

◆ ADC0_IM_R

#define ADC0_IM_R   (*((volatile u32 *)0x40038008))

◆ ADC0_ISC_R

#define ADC0_ISC_R   (*((volatile u32 *)0x4003800C))

◆ ADC0_OSTAT_R

#define ADC0_OSTAT_R   (*((volatile u32 *)0x40038010))

◆ ADC0_PC_R

#define ADC0_PC_R   (*((volatile u32 *)0x40038FC4))

◆ ADC0_PP_R

#define ADC0_PP_R   (*((volatile u32 *)0x40038FC0))

◆ ADC0_PSSI_R

#define ADC0_PSSI_R   (*((volatile u32 *)0x40038028))

◆ ADC0_RIS_R

#define ADC0_RIS_R   (*((volatile u32 *)0x40038004))

◆ ADC0_SAC_R

#define ADC0_SAC_R   (*((volatile u32 *)0x40038030))

◆ ADC0_SPC_R

#define ADC0_SPC_R   (*((volatile u32 *)0x40038024))

◆ ADC0_SSCTL0_R

#define ADC0_SSCTL0_R   (*((volatile u32 *)0x40038044))

◆ ADC0_SSCTL1_R

#define ADC0_SSCTL1_R   (*((volatile u32 *)0x40038064))

◆ ADC0_SSCTL2_R

#define ADC0_SSCTL2_R   (*((volatile u32 *)0x40038084))

◆ ADC0_SSCTL3_R

#define ADC0_SSCTL3_R   (*((volatile u32 *)0x400380A4))

◆ ADC0_SSDC0_R

#define ADC0_SSDC0_R   (*((volatile u32 *)0x40038054))

◆ ADC0_SSDC1_R

#define ADC0_SSDC1_R   (*((volatile u32 *)0x40038074))

◆ ADC0_SSDC2_R

#define ADC0_SSDC2_R   (*((volatile u32 *)0x40038094))

◆ ADC0_SSDC3_R

#define ADC0_SSDC3_R   (*((volatile u32 *)0x400380B4))

◆ ADC0_SSFIFO0_R

#define ADC0_SSFIFO0_R   (*((volatile u32 *)0x40038048))

◆ ADC0_SSFIFO1_R

#define ADC0_SSFIFO1_R   (*((volatile u32 *)0x40038068))

◆ ADC0_SSFIFO2_R

#define ADC0_SSFIFO2_R   (*((volatile u32 *)0x40038088))

◆ ADC0_SSFIFO3_R

#define ADC0_SSFIFO3_R   (*((volatile u32 *)0x400380A8))

◆ ADC0_SSFSTAT0_R

#define ADC0_SSFSTAT0_R   (*((volatile u32 *)0x4003804C))

◆ ADC0_SSFSTAT1_R

#define ADC0_SSFSTAT1_R   (*((volatile u32 *)0x4003806C))

◆ ADC0_SSFSTAT2_R

#define ADC0_SSFSTAT2_R   (*((volatile u32 *)0x4003808C))

◆ ADC0_SSFSTAT3_R

#define ADC0_SSFSTAT3_R   (*((volatile u32 *)0x400380AC))

◆ ADC0_SSMUX0_R

#define ADC0_SSMUX0_R   (*((volatile u32 *)0x40038040))

◆ ADC0_SSMUX1_R

#define ADC0_SSMUX1_R   (*((volatile u32 *)0x40038060))

◆ ADC0_SSMUX2_R

#define ADC0_SSMUX2_R   (*((volatile u32 *)0x40038080))

◆ ADC0_SSMUX3_R

#define ADC0_SSMUX3_R   (*((volatile u32 *)0x400380A0))

◆ ADC0_SSOP0_R

#define ADC0_SSOP0_R   (*((volatile u32 *)0x40038050))

◆ ADC0_SSOP1_R

#define ADC0_SSOP1_R   (*((volatile u32 *)0x40038070))

◆ ADC0_SSOP2_R

#define ADC0_SSOP2_R   (*((volatile u32 *)0x40038090))

◆ ADC0_SSOP3_R

#define ADC0_SSOP3_R   (*((volatile u32 *)0x400380B0))

◆ ADC0_SSPRI_R

#define ADC0_SSPRI_R   (*((volatile u32 *)0x40038020))

◆ ADC0_TSSEL_R

#define ADC0_TSSEL_R   (*((volatile u32 *)0x4003801C))

◆ ADC0_USTAT_R

#define ADC0_USTAT_R   (*((volatile u32 *)0x40038018))

◆ ADC1_ACTSS_R

#define ADC1_ACTSS_R   (*((volatile u32 *)0x40039000))

◆ ADC1_CC_R

#define ADC1_CC_R   (*((volatile u32 *)0x40039FC8))

◆ ADC1_CTL_R

#define ADC1_CTL_R   (*((volatile u32 *)0x40039038))

◆ ADC1_DCCMP0_R

#define ADC1_DCCMP0_R   (*((volatile u32 *)0x40039E40))

◆ ADC1_DCCMP1_R

#define ADC1_DCCMP1_R   (*((volatile u32 *)0x40039E44))

◆ ADC1_DCCMP2_R

#define ADC1_DCCMP2_R   (*((volatile u32 *)0x40039E48))

◆ ADC1_DCCMP3_R

#define ADC1_DCCMP3_R   (*((volatile u32 *)0x40039E4C))

◆ ADC1_DCCMP4_R

#define ADC1_DCCMP4_R   (*((volatile u32 *)0x40039E50))

◆ ADC1_DCCMP5_R

#define ADC1_DCCMP5_R   (*((volatile u32 *)0x40039E54))

◆ ADC1_DCCMP6_R

#define ADC1_DCCMP6_R   (*((volatile u32 *)0x40039E58))

◆ ADC1_DCCMP7_R

#define ADC1_DCCMP7_R   (*((volatile u32 *)0x40039E5C))

◆ ADC1_DCCTL0_R

#define ADC1_DCCTL0_R   (*((volatile u32 *)0x40039E00))

◆ ADC1_DCCTL1_R

#define ADC1_DCCTL1_R   (*((volatile u32 *)0x40039E04))

◆ ADC1_DCCTL2_R

#define ADC1_DCCTL2_R   (*((volatile u32 *)0x40039E08))

◆ ADC1_DCCTL3_R

#define ADC1_DCCTL3_R   (*((volatile u32 *)0x40039E0C))

◆ ADC1_DCCTL4_R

#define ADC1_DCCTL4_R   (*((volatile u32 *)0x40039E10))

◆ ADC1_DCCTL5_R

#define ADC1_DCCTL5_R   (*((volatile u32 *)0x40039E14))

◆ ADC1_DCCTL6_R

#define ADC1_DCCTL6_R   (*((volatile u32 *)0x40039E18))

◆ ADC1_DCCTL7_R

#define ADC1_DCCTL7_R   (*((volatile u32 *)0x40039E1C))

◆ ADC1_DCISC_R

#define ADC1_DCISC_R   (*((volatile u32 *)0x40039034))

◆ ADC1_DCRIC_R

#define ADC1_DCRIC_R   (*((volatile u32 *)0x40039D00))

◆ ADC1_EMUX_R

#define ADC1_EMUX_R   (*((volatile u32 *)0x40039014))

◆ ADC1_IM_R

#define ADC1_IM_R   (*((volatile u32 *)0x40039008))

◆ ADC1_ISC_R

#define ADC1_ISC_R   (*((volatile u32 *)0x4003900C))

◆ ADC1_OSTAT_R

#define ADC1_OSTAT_R   (*((volatile u32 *)0x40039010))

◆ ADC1_PC_R

#define ADC1_PC_R   (*((volatile u32 *)0x40039FC4))

◆ ADC1_PP_R

#define ADC1_PP_R   (*((volatile u32 *)0x40039FC0))

◆ ADC1_PSSI_R

#define ADC1_PSSI_R   (*((volatile u32 *)0x40039028))

◆ ADC1_RIS_R

#define ADC1_RIS_R   (*((volatile u32 *)0x40039004))

◆ ADC1_SAC_R

#define ADC1_SAC_R   (*((volatile u32 *)0x40039030))

◆ ADC1_SPC_R

#define ADC1_SPC_R   (*((volatile u32 *)0x40039024))

◆ ADC1_SSCTL0_R

#define ADC1_SSCTL0_R   (*((volatile u32 *)0x40039044))

◆ ADC1_SSCTL1_R

#define ADC1_SSCTL1_R   (*((volatile u32 *)0x40039064))

◆ ADC1_SSCTL2_R

#define ADC1_SSCTL2_R   (*((volatile u32 *)0x40039084))

◆ ADC1_SSCTL3_R

#define ADC1_SSCTL3_R   (*((volatile u32 *)0x400390A4))

◆ ADC1_SSDC0_R

#define ADC1_SSDC0_R   (*((volatile u32 *)0x40039054))

◆ ADC1_SSDC1_R

#define ADC1_SSDC1_R   (*((volatile u32 *)0x40039074))

◆ ADC1_SSDC2_R

#define ADC1_SSDC2_R   (*((volatile u32 *)0x40039094))

◆ ADC1_SSDC3_R

#define ADC1_SSDC3_R   (*((volatile u32 *)0x400390B4))

◆ ADC1_SSFIFO0_R

#define ADC1_SSFIFO0_R   (*((volatile u32 *)0x40039048))

◆ ADC1_SSFIFO1_R

#define ADC1_SSFIFO1_R   (*((volatile u32 *)0x40039068))

◆ ADC1_SSFIFO2_R

#define ADC1_SSFIFO2_R   (*((volatile u32 *)0x40039088))

◆ ADC1_SSFIFO3_R

#define ADC1_SSFIFO3_R   (*((volatile u32 *)0x400390A8))

◆ ADC1_SSFSTAT0_R

#define ADC1_SSFSTAT0_R   (*((volatile u32 *)0x4003904C))

◆ ADC1_SSFSTAT1_R

#define ADC1_SSFSTAT1_R   (*((volatile u32 *)0x4003906C))

◆ ADC1_SSFSTAT2_R

#define ADC1_SSFSTAT2_R   (*((volatile u32 *)0x4003908C))

◆ ADC1_SSFSTAT3_R

#define ADC1_SSFSTAT3_R   (*((volatile u32 *)0x400390AC))

◆ ADC1_SSMUX0_R

#define ADC1_SSMUX0_R   (*((volatile u32 *)0x40039040))

◆ ADC1_SSMUX1_R

#define ADC1_SSMUX1_R   (*((volatile u32 *)0x40039060))

◆ ADC1_SSMUX2_R

#define ADC1_SSMUX2_R   (*((volatile u32 *)0x40039080))

◆ ADC1_SSMUX3_R

#define ADC1_SSMUX3_R   (*((volatile u32 *)0x400390A0))

◆ ADC1_SSOP0_R

#define ADC1_SSOP0_R   (*((volatile u32 *)0x40039050))

◆ ADC1_SSOP1_R

#define ADC1_SSOP1_R   (*((volatile u32 *)0x40039070))

◆ ADC1_SSOP2_R

#define ADC1_SSOP2_R   (*((volatile u32 *)0x40039090))

◆ ADC1_SSOP3_R

#define ADC1_SSOP3_R   (*((volatile u32 *)0x400390B0))

◆ ADC1_SSPRI_R

#define ADC1_SSPRI_R   (*((volatile u32 *)0x40039020))

◆ ADC1_TSSEL_R

#define ADC1_TSSEL_R   (*((volatile u32 *)0x4003901C))

◆ ADC1_USTAT_R

#define ADC1_USTAT_R   (*((volatile u32 *)0x40039018))

◆ ADC_ACTSS_ASEN0

#define ADC_ACTSS_ASEN0   0x00000001

◆ ADC_ACTSS_ASEN1

#define ADC_ACTSS_ASEN1   0x00000002

◆ ADC_ACTSS_ASEN2

#define ADC_ACTSS_ASEN2   0x00000004

◆ ADC_ACTSS_ASEN3

#define ADC_ACTSS_ASEN3   0x00000008

◆ ADC_ACTSS_BUSY

#define ADC_ACTSS_BUSY   0x00010000

◆ ADC_CC_CS_M

#define ADC_CC_CS_M   0x0000000F

◆ ADC_CC_CS_PIOSC

#define ADC_CC_CS_PIOSC   0x00000001

◆ ADC_CC_CS_SYSPLL

#define ADC_CC_CS_SYSPLL   0x00000000

◆ ADC_CTL_DITHER

#define ADC_CTL_DITHER   0x00000040

◆ ADC_CTL_VREF_INTERNAL

#define ADC_CTL_VREF_INTERNAL   0x00000000

◆ ADC_CTL_VREF_M

#define ADC_CTL_VREF_M   0x00000001

◆ ADC_DCCMP0_COMP0_M

#define ADC_DCCMP0_COMP0_M   0x00000FFF

◆ ADC_DCCMP0_COMP0_S

#define ADC_DCCMP0_COMP0_S   0

◆ ADC_DCCMP0_COMP1_M

#define ADC_DCCMP0_COMP1_M   0x0FFF0000

◆ ADC_DCCMP0_COMP1_S

#define ADC_DCCMP0_COMP1_S   16

◆ ADC_DCCMP1_COMP0_M

#define ADC_DCCMP1_COMP0_M   0x00000FFF

◆ ADC_DCCMP1_COMP0_S

#define ADC_DCCMP1_COMP0_S   0

◆ ADC_DCCMP1_COMP1_M

#define ADC_DCCMP1_COMP1_M   0x0FFF0000

◆ ADC_DCCMP1_COMP1_S

#define ADC_DCCMP1_COMP1_S   16

◆ ADC_DCCMP2_COMP0_M

#define ADC_DCCMP2_COMP0_M   0x00000FFF

◆ ADC_DCCMP2_COMP0_S

#define ADC_DCCMP2_COMP0_S   0

◆ ADC_DCCMP2_COMP1_M

#define ADC_DCCMP2_COMP1_M   0x0FFF0000

◆ ADC_DCCMP2_COMP1_S

#define ADC_DCCMP2_COMP1_S   16

◆ ADC_DCCMP3_COMP0_M

#define ADC_DCCMP3_COMP0_M   0x00000FFF

◆ ADC_DCCMP3_COMP0_S

#define ADC_DCCMP3_COMP0_S   0

◆ ADC_DCCMP3_COMP1_M

#define ADC_DCCMP3_COMP1_M   0x0FFF0000

◆ ADC_DCCMP3_COMP1_S

#define ADC_DCCMP3_COMP1_S   16

◆ ADC_DCCMP4_COMP0_M

#define ADC_DCCMP4_COMP0_M   0x00000FFF

◆ ADC_DCCMP4_COMP0_S

#define ADC_DCCMP4_COMP0_S   0

◆ ADC_DCCMP4_COMP1_M

#define ADC_DCCMP4_COMP1_M   0x0FFF0000

◆ ADC_DCCMP4_COMP1_S

#define ADC_DCCMP4_COMP1_S   16

◆ ADC_DCCMP5_COMP0_M

#define ADC_DCCMP5_COMP0_M   0x00000FFF

◆ ADC_DCCMP5_COMP0_S

#define ADC_DCCMP5_COMP0_S   0

◆ ADC_DCCMP5_COMP1_M

#define ADC_DCCMP5_COMP1_M   0x0FFF0000

◆ ADC_DCCMP5_COMP1_S

#define ADC_DCCMP5_COMP1_S   16

◆ ADC_DCCMP6_COMP0_M

#define ADC_DCCMP6_COMP0_M   0x00000FFF

◆ ADC_DCCMP6_COMP0_S

#define ADC_DCCMP6_COMP0_S   0

◆ ADC_DCCMP6_COMP1_M

#define ADC_DCCMP6_COMP1_M   0x0FFF0000

◆ ADC_DCCMP6_COMP1_S

#define ADC_DCCMP6_COMP1_S   16

◆ ADC_DCCMP7_COMP0_M

#define ADC_DCCMP7_COMP0_M   0x00000FFF

◆ ADC_DCCMP7_COMP0_S

#define ADC_DCCMP7_COMP0_S   0

◆ ADC_DCCMP7_COMP1_M

#define ADC_DCCMP7_COMP1_M   0x0FFF0000

◆ ADC_DCCMP7_COMP1_S

#define ADC_DCCMP7_COMP1_S   16

◆ ADC_DCCTL0_CIC_HIGH

#define ADC_DCCTL0_CIC_HIGH   0x0000000C

◆ ADC_DCCTL0_CIC_LOW

#define ADC_DCCTL0_CIC_LOW   0x00000000

◆ ADC_DCCTL0_CIC_M

#define ADC_DCCTL0_CIC_M   0x0000000C

◆ ADC_DCCTL0_CIC_MID

#define ADC_DCCTL0_CIC_MID   0x00000004

◆ ADC_DCCTL0_CIE

#define ADC_DCCTL0_CIE   0x00000010

◆ ADC_DCCTL0_CIM_ALWAYS

#define ADC_DCCTL0_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL0_CIM_HALWAYS

#define ADC_DCCTL0_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL0_CIM_HONCE

#define ADC_DCCTL0_CIM_HONCE   0x00000003

◆ ADC_DCCTL0_CIM_M

#define ADC_DCCTL0_CIM_M   0x00000003

◆ ADC_DCCTL0_CIM_ONCE

#define ADC_DCCTL0_CIM_ONCE   0x00000001

◆ ADC_DCCTL0_CTC_HIGH

#define ADC_DCCTL0_CTC_HIGH   0x00000C00

◆ ADC_DCCTL0_CTC_LOW

#define ADC_DCCTL0_CTC_LOW   0x00000000

◆ ADC_DCCTL0_CTC_M

#define ADC_DCCTL0_CTC_M   0x00000C00

◆ ADC_DCCTL0_CTC_MID

#define ADC_DCCTL0_CTC_MID   0x00000400

◆ ADC_DCCTL0_CTE

#define ADC_DCCTL0_CTE   0x00001000

◆ ADC_DCCTL0_CTM_ALWAYS

#define ADC_DCCTL0_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL0_CTM_HALWAYS

#define ADC_DCCTL0_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL0_CTM_HONCE

#define ADC_DCCTL0_CTM_HONCE   0x00000300

◆ ADC_DCCTL0_CTM_M

#define ADC_DCCTL0_CTM_M   0x00000300

◆ ADC_DCCTL0_CTM_ONCE

#define ADC_DCCTL0_CTM_ONCE   0x00000100

◆ ADC_DCCTL1_CIC_HIGH

#define ADC_DCCTL1_CIC_HIGH   0x0000000C

◆ ADC_DCCTL1_CIC_LOW

#define ADC_DCCTL1_CIC_LOW   0x00000000

◆ ADC_DCCTL1_CIC_M

#define ADC_DCCTL1_CIC_M   0x0000000C

◆ ADC_DCCTL1_CIC_MID

#define ADC_DCCTL1_CIC_MID   0x00000004

◆ ADC_DCCTL1_CIE

#define ADC_DCCTL1_CIE   0x00000010

◆ ADC_DCCTL1_CIM_ALWAYS

#define ADC_DCCTL1_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL1_CIM_HALWAYS

#define ADC_DCCTL1_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL1_CIM_HONCE

#define ADC_DCCTL1_CIM_HONCE   0x00000003

◆ ADC_DCCTL1_CIM_M

#define ADC_DCCTL1_CIM_M   0x00000003

◆ ADC_DCCTL1_CIM_ONCE

#define ADC_DCCTL1_CIM_ONCE   0x00000001

◆ ADC_DCCTL1_CTC_HIGH

#define ADC_DCCTL1_CTC_HIGH   0x00000C00

◆ ADC_DCCTL1_CTC_LOW

#define ADC_DCCTL1_CTC_LOW   0x00000000

◆ ADC_DCCTL1_CTC_M

#define ADC_DCCTL1_CTC_M   0x00000C00

◆ ADC_DCCTL1_CTC_MID

#define ADC_DCCTL1_CTC_MID   0x00000400

◆ ADC_DCCTL1_CTE

#define ADC_DCCTL1_CTE   0x00001000

◆ ADC_DCCTL1_CTM_ALWAYS

#define ADC_DCCTL1_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL1_CTM_HALWAYS

#define ADC_DCCTL1_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL1_CTM_HONCE

#define ADC_DCCTL1_CTM_HONCE   0x00000300

◆ ADC_DCCTL1_CTM_M

#define ADC_DCCTL1_CTM_M   0x00000300

◆ ADC_DCCTL1_CTM_ONCE

#define ADC_DCCTL1_CTM_ONCE   0x00000100

◆ ADC_DCCTL2_CIC_HIGH

#define ADC_DCCTL2_CIC_HIGH   0x0000000C

◆ ADC_DCCTL2_CIC_LOW

#define ADC_DCCTL2_CIC_LOW   0x00000000

◆ ADC_DCCTL2_CIC_M

#define ADC_DCCTL2_CIC_M   0x0000000C

◆ ADC_DCCTL2_CIC_MID

#define ADC_DCCTL2_CIC_MID   0x00000004

◆ ADC_DCCTL2_CIE

#define ADC_DCCTL2_CIE   0x00000010

◆ ADC_DCCTL2_CIM_ALWAYS

#define ADC_DCCTL2_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL2_CIM_HALWAYS

#define ADC_DCCTL2_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL2_CIM_HONCE

#define ADC_DCCTL2_CIM_HONCE   0x00000003

◆ ADC_DCCTL2_CIM_M

#define ADC_DCCTL2_CIM_M   0x00000003

◆ ADC_DCCTL2_CIM_ONCE

#define ADC_DCCTL2_CIM_ONCE   0x00000001

◆ ADC_DCCTL2_CTC_HIGH

#define ADC_DCCTL2_CTC_HIGH   0x00000C00

◆ ADC_DCCTL2_CTC_LOW

#define ADC_DCCTL2_CTC_LOW   0x00000000

◆ ADC_DCCTL2_CTC_M

#define ADC_DCCTL2_CTC_M   0x00000C00

◆ ADC_DCCTL2_CTC_MID

#define ADC_DCCTL2_CTC_MID   0x00000400

◆ ADC_DCCTL2_CTE

#define ADC_DCCTL2_CTE   0x00001000

◆ ADC_DCCTL2_CTM_ALWAYS

#define ADC_DCCTL2_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL2_CTM_HALWAYS

#define ADC_DCCTL2_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL2_CTM_HONCE

#define ADC_DCCTL2_CTM_HONCE   0x00000300

◆ ADC_DCCTL2_CTM_M

#define ADC_DCCTL2_CTM_M   0x00000300

◆ ADC_DCCTL2_CTM_ONCE

#define ADC_DCCTL2_CTM_ONCE   0x00000100

◆ ADC_DCCTL3_CIC_HIGH

#define ADC_DCCTL3_CIC_HIGH   0x0000000C

◆ ADC_DCCTL3_CIC_LOW

#define ADC_DCCTL3_CIC_LOW   0x00000000

◆ ADC_DCCTL3_CIC_M

#define ADC_DCCTL3_CIC_M   0x0000000C

◆ ADC_DCCTL3_CIC_MID

#define ADC_DCCTL3_CIC_MID   0x00000004

◆ ADC_DCCTL3_CIE

#define ADC_DCCTL3_CIE   0x00000010

◆ ADC_DCCTL3_CIM_ALWAYS

#define ADC_DCCTL3_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL3_CIM_HALWAYS

#define ADC_DCCTL3_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL3_CIM_HONCE

#define ADC_DCCTL3_CIM_HONCE   0x00000003

◆ ADC_DCCTL3_CIM_M

#define ADC_DCCTL3_CIM_M   0x00000003

◆ ADC_DCCTL3_CIM_ONCE

#define ADC_DCCTL3_CIM_ONCE   0x00000001

◆ ADC_DCCTL3_CTC_HIGH

#define ADC_DCCTL3_CTC_HIGH   0x00000C00

◆ ADC_DCCTL3_CTC_LOW

#define ADC_DCCTL3_CTC_LOW   0x00000000

◆ ADC_DCCTL3_CTC_M

#define ADC_DCCTL3_CTC_M   0x00000C00

◆ ADC_DCCTL3_CTC_MID

#define ADC_DCCTL3_CTC_MID   0x00000400

◆ ADC_DCCTL3_CTE

#define ADC_DCCTL3_CTE   0x00001000

◆ ADC_DCCTL3_CTM_ALWAYS

#define ADC_DCCTL3_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL3_CTM_HALWAYS

#define ADC_DCCTL3_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL3_CTM_HONCE

#define ADC_DCCTL3_CTM_HONCE   0x00000300

◆ ADC_DCCTL3_CTM_M

#define ADC_DCCTL3_CTM_M   0x00000300

◆ ADC_DCCTL3_CTM_ONCE

#define ADC_DCCTL3_CTM_ONCE   0x00000100

◆ ADC_DCCTL4_CIC_HIGH

#define ADC_DCCTL4_CIC_HIGH   0x0000000C

◆ ADC_DCCTL4_CIC_LOW

#define ADC_DCCTL4_CIC_LOW   0x00000000

◆ ADC_DCCTL4_CIC_M

#define ADC_DCCTL4_CIC_M   0x0000000C

◆ ADC_DCCTL4_CIC_MID

#define ADC_DCCTL4_CIC_MID   0x00000004

◆ ADC_DCCTL4_CIE

#define ADC_DCCTL4_CIE   0x00000010

◆ ADC_DCCTL4_CIM_ALWAYS

#define ADC_DCCTL4_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL4_CIM_HALWAYS

#define ADC_DCCTL4_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL4_CIM_HONCE

#define ADC_DCCTL4_CIM_HONCE   0x00000003

◆ ADC_DCCTL4_CIM_M

#define ADC_DCCTL4_CIM_M   0x00000003

◆ ADC_DCCTL4_CIM_ONCE

#define ADC_DCCTL4_CIM_ONCE   0x00000001

◆ ADC_DCCTL4_CTC_HIGH

#define ADC_DCCTL4_CTC_HIGH   0x00000C00

◆ ADC_DCCTL4_CTC_LOW

#define ADC_DCCTL4_CTC_LOW   0x00000000

◆ ADC_DCCTL4_CTC_M

#define ADC_DCCTL4_CTC_M   0x00000C00

◆ ADC_DCCTL4_CTC_MID

#define ADC_DCCTL4_CTC_MID   0x00000400

◆ ADC_DCCTL4_CTE

#define ADC_DCCTL4_CTE   0x00001000

◆ ADC_DCCTL4_CTM_ALWAYS

#define ADC_DCCTL4_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL4_CTM_HALWAYS

#define ADC_DCCTL4_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL4_CTM_HONCE

#define ADC_DCCTL4_CTM_HONCE   0x00000300

◆ ADC_DCCTL4_CTM_M

#define ADC_DCCTL4_CTM_M   0x00000300

◆ ADC_DCCTL4_CTM_ONCE

#define ADC_DCCTL4_CTM_ONCE   0x00000100

◆ ADC_DCCTL5_CIC_HIGH

#define ADC_DCCTL5_CIC_HIGH   0x0000000C

◆ ADC_DCCTL5_CIC_LOW

#define ADC_DCCTL5_CIC_LOW   0x00000000

◆ ADC_DCCTL5_CIC_M

#define ADC_DCCTL5_CIC_M   0x0000000C

◆ ADC_DCCTL5_CIC_MID

#define ADC_DCCTL5_CIC_MID   0x00000004

◆ ADC_DCCTL5_CIE

#define ADC_DCCTL5_CIE   0x00000010

◆ ADC_DCCTL5_CIM_ALWAYS

#define ADC_DCCTL5_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL5_CIM_HALWAYS

#define ADC_DCCTL5_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL5_CIM_HONCE

#define ADC_DCCTL5_CIM_HONCE   0x00000003

◆ ADC_DCCTL5_CIM_M

#define ADC_DCCTL5_CIM_M   0x00000003

◆ ADC_DCCTL5_CIM_ONCE

#define ADC_DCCTL5_CIM_ONCE   0x00000001

◆ ADC_DCCTL5_CTC_HIGH

#define ADC_DCCTL5_CTC_HIGH   0x00000C00

◆ ADC_DCCTL5_CTC_LOW

#define ADC_DCCTL5_CTC_LOW   0x00000000

◆ ADC_DCCTL5_CTC_M

#define ADC_DCCTL5_CTC_M   0x00000C00

◆ ADC_DCCTL5_CTC_MID

#define ADC_DCCTL5_CTC_MID   0x00000400

◆ ADC_DCCTL5_CTE

#define ADC_DCCTL5_CTE   0x00001000

◆ ADC_DCCTL5_CTM_ALWAYS

#define ADC_DCCTL5_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL5_CTM_HALWAYS

#define ADC_DCCTL5_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL5_CTM_HONCE

#define ADC_DCCTL5_CTM_HONCE   0x00000300

◆ ADC_DCCTL5_CTM_M

#define ADC_DCCTL5_CTM_M   0x00000300

◆ ADC_DCCTL5_CTM_ONCE

#define ADC_DCCTL5_CTM_ONCE   0x00000100

◆ ADC_DCCTL6_CIC_HIGH

#define ADC_DCCTL6_CIC_HIGH   0x0000000C

◆ ADC_DCCTL6_CIC_LOW

#define ADC_DCCTL6_CIC_LOW   0x00000000

◆ ADC_DCCTL6_CIC_M

#define ADC_DCCTL6_CIC_M   0x0000000C

◆ ADC_DCCTL6_CIC_MID

#define ADC_DCCTL6_CIC_MID   0x00000004

◆ ADC_DCCTL6_CIE

#define ADC_DCCTL6_CIE   0x00000010

◆ ADC_DCCTL6_CIM_ALWAYS

#define ADC_DCCTL6_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL6_CIM_HALWAYS

#define ADC_DCCTL6_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL6_CIM_HONCE

#define ADC_DCCTL6_CIM_HONCE   0x00000003

◆ ADC_DCCTL6_CIM_M

#define ADC_DCCTL6_CIM_M   0x00000003

◆ ADC_DCCTL6_CIM_ONCE

#define ADC_DCCTL6_CIM_ONCE   0x00000001

◆ ADC_DCCTL6_CTC_HIGH

#define ADC_DCCTL6_CTC_HIGH   0x00000C00

◆ ADC_DCCTL6_CTC_LOW

#define ADC_DCCTL6_CTC_LOW   0x00000000

◆ ADC_DCCTL6_CTC_M

#define ADC_DCCTL6_CTC_M   0x00000C00

◆ ADC_DCCTL6_CTC_MID

#define ADC_DCCTL6_CTC_MID   0x00000400

◆ ADC_DCCTL6_CTE

#define ADC_DCCTL6_CTE   0x00001000

◆ ADC_DCCTL6_CTM_ALWAYS

#define ADC_DCCTL6_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL6_CTM_HALWAYS

#define ADC_DCCTL6_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL6_CTM_HONCE

#define ADC_DCCTL6_CTM_HONCE   0x00000300

◆ ADC_DCCTL6_CTM_M

#define ADC_DCCTL6_CTM_M   0x00000300

◆ ADC_DCCTL6_CTM_ONCE

#define ADC_DCCTL6_CTM_ONCE   0x00000100

◆ ADC_DCCTL7_CIC_HIGH

#define ADC_DCCTL7_CIC_HIGH   0x0000000C

◆ ADC_DCCTL7_CIC_LOW

#define ADC_DCCTL7_CIC_LOW   0x00000000

◆ ADC_DCCTL7_CIC_M

#define ADC_DCCTL7_CIC_M   0x0000000C

◆ ADC_DCCTL7_CIC_MID

#define ADC_DCCTL7_CIC_MID   0x00000004

◆ ADC_DCCTL7_CIE

#define ADC_DCCTL7_CIE   0x00000010

◆ ADC_DCCTL7_CIM_ALWAYS

#define ADC_DCCTL7_CIM_ALWAYS   0x00000000

◆ ADC_DCCTL7_CIM_HALWAYS

#define ADC_DCCTL7_CIM_HALWAYS   0x00000002

◆ ADC_DCCTL7_CIM_HONCE

#define ADC_DCCTL7_CIM_HONCE   0x00000003

◆ ADC_DCCTL7_CIM_M

#define ADC_DCCTL7_CIM_M   0x00000003

◆ ADC_DCCTL7_CIM_ONCE

#define ADC_DCCTL7_CIM_ONCE   0x00000001

◆ ADC_DCCTL7_CTC_HIGH

#define ADC_DCCTL7_CTC_HIGH   0x00000C00

◆ ADC_DCCTL7_CTC_LOW

#define ADC_DCCTL7_CTC_LOW   0x00000000

◆ ADC_DCCTL7_CTC_M

#define ADC_DCCTL7_CTC_M   0x00000C00

◆ ADC_DCCTL7_CTC_MID

#define ADC_DCCTL7_CTC_MID   0x00000400

◆ ADC_DCCTL7_CTE

#define ADC_DCCTL7_CTE   0x00001000

◆ ADC_DCCTL7_CTM_ALWAYS

#define ADC_DCCTL7_CTM_ALWAYS   0x00000000

◆ ADC_DCCTL7_CTM_HALWAYS

#define ADC_DCCTL7_CTM_HALWAYS   0x00000200

◆ ADC_DCCTL7_CTM_HONCE

#define ADC_DCCTL7_CTM_HONCE   0x00000300

◆ ADC_DCCTL7_CTM_M

#define ADC_DCCTL7_CTM_M   0x00000300

◆ ADC_DCCTL7_CTM_ONCE

#define ADC_DCCTL7_CTM_ONCE   0x00000100

◆ ADC_DCISC_DCINT0

#define ADC_DCISC_DCINT0   0x00000001

◆ ADC_DCISC_DCINT1

#define ADC_DCISC_DCINT1   0x00000002

◆ ADC_DCISC_DCINT2

#define ADC_DCISC_DCINT2   0x00000004

◆ ADC_DCISC_DCINT3

#define ADC_DCISC_DCINT3   0x00000008

◆ ADC_DCISC_DCINT4

#define ADC_DCISC_DCINT4   0x00000010

◆ ADC_DCISC_DCINT5

#define ADC_DCISC_DCINT5   0x00000020

◆ ADC_DCISC_DCINT6

#define ADC_DCISC_DCINT6   0x00000040

◆ ADC_DCISC_DCINT7

#define ADC_DCISC_DCINT7   0x00000080

◆ ADC_DCRIC_DCINT0

#define ADC_DCRIC_DCINT0   0x00000001

◆ ADC_DCRIC_DCINT1

#define ADC_DCRIC_DCINT1   0x00000002

◆ ADC_DCRIC_DCINT2

#define ADC_DCRIC_DCINT2   0x00000004

◆ ADC_DCRIC_DCINT3

#define ADC_DCRIC_DCINT3   0x00000008

◆ ADC_DCRIC_DCINT4

#define ADC_DCRIC_DCINT4   0x00000010

◆ ADC_DCRIC_DCINT5

#define ADC_DCRIC_DCINT5   0x00000020

◆ ADC_DCRIC_DCINT6

#define ADC_DCRIC_DCINT6   0x00000040

◆ ADC_DCRIC_DCINT7

#define ADC_DCRIC_DCINT7   0x00000080

◆ ADC_DCRIC_DCTRIG0

#define ADC_DCRIC_DCTRIG0   0x00010000

◆ ADC_DCRIC_DCTRIG1

#define ADC_DCRIC_DCTRIG1   0x00020000

◆ ADC_DCRIC_DCTRIG2

#define ADC_DCRIC_DCTRIG2   0x00040000

◆ ADC_DCRIC_DCTRIG3

#define ADC_DCRIC_DCTRIG3   0x00080000

◆ ADC_DCRIC_DCTRIG4

#define ADC_DCRIC_DCTRIG4   0x00100000

◆ ADC_DCRIC_DCTRIG5

#define ADC_DCRIC_DCTRIG5   0x00200000

◆ ADC_DCRIC_DCTRIG6

#define ADC_DCRIC_DCTRIG6   0x00400000

◆ ADC_DCRIC_DCTRIG7

#define ADC_DCRIC_DCTRIG7   0x00800000

◆ ADC_EMUX_EM0_ALWAYS

#define ADC_EMUX_EM0_ALWAYS   0x0000000F

◆ ADC_EMUX_EM0_COMP0

#define ADC_EMUX_EM0_COMP0   0x00000001

◆ ADC_EMUX_EM0_COMP1

#define ADC_EMUX_EM0_COMP1   0x00000002

◆ ADC_EMUX_EM0_EXTERNAL

#define ADC_EMUX_EM0_EXTERNAL   0x00000004

◆ ADC_EMUX_EM0_M

#define ADC_EMUX_EM0_M   0x0000000F

◆ ADC_EMUX_EM0_PROCESSOR

#define ADC_EMUX_EM0_PROCESSOR   0x00000000

◆ ADC_EMUX_EM0_PWM0

#define ADC_EMUX_EM0_PWM0   0x00000006

◆ ADC_EMUX_EM0_PWM1

#define ADC_EMUX_EM0_PWM1   0x00000007

◆ ADC_EMUX_EM0_PWM2

#define ADC_EMUX_EM0_PWM2   0x00000008

◆ ADC_EMUX_EM0_PWM3

#define ADC_EMUX_EM0_PWM3   0x00000009

◆ ADC_EMUX_EM0_TIMER

#define ADC_EMUX_EM0_TIMER   0x00000005

◆ ADC_EMUX_EM1_ALWAYS

#define ADC_EMUX_EM1_ALWAYS   0x000000F0

◆ ADC_EMUX_EM1_COMP0

#define ADC_EMUX_EM1_COMP0   0x00000010

◆ ADC_EMUX_EM1_COMP1

#define ADC_EMUX_EM1_COMP1   0x00000020

◆ ADC_EMUX_EM1_EXTERNAL

#define ADC_EMUX_EM1_EXTERNAL   0x00000040

◆ ADC_EMUX_EM1_M

#define ADC_EMUX_EM1_M   0x000000F0

◆ ADC_EMUX_EM1_PROCESSOR

#define ADC_EMUX_EM1_PROCESSOR   0x00000000

◆ ADC_EMUX_EM1_PWM0

#define ADC_EMUX_EM1_PWM0   0x00000060

◆ ADC_EMUX_EM1_PWM1

#define ADC_EMUX_EM1_PWM1   0x00000070

◆ ADC_EMUX_EM1_PWM2

#define ADC_EMUX_EM1_PWM2   0x00000080

◆ ADC_EMUX_EM1_PWM3

#define ADC_EMUX_EM1_PWM3   0x00000090

◆ ADC_EMUX_EM1_TIMER

#define ADC_EMUX_EM1_TIMER   0x00000050

◆ ADC_EMUX_EM2_ALWAYS

#define ADC_EMUX_EM2_ALWAYS   0x00000F00

◆ ADC_EMUX_EM2_COMP0

#define ADC_EMUX_EM2_COMP0   0x00000100

◆ ADC_EMUX_EM2_COMP1

#define ADC_EMUX_EM2_COMP1   0x00000200

◆ ADC_EMUX_EM2_EXTERNAL

#define ADC_EMUX_EM2_EXTERNAL   0x00000400

◆ ADC_EMUX_EM2_M

#define ADC_EMUX_EM2_M   0x00000F00

◆ ADC_EMUX_EM2_PROCESSOR

#define ADC_EMUX_EM2_PROCESSOR   0x00000000

◆ ADC_EMUX_EM2_PWM0

#define ADC_EMUX_EM2_PWM0   0x00000600

◆ ADC_EMUX_EM2_PWM1

#define ADC_EMUX_EM2_PWM1   0x00000700

◆ ADC_EMUX_EM2_PWM2

#define ADC_EMUX_EM2_PWM2   0x00000800

◆ ADC_EMUX_EM2_PWM3

#define ADC_EMUX_EM2_PWM3   0x00000900

◆ ADC_EMUX_EM2_TIMER

#define ADC_EMUX_EM2_TIMER   0x00000500

◆ ADC_EMUX_EM3_ALWAYS

#define ADC_EMUX_EM3_ALWAYS   0x0000F000

◆ ADC_EMUX_EM3_COMP0

#define ADC_EMUX_EM3_COMP0   0x00001000

◆ ADC_EMUX_EM3_COMP1

#define ADC_EMUX_EM3_COMP1   0x00002000

◆ ADC_EMUX_EM3_EXTERNAL

#define ADC_EMUX_EM3_EXTERNAL   0x00004000

◆ ADC_EMUX_EM3_M

#define ADC_EMUX_EM3_M   0x0000F000

◆ ADC_EMUX_EM3_PROCESSOR

#define ADC_EMUX_EM3_PROCESSOR   0x00000000

◆ ADC_EMUX_EM3_PWM0

#define ADC_EMUX_EM3_PWM0   0x00006000

◆ ADC_EMUX_EM3_PWM1

#define ADC_EMUX_EM3_PWM1   0x00007000

◆ ADC_EMUX_EM3_PWM2

#define ADC_EMUX_EM3_PWM2   0x00008000

◆ ADC_EMUX_EM3_PWM3

#define ADC_EMUX_EM3_PWM3   0x00009000

◆ ADC_EMUX_EM3_TIMER

#define ADC_EMUX_EM3_TIMER   0x00005000

◆ ADC_IM_DCONSS0

#define ADC_IM_DCONSS0   0x00010000

◆ ADC_IM_DCONSS1

#define ADC_IM_DCONSS1   0x00020000

◆ ADC_IM_DCONSS2

#define ADC_IM_DCONSS2   0x00040000

◆ ADC_IM_DCONSS3

#define ADC_IM_DCONSS3   0x00080000

◆ ADC_IM_MASK0

#define ADC_IM_MASK0   0x00000001

◆ ADC_IM_MASK1

#define ADC_IM_MASK1   0x00000002

◆ ADC_IM_MASK2

#define ADC_IM_MASK2   0x00000004

◆ ADC_IM_MASK3

#define ADC_IM_MASK3   0x00000008

◆ ADC_ISC_DCINSS0

#define ADC_ISC_DCINSS0   0x00010000

◆ ADC_ISC_DCINSS1

#define ADC_ISC_DCINSS1   0x00020000

◆ ADC_ISC_DCINSS2

#define ADC_ISC_DCINSS2   0x00040000

◆ ADC_ISC_DCINSS3

#define ADC_ISC_DCINSS3   0x00080000

◆ ADC_ISC_IN0

#define ADC_ISC_IN0   0x00000001

◆ ADC_ISC_IN1

#define ADC_ISC_IN1   0x00000002

◆ ADC_ISC_IN2

#define ADC_ISC_IN2   0x00000004

◆ ADC_ISC_IN3

#define ADC_ISC_IN3   0x00000008

◆ ADC_OSTAT_OV0

#define ADC_OSTAT_OV0   0x00000001

◆ ADC_OSTAT_OV1

#define ADC_OSTAT_OV1   0x00000002

◆ ADC_OSTAT_OV2

#define ADC_OSTAT_OV2   0x00000004

◆ ADC_OSTAT_OV3

#define ADC_OSTAT_OV3   0x00000008

◆ ADC_PC_SR_125K

#define ADC_PC_SR_125K   0x00000001

◆ ADC_PC_SR_1M

#define ADC_PC_SR_1M   0x00000007

◆ ADC_PC_SR_250K

#define ADC_PC_SR_250K   0x00000003

◆ ADC_PC_SR_500K

#define ADC_PC_SR_500K   0x00000005

◆ ADC_PC_SR_M

#define ADC_PC_SR_M   0x0000000F

◆ ADC_PP_CH_M

#define ADC_PP_CH_M   0x000003F0

◆ ADC_PP_CH_S

#define ADC_PP_CH_S   4

◆ ADC_PP_DC_M

#define ADC_PP_DC_M   0x0000FC00

◆ ADC_PP_DC_S

#define ADC_PP_DC_S   10

◆ ADC_PP_MSR_125K

#define ADC_PP_MSR_125K   0x00000001

◆ ADC_PP_MSR_1M

#define ADC_PP_MSR_1M   0x00000007

◆ ADC_PP_MSR_250K

#define ADC_PP_MSR_250K   0x00000003

◆ ADC_PP_MSR_500K

#define ADC_PP_MSR_500K   0x00000005

◆ ADC_PP_MSR_M

#define ADC_PP_MSR_M   0x0000000F

◆ ADC_PP_RSL_M

#define ADC_PP_RSL_M   0x007C0000

◆ ADC_PP_RSL_S

#define ADC_PP_RSL_S   18

◆ ADC_PP_TS

#define ADC_PP_TS   0x00800000

◆ ADC_PP_TYPE_M

#define ADC_PP_TYPE_M   0x00030000

◆ ADC_PP_TYPE_SAR

#define ADC_PP_TYPE_SAR   0x00000000

◆ ADC_PSSI_GSYNC

#define ADC_PSSI_GSYNC   0x80000000

◆ ADC_PSSI_SS0

#define ADC_PSSI_SS0   0x00000001

◆ ADC_PSSI_SS1

#define ADC_PSSI_SS1   0x00000002

◆ ADC_PSSI_SS2

#define ADC_PSSI_SS2   0x00000004

◆ ADC_PSSI_SS3

#define ADC_PSSI_SS3   0x00000008

◆ ADC_PSSI_SYNCWAIT

#define ADC_PSSI_SYNCWAIT   0x08000000

◆ ADC_RIS_INR0

#define ADC_RIS_INR0   0x00000001

◆ ADC_RIS_INR1

#define ADC_RIS_INR1   0x00000002

◆ ADC_RIS_INR2

#define ADC_RIS_INR2   0x00000004

◆ ADC_RIS_INR3

#define ADC_RIS_INR3   0x00000008

◆ ADC_RIS_INRDC

#define ADC_RIS_INRDC   0x00010000

◆ ADC_SAC_AVG_16X

#define ADC_SAC_AVG_16X   0x00000004

◆ ADC_SAC_AVG_2X

#define ADC_SAC_AVG_2X   0x00000001

◆ ADC_SAC_AVG_32X

#define ADC_SAC_AVG_32X   0x00000005

◆ ADC_SAC_AVG_4X

#define ADC_SAC_AVG_4X   0x00000002

◆ ADC_SAC_AVG_64X

#define ADC_SAC_AVG_64X   0x00000006

◆ ADC_SAC_AVG_8X

#define ADC_SAC_AVG_8X   0x00000003

◆ ADC_SAC_AVG_M

#define ADC_SAC_AVG_M   0x00000007

◆ ADC_SAC_AVG_OFF

#define ADC_SAC_AVG_OFF   0x00000000

◆ ADC_SPC_PHASE_0

#define ADC_SPC_PHASE_0   0x00000000

◆ ADC_SPC_PHASE_112_5

#define ADC_SPC_PHASE_112_5   0x00000005

◆ ADC_SPC_PHASE_135

#define ADC_SPC_PHASE_135   0x00000006

◆ ADC_SPC_PHASE_157_5

#define ADC_SPC_PHASE_157_5   0x00000007

◆ ADC_SPC_PHASE_180

#define ADC_SPC_PHASE_180   0x00000008

◆ ADC_SPC_PHASE_202_5

#define ADC_SPC_PHASE_202_5   0x00000009

◆ ADC_SPC_PHASE_225

#define ADC_SPC_PHASE_225   0x0000000A

◆ ADC_SPC_PHASE_22_5

#define ADC_SPC_PHASE_22_5   0x00000001

◆ ADC_SPC_PHASE_247_5

#define ADC_SPC_PHASE_247_5   0x0000000B

◆ ADC_SPC_PHASE_270

#define ADC_SPC_PHASE_270   0x0000000C

◆ ADC_SPC_PHASE_292_5

#define ADC_SPC_PHASE_292_5   0x0000000D

◆ ADC_SPC_PHASE_315

#define ADC_SPC_PHASE_315   0x0000000E

◆ ADC_SPC_PHASE_337_5

#define ADC_SPC_PHASE_337_5   0x0000000F

◆ ADC_SPC_PHASE_45

#define ADC_SPC_PHASE_45   0x00000002

◆ ADC_SPC_PHASE_67_5

#define ADC_SPC_PHASE_67_5   0x00000003

◆ ADC_SPC_PHASE_90

#define ADC_SPC_PHASE_90   0x00000004

◆ ADC_SPC_PHASE_M

#define ADC_SPC_PHASE_M   0x0000000F

◆ ADC_SSCTL0_D0

#define ADC_SSCTL0_D0   0x00000001

◆ ADC_SSCTL0_D1

#define ADC_SSCTL0_D1   0x00000010

◆ ADC_SSCTL0_D2

#define ADC_SSCTL0_D2   0x00000100

◆ ADC_SSCTL0_D3

#define ADC_SSCTL0_D3   0x00001000

◆ ADC_SSCTL0_D4

#define ADC_SSCTL0_D4   0x00010000

◆ ADC_SSCTL0_D5

#define ADC_SSCTL0_D5   0x00100000

◆ ADC_SSCTL0_D6

#define ADC_SSCTL0_D6   0x01000000

◆ ADC_SSCTL0_D7

#define ADC_SSCTL0_D7   0x10000000

◆ ADC_SSCTL0_END0

#define ADC_SSCTL0_END0   0x00000002

◆ ADC_SSCTL0_END1

#define ADC_SSCTL0_END1   0x00000020

◆ ADC_SSCTL0_END2

#define ADC_SSCTL0_END2   0x00000200

◆ ADC_SSCTL0_END3

#define ADC_SSCTL0_END3   0x00002000

◆ ADC_SSCTL0_END4

#define ADC_SSCTL0_END4   0x00020000

◆ ADC_SSCTL0_END5

#define ADC_SSCTL0_END5   0x00200000

◆ ADC_SSCTL0_END6

#define ADC_SSCTL0_END6   0x02000000

◆ ADC_SSCTL0_END7

#define ADC_SSCTL0_END7   0x20000000

◆ ADC_SSCTL0_IE0

#define ADC_SSCTL0_IE0   0x00000004

◆ ADC_SSCTL0_IE1

#define ADC_SSCTL0_IE1   0x00000040

◆ ADC_SSCTL0_IE2

#define ADC_SSCTL0_IE2   0x00000400

◆ ADC_SSCTL0_IE3

#define ADC_SSCTL0_IE3   0x00004000

◆ ADC_SSCTL0_IE4

#define ADC_SSCTL0_IE4   0x00040000

◆ ADC_SSCTL0_IE5

#define ADC_SSCTL0_IE5   0x00400000

◆ ADC_SSCTL0_IE6

#define ADC_SSCTL0_IE6   0x04000000

◆ ADC_SSCTL0_IE7

#define ADC_SSCTL0_IE7   0x40000000

◆ ADC_SSCTL0_TS0

#define ADC_SSCTL0_TS0   0x00000008

◆ ADC_SSCTL0_TS1

#define ADC_SSCTL0_TS1   0x00000080

◆ ADC_SSCTL0_TS2

#define ADC_SSCTL0_TS2   0x00000800

◆ ADC_SSCTL0_TS3

#define ADC_SSCTL0_TS3   0x00008000

◆ ADC_SSCTL0_TS4

#define ADC_SSCTL0_TS4   0x00080000

◆ ADC_SSCTL0_TS5

#define ADC_SSCTL0_TS5   0x00800000

◆ ADC_SSCTL0_TS6

#define ADC_SSCTL0_TS6   0x08000000

◆ ADC_SSCTL0_TS7

#define ADC_SSCTL0_TS7   0x80000000

◆ ADC_SSCTL1_D0

#define ADC_SSCTL1_D0   0x00000001

◆ ADC_SSCTL1_D1

#define ADC_SSCTL1_D1   0x00000010

◆ ADC_SSCTL1_D2

#define ADC_SSCTL1_D2   0x00000100

◆ ADC_SSCTL1_D3

#define ADC_SSCTL1_D3   0x00001000

◆ ADC_SSCTL1_END0

#define ADC_SSCTL1_END0   0x00000002

◆ ADC_SSCTL1_END1

#define ADC_SSCTL1_END1   0x00000020

◆ ADC_SSCTL1_END2

#define ADC_SSCTL1_END2   0x00000200

◆ ADC_SSCTL1_END3

#define ADC_SSCTL1_END3   0x00002000

◆ ADC_SSCTL1_IE0

#define ADC_SSCTL1_IE0   0x00000004

◆ ADC_SSCTL1_IE1

#define ADC_SSCTL1_IE1   0x00000040

◆ ADC_SSCTL1_IE2

#define ADC_SSCTL1_IE2   0x00000400

◆ ADC_SSCTL1_IE3

#define ADC_SSCTL1_IE3   0x00004000

◆ ADC_SSCTL1_TS0

#define ADC_SSCTL1_TS0   0x00000008

◆ ADC_SSCTL1_TS1

#define ADC_SSCTL1_TS1   0x00000080

◆ ADC_SSCTL1_TS2

#define ADC_SSCTL1_TS2   0x00000800

◆ ADC_SSCTL1_TS3

#define ADC_SSCTL1_TS3   0x00008000

◆ ADC_SSCTL2_D0

#define ADC_SSCTL2_D0   0x00000001

◆ ADC_SSCTL2_D1

#define ADC_SSCTL2_D1   0x00000010

◆ ADC_SSCTL2_D2

#define ADC_SSCTL2_D2   0x00000100

◆ ADC_SSCTL2_D3

#define ADC_SSCTL2_D3   0x00001000

◆ ADC_SSCTL2_END0

#define ADC_SSCTL2_END0   0x00000002

◆ ADC_SSCTL2_END1

#define ADC_SSCTL2_END1   0x00000020

◆ ADC_SSCTL2_END2

#define ADC_SSCTL2_END2   0x00000200

◆ ADC_SSCTL2_END3

#define ADC_SSCTL2_END3   0x00002000

◆ ADC_SSCTL2_IE0

#define ADC_SSCTL2_IE0   0x00000004

◆ ADC_SSCTL2_IE1

#define ADC_SSCTL2_IE1   0x00000040

◆ ADC_SSCTL2_IE2

#define ADC_SSCTL2_IE2   0x00000400

◆ ADC_SSCTL2_IE3

#define ADC_SSCTL2_IE3   0x00004000

◆ ADC_SSCTL2_TS0

#define ADC_SSCTL2_TS0   0x00000008

◆ ADC_SSCTL2_TS1

#define ADC_SSCTL2_TS1   0x00000080

◆ ADC_SSCTL2_TS2

#define ADC_SSCTL2_TS2   0x00000800

◆ ADC_SSCTL2_TS3

#define ADC_SSCTL2_TS3   0x00008000

◆ ADC_SSCTL3_D0

#define ADC_SSCTL3_D0   0x00000001

◆ ADC_SSCTL3_END0

#define ADC_SSCTL3_END0   0x00000002

◆ ADC_SSCTL3_IE0

#define ADC_SSCTL3_IE0   0x00000004

◆ ADC_SSCTL3_TS0

#define ADC_SSCTL3_TS0   0x00000008

◆ ADC_SSDC0_S0DCSEL_M

#define ADC_SSDC0_S0DCSEL_M   0x0000000F

◆ ADC_SSDC0_S0DCSEL_S

#define ADC_SSDC0_S0DCSEL_S   0

◆ ADC_SSDC0_S1DCSEL_M

#define ADC_SSDC0_S1DCSEL_M   0x000000F0

◆ ADC_SSDC0_S1DCSEL_S

#define ADC_SSDC0_S1DCSEL_S   4

◆ ADC_SSDC0_S2DCSEL_M

#define ADC_SSDC0_S2DCSEL_M   0x00000F00

◆ ADC_SSDC0_S2DCSEL_S

#define ADC_SSDC0_S2DCSEL_S   8

◆ ADC_SSDC0_S3DCSEL_M

#define ADC_SSDC0_S3DCSEL_M   0x0000F000

◆ ADC_SSDC0_S3DCSEL_S

#define ADC_SSDC0_S3DCSEL_S   12

◆ ADC_SSDC0_S4DCSEL_M

#define ADC_SSDC0_S4DCSEL_M   0x000F0000

◆ ADC_SSDC0_S4DCSEL_S

#define ADC_SSDC0_S4DCSEL_S   16

◆ ADC_SSDC0_S5DCSEL_M

#define ADC_SSDC0_S5DCSEL_M   0x00F00000

◆ ADC_SSDC0_S5DCSEL_S

#define ADC_SSDC0_S5DCSEL_S   20

◆ ADC_SSDC0_S6DCSEL_M

#define ADC_SSDC0_S6DCSEL_M   0x0F000000

◆ ADC_SSDC0_S6DCSEL_S

#define ADC_SSDC0_S6DCSEL_S   24

◆ ADC_SSDC0_S7DCSEL_M

#define ADC_SSDC0_S7DCSEL_M   0xF0000000

◆ ADC_SSDC1_S0DCSEL_M

#define ADC_SSDC1_S0DCSEL_M   0x0000000F

◆ ADC_SSDC1_S0DCSEL_S

#define ADC_SSDC1_S0DCSEL_S   0

◆ ADC_SSDC1_S1DCSEL_M

#define ADC_SSDC1_S1DCSEL_M   0x000000F0

◆ ADC_SSDC1_S1DCSEL_S

#define ADC_SSDC1_S1DCSEL_S   4

◆ ADC_SSDC1_S2DCSEL_M

#define ADC_SSDC1_S2DCSEL_M   0x00000F00

◆ ADC_SSDC1_S2DCSEL_S

#define ADC_SSDC1_S2DCSEL_S   8

◆ ADC_SSDC1_S3DCSEL_M

#define ADC_SSDC1_S3DCSEL_M   0x0000F000

◆ ADC_SSDC2_S0DCSEL_M

#define ADC_SSDC2_S0DCSEL_M   0x0000000F

◆ ADC_SSDC2_S0DCSEL_S

#define ADC_SSDC2_S0DCSEL_S   0

◆ ADC_SSDC2_S1DCSEL_M

#define ADC_SSDC2_S1DCSEL_M   0x000000F0

◆ ADC_SSDC2_S1DCSEL_S

#define ADC_SSDC2_S1DCSEL_S   4

◆ ADC_SSDC2_S2DCSEL_M

#define ADC_SSDC2_S2DCSEL_M   0x00000F00

◆ ADC_SSDC2_S2DCSEL_S

#define ADC_SSDC2_S2DCSEL_S   8

◆ ADC_SSDC2_S3DCSEL_M

#define ADC_SSDC2_S3DCSEL_M   0x0000F000

◆ ADC_SSDC3_S0DCSEL_M

#define ADC_SSDC3_S0DCSEL_M   0x0000000F

◆ ADC_SSFIFO0_DATA_M

#define ADC_SSFIFO0_DATA_M   0x00000FFF

◆ ADC_SSFIFO0_DATA_S

#define ADC_SSFIFO0_DATA_S   0

◆ ADC_SSFIFO1_DATA_M

#define ADC_SSFIFO1_DATA_M   0x00000FFF

◆ ADC_SSFIFO1_DATA_S

#define ADC_SSFIFO1_DATA_S   0

◆ ADC_SSFIFO2_DATA_M

#define ADC_SSFIFO2_DATA_M   0x00000FFF

◆ ADC_SSFIFO2_DATA_S

#define ADC_SSFIFO2_DATA_S   0

◆ ADC_SSFIFO3_DATA_M

#define ADC_SSFIFO3_DATA_M   0x00000FFF

◆ ADC_SSFIFO3_DATA_S

#define ADC_SSFIFO3_DATA_S   0

◆ ADC_SSFSTAT0_EMPTY

#define ADC_SSFSTAT0_EMPTY   0x00000100

◆ ADC_SSFSTAT0_FULL

#define ADC_SSFSTAT0_FULL   0x00001000

◆ ADC_SSFSTAT0_HPTR_M

#define ADC_SSFSTAT0_HPTR_M   0x000000F0

◆ ADC_SSFSTAT0_HPTR_S

#define ADC_SSFSTAT0_HPTR_S   4

◆ ADC_SSFSTAT0_TPTR_M

#define ADC_SSFSTAT0_TPTR_M   0x0000000F

◆ ADC_SSFSTAT0_TPTR_S

#define ADC_SSFSTAT0_TPTR_S   0

◆ ADC_SSFSTAT1_EMPTY

#define ADC_SSFSTAT1_EMPTY   0x00000100

◆ ADC_SSFSTAT1_FULL

#define ADC_SSFSTAT1_FULL   0x00001000

◆ ADC_SSFSTAT1_HPTR_M

#define ADC_SSFSTAT1_HPTR_M   0x000000F0

◆ ADC_SSFSTAT1_HPTR_S

#define ADC_SSFSTAT1_HPTR_S   4

◆ ADC_SSFSTAT1_TPTR_M

#define ADC_SSFSTAT1_TPTR_M   0x0000000F

◆ ADC_SSFSTAT1_TPTR_S

#define ADC_SSFSTAT1_TPTR_S   0

◆ ADC_SSFSTAT2_EMPTY

#define ADC_SSFSTAT2_EMPTY   0x00000100

◆ ADC_SSFSTAT2_FULL

#define ADC_SSFSTAT2_FULL   0x00001000

◆ ADC_SSFSTAT2_HPTR_M

#define ADC_SSFSTAT2_HPTR_M   0x000000F0

◆ ADC_SSFSTAT2_HPTR_S

#define ADC_SSFSTAT2_HPTR_S   4

◆ ADC_SSFSTAT2_TPTR_M

#define ADC_SSFSTAT2_TPTR_M   0x0000000F

◆ ADC_SSFSTAT2_TPTR_S

#define ADC_SSFSTAT2_TPTR_S   0

◆ ADC_SSFSTAT3_EMPTY

#define ADC_SSFSTAT3_EMPTY   0x00000100

◆ ADC_SSFSTAT3_FULL

#define ADC_SSFSTAT3_FULL   0x00001000

◆ ADC_SSFSTAT3_HPTR_M

#define ADC_SSFSTAT3_HPTR_M   0x000000F0

◆ ADC_SSFSTAT3_HPTR_S

#define ADC_SSFSTAT3_HPTR_S   4

◆ ADC_SSFSTAT3_TPTR_M

#define ADC_SSFSTAT3_TPTR_M   0x0000000F

◆ ADC_SSFSTAT3_TPTR_S

#define ADC_SSFSTAT3_TPTR_S   0

◆ ADC_SSMUX0_MUX0_M

#define ADC_SSMUX0_MUX0_M   0x0000000F

◆ ADC_SSMUX0_MUX0_S

#define ADC_SSMUX0_MUX0_S   0

◆ ADC_SSMUX0_MUX1_M

#define ADC_SSMUX0_MUX1_M   0x000000F0

◆ ADC_SSMUX0_MUX1_S

#define ADC_SSMUX0_MUX1_S   4

◆ ADC_SSMUX0_MUX2_M

#define ADC_SSMUX0_MUX2_M   0x00000F00

◆ ADC_SSMUX0_MUX2_S

#define ADC_SSMUX0_MUX2_S   8

◆ ADC_SSMUX0_MUX3_M

#define ADC_SSMUX0_MUX3_M   0x0000F000

◆ ADC_SSMUX0_MUX3_S

#define ADC_SSMUX0_MUX3_S   12

◆ ADC_SSMUX0_MUX4_M

#define ADC_SSMUX0_MUX4_M   0x000F0000

◆ ADC_SSMUX0_MUX4_S

#define ADC_SSMUX0_MUX4_S   16

◆ ADC_SSMUX0_MUX5_M

#define ADC_SSMUX0_MUX5_M   0x00F00000

◆ ADC_SSMUX0_MUX5_S

#define ADC_SSMUX0_MUX5_S   20

◆ ADC_SSMUX0_MUX6_M

#define ADC_SSMUX0_MUX6_M   0x0F000000

◆ ADC_SSMUX0_MUX6_S

#define ADC_SSMUX0_MUX6_S   24

◆ ADC_SSMUX0_MUX7_M

#define ADC_SSMUX0_MUX7_M   0xF0000000

◆ ADC_SSMUX0_MUX7_S

#define ADC_SSMUX0_MUX7_S   28

◆ ADC_SSMUX1_MUX0_M

#define ADC_SSMUX1_MUX0_M   0x0000000F

◆ ADC_SSMUX1_MUX0_S

#define ADC_SSMUX1_MUX0_S   0

◆ ADC_SSMUX1_MUX1_M

#define ADC_SSMUX1_MUX1_M   0x000000F0

◆ ADC_SSMUX1_MUX1_S

#define ADC_SSMUX1_MUX1_S   4

◆ ADC_SSMUX1_MUX2_M

#define ADC_SSMUX1_MUX2_M   0x00000F00

◆ ADC_SSMUX1_MUX2_S

#define ADC_SSMUX1_MUX2_S   8

◆ ADC_SSMUX1_MUX3_M

#define ADC_SSMUX1_MUX3_M   0x0000F000

◆ ADC_SSMUX1_MUX3_S

#define ADC_SSMUX1_MUX3_S   12

◆ ADC_SSMUX2_MUX0_M

#define ADC_SSMUX2_MUX0_M   0x0000000F

◆ ADC_SSMUX2_MUX0_S

#define ADC_SSMUX2_MUX0_S   0

◆ ADC_SSMUX2_MUX1_M

#define ADC_SSMUX2_MUX1_M   0x000000F0

◆ ADC_SSMUX2_MUX1_S

#define ADC_SSMUX2_MUX1_S   4

◆ ADC_SSMUX2_MUX2_M

#define ADC_SSMUX2_MUX2_M   0x00000F00

◆ ADC_SSMUX2_MUX2_S

#define ADC_SSMUX2_MUX2_S   8

◆ ADC_SSMUX2_MUX3_M

#define ADC_SSMUX2_MUX3_M   0x0000F000

◆ ADC_SSMUX2_MUX3_S

#define ADC_SSMUX2_MUX3_S   12

◆ ADC_SSMUX3_MUX0_M

#define ADC_SSMUX3_MUX0_M   0x0000000F

◆ ADC_SSMUX3_MUX0_S

#define ADC_SSMUX3_MUX0_S   0

◆ ADC_SSOP0_S0DCOP

#define ADC_SSOP0_S0DCOP   0x00000001

◆ ADC_SSOP0_S1DCOP

#define ADC_SSOP0_S1DCOP   0x00000010

◆ ADC_SSOP0_S2DCOP

#define ADC_SSOP0_S2DCOP   0x00000100

◆ ADC_SSOP0_S3DCOP

#define ADC_SSOP0_S3DCOP   0x00001000

◆ ADC_SSOP0_S4DCOP

#define ADC_SSOP0_S4DCOP   0x00010000

◆ ADC_SSOP0_S5DCOP

#define ADC_SSOP0_S5DCOP   0x00100000

◆ ADC_SSOP0_S6DCOP

#define ADC_SSOP0_S6DCOP   0x01000000

◆ ADC_SSOP0_S7DCOP

#define ADC_SSOP0_S7DCOP   0x10000000

◆ ADC_SSOP1_S0DCOP

#define ADC_SSOP1_S0DCOP   0x00000001

◆ ADC_SSOP1_S1DCOP

#define ADC_SSOP1_S1DCOP   0x00000010

◆ ADC_SSOP1_S2DCOP

#define ADC_SSOP1_S2DCOP   0x00000100

◆ ADC_SSOP1_S3DCOP

#define ADC_SSOP1_S3DCOP   0x00001000

◆ ADC_SSOP2_S0DCOP

#define ADC_SSOP2_S0DCOP   0x00000001

◆ ADC_SSOP2_S1DCOP

#define ADC_SSOP2_S1DCOP   0x00000010

◆ ADC_SSOP2_S2DCOP

#define ADC_SSOP2_S2DCOP   0x00000100

◆ ADC_SSOP2_S3DCOP

#define ADC_SSOP2_S3DCOP   0x00001000

◆ ADC_SSOP3_S0DCOP

#define ADC_SSOP3_S0DCOP   0x00000001

◆ ADC_SSPRI_SS0_M

#define ADC_SSPRI_SS0_M   0x00000003

◆ ADC_SSPRI_SS1_M

#define ADC_SSPRI_SS1_M   0x00000030

◆ ADC_SSPRI_SS2_M

#define ADC_SSPRI_SS2_M   0x00000300

◆ ADC_SSPRI_SS3_M

#define ADC_SSPRI_SS3_M   0x00003000

◆ ADC_TSSEL_PS0_0

#define ADC_TSSEL_PS0_0   0x00000000

◆ ADC_TSSEL_PS0_1

#define ADC_TSSEL_PS0_1   0x00000010

◆ ADC_TSSEL_PS0_M

#define ADC_TSSEL_PS0_M   0x00000030

◆ ADC_TSSEL_PS1_0

#define ADC_TSSEL_PS1_0   0x00000000

◆ ADC_TSSEL_PS1_1

#define ADC_TSSEL_PS1_1   0x00001000

◆ ADC_TSSEL_PS1_M

#define ADC_TSSEL_PS1_M   0x00003000

◆ ADC_TSSEL_PS2_0

#define ADC_TSSEL_PS2_0   0x00000000

◆ ADC_TSSEL_PS2_1

#define ADC_TSSEL_PS2_1   0x00100000

◆ ADC_TSSEL_PS2_M

#define ADC_TSSEL_PS2_M   0x00300000

◆ ADC_TSSEL_PS3_0

#define ADC_TSSEL_PS3_0   0x00000000

◆ ADC_TSSEL_PS3_1

#define ADC_TSSEL_PS3_1   0x10000000

◆ ADC_TSSEL_PS3_M

#define ADC_TSSEL_PS3_M   0x30000000

◆ ADC_USTAT_UV0

#define ADC_USTAT_UV0   0x00000001

◆ ADC_USTAT_UV1

#define ADC_USTAT_UV1   0x00000002

◆ ADC_USTAT_UV2

#define ADC_USTAT_UV2   0x00000004

◆ ADC_USTAT_UV3

#define ADC_USTAT_UV3   0x00000008

◆ CAN0_BIT_R

#define CAN0_BIT_R   (*((volatile u32 *)0x4004000C))

◆ CAN0_BRPE_R

#define CAN0_BRPE_R   (*((volatile u32 *)0x40040018))

◆ CAN0_CTL_R

#define CAN0_CTL_R   (*((volatile u32 *)0x40040000))

◆ CAN0_ERR_R

#define CAN0_ERR_R   (*((volatile u32 *)0x40040008))

◆ CAN0_IF1ARB1_R

#define CAN0_IF1ARB1_R   (*((volatile u32 *)0x40040030))

◆ CAN0_IF1ARB2_R

#define CAN0_IF1ARB2_R   (*((volatile u32 *)0x40040034))

◆ CAN0_IF1CMSK_R

#define CAN0_IF1CMSK_R   (*((volatile u32 *)0x40040024))

◆ CAN0_IF1CRQ_R

#define CAN0_IF1CRQ_R   (*((volatile u32 *)0x40040020))

◆ CAN0_IF1DA1_R

#define CAN0_IF1DA1_R   (*((volatile u32 *)0x4004003C))

◆ CAN0_IF1DA2_R

#define CAN0_IF1DA2_R   (*((volatile u32 *)0x40040040))

◆ CAN0_IF1DB1_R

#define CAN0_IF1DB1_R   (*((volatile u32 *)0x40040044))

◆ CAN0_IF1DB2_R

#define CAN0_IF1DB2_R   (*((volatile u32 *)0x40040048))

◆ CAN0_IF1MCTL_R

#define CAN0_IF1MCTL_R   (*((volatile u32 *)0x40040038))

◆ CAN0_IF1MSK1_R

#define CAN0_IF1MSK1_R   (*((volatile u32 *)0x40040028))

◆ CAN0_IF1MSK2_R

#define CAN0_IF1MSK2_R   (*((volatile u32 *)0x4004002C))

◆ CAN0_IF2ARB1_R

#define CAN0_IF2ARB1_R   (*((volatile u32 *)0x40040090))

◆ CAN0_IF2ARB2_R

#define CAN0_IF2ARB2_R   (*((volatile u32 *)0x40040094))

◆ CAN0_IF2CMSK_R

#define CAN0_IF2CMSK_R   (*((volatile u32 *)0x40040084))

◆ CAN0_IF2CRQ_R

#define CAN0_IF2CRQ_R   (*((volatile u32 *)0x40040080))

◆ CAN0_IF2DA1_R

#define CAN0_IF2DA1_R   (*((volatile u32 *)0x4004009C))

◆ CAN0_IF2DA2_R

#define CAN0_IF2DA2_R   (*((volatile u32 *)0x400400A0))

◆ CAN0_IF2DB1_R

#define CAN0_IF2DB1_R   (*((volatile u32 *)0x400400A4))

◆ CAN0_IF2DB2_R

#define CAN0_IF2DB2_R   (*((volatile u32 *)0x400400A8))

◆ CAN0_IF2MCTL_R

#define CAN0_IF2MCTL_R   (*((volatile u32 *)0x40040098))

◆ CAN0_IF2MSK1_R

#define CAN0_IF2MSK1_R   (*((volatile u32 *)0x40040088))

◆ CAN0_IF2MSK2_R

#define CAN0_IF2MSK2_R   (*((volatile u32 *)0x4004008C))

◆ CAN0_INT_R

#define CAN0_INT_R   (*((volatile u32 *)0x40040010))

◆ CAN0_MSG1INT_R

#define CAN0_MSG1INT_R   (*((volatile u32 *)0x40040140))

◆ CAN0_MSG1VAL_R

#define CAN0_MSG1VAL_R   (*((volatile u32 *)0x40040160))

◆ CAN0_MSG2INT_R

#define CAN0_MSG2INT_R   (*((volatile u32 *)0x40040144))

◆ CAN0_MSG2VAL_R

#define CAN0_MSG2VAL_R   (*((volatile u32 *)0x40040164))

◆ CAN0_NWDA1_R

#define CAN0_NWDA1_R   (*((volatile u32 *)0x40040120))

◆ CAN0_NWDA2_R

#define CAN0_NWDA2_R   (*((volatile u32 *)0x40040124))

◆ CAN0_STS_R

#define CAN0_STS_R   (*((volatile u32 *)0x40040004))

◆ CAN0_TST_R

#define CAN0_TST_R   (*((volatile u32 *)0x40040014))

◆ CAN0_TXRQ1_R

#define CAN0_TXRQ1_R   (*((volatile u32 *)0x40040100))

◆ CAN0_TXRQ2_R

#define CAN0_TXRQ2_R   (*((volatile u32 *)0x40040104))

◆ CAN1_BIT_R

#define CAN1_BIT_R   (*((volatile u32 *)0x4004100C))

◆ CAN1_BRPE_R

#define CAN1_BRPE_R   (*((volatile u32 *)0x40041018))

◆ CAN1_CTL_R

#define CAN1_CTL_R   (*((volatile u32 *)0x40041000))

◆ CAN1_ERR_R

#define CAN1_ERR_R   (*((volatile u32 *)0x40041008))

◆ CAN1_IF1ARB1_R

#define CAN1_IF1ARB1_R   (*((volatile u32 *)0x40041030))

◆ CAN1_IF1ARB2_R

#define CAN1_IF1ARB2_R   (*((volatile u32 *)0x40041034))

◆ CAN1_IF1CMSK_R

#define CAN1_IF1CMSK_R   (*((volatile u32 *)0x40041024))

◆ CAN1_IF1CRQ_R

#define CAN1_IF1CRQ_R   (*((volatile u32 *)0x40041020))

◆ CAN1_IF1DA1_R

#define CAN1_IF1DA1_R   (*((volatile u32 *)0x4004103C))

◆ CAN1_IF1DA2_R

#define CAN1_IF1DA2_R   (*((volatile u32 *)0x40041040))

◆ CAN1_IF1DB1_R

#define CAN1_IF1DB1_R   (*((volatile u32 *)0x40041044))

◆ CAN1_IF1DB2_R

#define CAN1_IF1DB2_R   (*((volatile u32 *)0x40041048))

◆ CAN1_IF1MCTL_R

#define CAN1_IF1MCTL_R   (*((volatile u32 *)0x40041038))

◆ CAN1_IF1MSK1_R

#define CAN1_IF1MSK1_R   (*((volatile u32 *)0x40041028))

◆ CAN1_IF1MSK2_R

#define CAN1_IF1MSK2_R   (*((volatile u32 *)0x4004102C))

◆ CAN1_IF2ARB1_R

#define CAN1_IF2ARB1_R   (*((volatile u32 *)0x40041090))

◆ CAN1_IF2ARB2_R

#define CAN1_IF2ARB2_R   (*((volatile u32 *)0x40041094))

◆ CAN1_IF2CMSK_R

#define CAN1_IF2CMSK_R   (*((volatile u32 *)0x40041084))

◆ CAN1_IF2CRQ_R

#define CAN1_IF2CRQ_R   (*((volatile u32 *)0x40041080))

◆ CAN1_IF2DA1_R

#define CAN1_IF2DA1_R   (*((volatile u32 *)0x4004109C))

◆ CAN1_IF2DA2_R

#define CAN1_IF2DA2_R   (*((volatile u32 *)0x400410A0))

◆ CAN1_IF2DB1_R

#define CAN1_IF2DB1_R   (*((volatile u32 *)0x400410A4))

◆ CAN1_IF2DB2_R

#define CAN1_IF2DB2_R   (*((volatile u32 *)0x400410A8))

◆ CAN1_IF2MCTL_R

#define CAN1_IF2MCTL_R   (*((volatile u32 *)0x40041098))

◆ CAN1_IF2MSK1_R

#define CAN1_IF2MSK1_R   (*((volatile u32 *)0x40041088))

◆ CAN1_IF2MSK2_R

#define CAN1_IF2MSK2_R   (*((volatile u32 *)0x4004108C))

◆ CAN1_INT_R

#define CAN1_INT_R   (*((volatile u32 *)0x40041010))

◆ CAN1_MSG1INT_R

#define CAN1_MSG1INT_R   (*((volatile u32 *)0x40041140))

◆ CAN1_MSG1VAL_R

#define CAN1_MSG1VAL_R   (*((volatile u32 *)0x40041160))

◆ CAN1_MSG2INT_R

#define CAN1_MSG2INT_R   (*((volatile u32 *)0x40041144))

◆ CAN1_MSG2VAL_R

#define CAN1_MSG2VAL_R   (*((volatile u32 *)0x40041164))

◆ CAN1_NWDA1_R

#define CAN1_NWDA1_R   (*((volatile u32 *)0x40041120))

◆ CAN1_NWDA2_R

#define CAN1_NWDA2_R   (*((volatile u32 *)0x40041124))

◆ CAN1_STS_R

#define CAN1_STS_R   (*((volatile u32 *)0x40041004))

◆ CAN1_TST_R

#define CAN1_TST_R   (*((volatile u32 *)0x40041014))

◆ CAN1_TXRQ1_R

#define CAN1_TXRQ1_R   (*((volatile u32 *)0x40041100))

◆ CAN1_TXRQ2_R

#define CAN1_TXRQ2_R   (*((volatile u32 *)0x40041104))

◆ CAN_BIT_BRP_M

#define CAN_BIT_BRP_M   0x0000003F

◆ CAN_BIT_BRP_S

#define CAN_BIT_BRP_S   0

◆ CAN_BIT_SJW_M

#define CAN_BIT_SJW_M   0x000000C0

◆ CAN_BIT_SJW_S

#define CAN_BIT_SJW_S   6

◆ CAN_BIT_TSEG1_M

#define CAN_BIT_TSEG1_M   0x00000F00

◆ CAN_BIT_TSEG1_S

#define CAN_BIT_TSEG1_S   8

◆ CAN_BIT_TSEG2_M

#define CAN_BIT_TSEG2_M   0x00007000

◆ CAN_BIT_TSEG2_S

#define CAN_BIT_TSEG2_S   12

◆ CAN_BRPE_BRPE_M

#define CAN_BRPE_BRPE_M   0x0000000F

◆ CAN_BRPE_BRPE_S

#define CAN_BRPE_BRPE_S   0

◆ CAN_CTL_CCE

#define CAN_CTL_CCE   0x00000040

◆ CAN_CTL_DAR

#define CAN_CTL_DAR   0x00000020

◆ CAN_CTL_EIE

#define CAN_CTL_EIE   0x00000008

◆ CAN_CTL_IE

#define CAN_CTL_IE   0x00000002

◆ CAN_CTL_INIT

#define CAN_CTL_INIT   0x00000001

◆ CAN_CTL_SIE

#define CAN_CTL_SIE   0x00000004

◆ CAN_CTL_TEST

#define CAN_CTL_TEST   0x00000080

◆ CAN_ERR_REC_M

#define CAN_ERR_REC_M   0x00007F00

◆ CAN_ERR_REC_S

#define CAN_ERR_REC_S   8

◆ CAN_ERR_RP

#define CAN_ERR_RP   0x00008000

◆ CAN_ERR_TEC_M

#define CAN_ERR_TEC_M   0x000000FF

◆ CAN_ERR_TEC_S

#define CAN_ERR_TEC_S   0

◆ CAN_IF1ARB1_ID_M

#define CAN_IF1ARB1_ID_M   0x0000FFFF

◆ CAN_IF1ARB1_ID_S

#define CAN_IF1ARB1_ID_S   0

◆ CAN_IF1ARB2_DIR

#define CAN_IF1ARB2_DIR   0x00002000

◆ CAN_IF1ARB2_ID_M

#define CAN_IF1ARB2_ID_M   0x00001FFF

◆ CAN_IF1ARB2_ID_S

#define CAN_IF1ARB2_ID_S   0

◆ CAN_IF1ARB2_MSGVAL

#define CAN_IF1ARB2_MSGVAL   0x00008000

◆ CAN_IF1ARB2_XTD

#define CAN_IF1ARB2_XTD   0x00004000

◆ CAN_IF1CMSK_ARB

#define CAN_IF1CMSK_ARB   0x00000020

◆ CAN_IF1CMSK_CLRINTPND

#define CAN_IF1CMSK_CLRINTPND   0x00000008

◆ CAN_IF1CMSK_CONTROL

#define CAN_IF1CMSK_CONTROL   0x00000010

◆ CAN_IF1CMSK_DATAA

#define CAN_IF1CMSK_DATAA   0x00000002

◆ CAN_IF1CMSK_DATAB

#define CAN_IF1CMSK_DATAB   0x00000001

◆ CAN_IF1CMSK_MASK

#define CAN_IF1CMSK_MASK   0x00000040

◆ CAN_IF1CMSK_NEWDAT

#define CAN_IF1CMSK_NEWDAT   0x00000004

◆ CAN_IF1CMSK_TXRQST

#define CAN_IF1CMSK_TXRQST   0x00000004

◆ CAN_IF1CMSK_WRNRD

#define CAN_IF1CMSK_WRNRD   0x00000080

◆ CAN_IF1CRQ_BUSY

#define CAN_IF1CRQ_BUSY   0x00008000

◆ CAN_IF1CRQ_MNUM_M

#define CAN_IF1CRQ_MNUM_M   0x0000003F

◆ CAN_IF1CRQ_MNUM_S

#define CAN_IF1CRQ_MNUM_S   0

◆ CAN_IF1DA1_DATA_M

#define CAN_IF1DA1_DATA_M   0x0000FFFF

◆ CAN_IF1DA1_DATA_S

#define CAN_IF1DA1_DATA_S   0

◆ CAN_IF1DA2_DATA_M

#define CAN_IF1DA2_DATA_M   0x0000FFFF

◆ CAN_IF1DA2_DATA_S

#define CAN_IF1DA2_DATA_S   0

◆ CAN_IF1DB1_DATA_M

#define CAN_IF1DB1_DATA_M   0x0000FFFF

◆ CAN_IF1DB1_DATA_S

#define CAN_IF1DB1_DATA_S   0

◆ CAN_IF1DB2_DATA_M

#define CAN_IF1DB2_DATA_M   0x0000FFFF

◆ CAN_IF1DB2_DATA_S

#define CAN_IF1DB2_DATA_S   0

◆ CAN_IF1MCTL_DLC_M

#define CAN_IF1MCTL_DLC_M   0x0000000F

◆ CAN_IF1MCTL_DLC_S

#define CAN_IF1MCTL_DLC_S   0

◆ CAN_IF1MCTL_EOB

#define CAN_IF1MCTL_EOB   0x00000080

◆ CAN_IF1MCTL_INTPND

#define CAN_IF1MCTL_INTPND   0x00002000

◆ CAN_IF1MCTL_MSGLST

#define CAN_IF1MCTL_MSGLST   0x00004000

◆ CAN_IF1MCTL_NEWDAT

#define CAN_IF1MCTL_NEWDAT   0x00008000

◆ CAN_IF1MCTL_RMTEN

#define CAN_IF1MCTL_RMTEN   0x00000200

◆ CAN_IF1MCTL_RXIE

#define CAN_IF1MCTL_RXIE   0x00000400

◆ CAN_IF1MCTL_TXIE

#define CAN_IF1MCTL_TXIE   0x00000800

◆ CAN_IF1MCTL_TXRQST

#define CAN_IF1MCTL_TXRQST   0x00000100

◆ CAN_IF1MCTL_UMASK

#define CAN_IF1MCTL_UMASK   0x00001000

◆ CAN_IF1MSK1_IDMSK_M

#define CAN_IF1MSK1_IDMSK_M   0x0000FFFF

◆ CAN_IF1MSK1_IDMSK_S

#define CAN_IF1MSK1_IDMSK_S   0

◆ CAN_IF1MSK2_IDMSK_M

#define CAN_IF1MSK2_IDMSK_M   0x00001FFF

◆ CAN_IF1MSK2_IDMSK_S

#define CAN_IF1MSK2_IDMSK_S   0

◆ CAN_IF1MSK2_MDIR

#define CAN_IF1MSK2_MDIR   0x00004000

◆ CAN_IF1MSK2_MXTD

#define CAN_IF1MSK2_MXTD   0x00008000

◆ CAN_IF2ARB1_ID_M

#define CAN_IF2ARB1_ID_M   0x0000FFFF

◆ CAN_IF2ARB1_ID_S

#define CAN_IF2ARB1_ID_S   0

◆ CAN_IF2ARB2_DIR

#define CAN_IF2ARB2_DIR   0x00002000

◆ CAN_IF2ARB2_ID_M

#define CAN_IF2ARB2_ID_M   0x00001FFF

◆ CAN_IF2ARB2_ID_S

#define CAN_IF2ARB2_ID_S   0

◆ CAN_IF2ARB2_MSGVAL

#define CAN_IF2ARB2_MSGVAL   0x00008000

◆ CAN_IF2ARB2_XTD

#define CAN_IF2ARB2_XTD   0x00004000

◆ CAN_IF2CMSK_ARB

#define CAN_IF2CMSK_ARB   0x00000020

◆ CAN_IF2CMSK_CLRINTPND

#define CAN_IF2CMSK_CLRINTPND   0x00000008

◆ CAN_IF2CMSK_CONTROL

#define CAN_IF2CMSK_CONTROL   0x00000010

◆ CAN_IF2CMSK_DATAA

#define CAN_IF2CMSK_DATAA   0x00000002

◆ CAN_IF2CMSK_DATAB

#define CAN_IF2CMSK_DATAB   0x00000001

◆ CAN_IF2CMSK_MASK

#define CAN_IF2CMSK_MASK   0x00000040

◆ CAN_IF2CMSK_NEWDAT

#define CAN_IF2CMSK_NEWDAT   0x00000004

◆ CAN_IF2CMSK_TXRQST

#define CAN_IF2CMSK_TXRQST   0x00000004

◆ CAN_IF2CMSK_WRNRD

#define CAN_IF2CMSK_WRNRD   0x00000080

◆ CAN_IF2CRQ_BUSY

#define CAN_IF2CRQ_BUSY   0x00008000

◆ CAN_IF2CRQ_MNUM_M

#define CAN_IF2CRQ_MNUM_M   0x0000003F

◆ CAN_IF2CRQ_MNUM_S

#define CAN_IF2CRQ_MNUM_S   0

◆ CAN_IF2DA1_DATA_M

#define CAN_IF2DA1_DATA_M   0x0000FFFF

◆ CAN_IF2DA1_DATA_S

#define CAN_IF2DA1_DATA_S   0

◆ CAN_IF2DA2_DATA_M

#define CAN_IF2DA2_DATA_M   0x0000FFFF

◆ CAN_IF2DA2_DATA_S

#define CAN_IF2DA2_DATA_S   0

◆ CAN_IF2DB1_DATA_M

#define CAN_IF2DB1_DATA_M   0x0000FFFF

◆ CAN_IF2DB1_DATA_S

#define CAN_IF2DB1_DATA_S   0

◆ CAN_IF2DB2_DATA_M

#define CAN_IF2DB2_DATA_M   0x0000FFFF

◆ CAN_IF2DB2_DATA_S

#define CAN_IF2DB2_DATA_S   0

◆ CAN_IF2MCTL_DLC_M

#define CAN_IF2MCTL_DLC_M   0x0000000F

◆ CAN_IF2MCTL_DLC_S

#define CAN_IF2MCTL_DLC_S   0

◆ CAN_IF2MCTL_EOB

#define CAN_IF2MCTL_EOB   0x00000080

◆ CAN_IF2MCTL_INTPND

#define CAN_IF2MCTL_INTPND   0x00002000

◆ CAN_IF2MCTL_MSGLST

#define CAN_IF2MCTL_MSGLST   0x00004000

◆ CAN_IF2MCTL_NEWDAT

#define CAN_IF2MCTL_NEWDAT   0x00008000

◆ CAN_IF2MCTL_RMTEN

#define CAN_IF2MCTL_RMTEN   0x00000200

◆ CAN_IF2MCTL_RXIE

#define CAN_IF2MCTL_RXIE   0x00000400

◆ CAN_IF2MCTL_TXIE

#define CAN_IF2MCTL_TXIE   0x00000800

◆ CAN_IF2MCTL_TXRQST

#define CAN_IF2MCTL_TXRQST   0x00000100

◆ CAN_IF2MCTL_UMASK

#define CAN_IF2MCTL_UMASK   0x00001000

◆ CAN_IF2MSK1_IDMSK_M

#define CAN_IF2MSK1_IDMSK_M   0x0000FFFF

◆ CAN_IF2MSK1_IDMSK_S

#define CAN_IF2MSK1_IDMSK_S   0

◆ CAN_IF2MSK2_IDMSK_M

#define CAN_IF2MSK2_IDMSK_M   0x00001FFF

◆ CAN_IF2MSK2_IDMSK_S

#define CAN_IF2MSK2_IDMSK_S   0

◆ CAN_IF2MSK2_MDIR

#define CAN_IF2MSK2_MDIR   0x00004000

◆ CAN_IF2MSK2_MXTD

#define CAN_IF2MSK2_MXTD   0x00008000

◆ CAN_INT_INTID_M

#define CAN_INT_INTID_M   0x0000FFFF

◆ CAN_INT_INTID_NONE

#define CAN_INT_INTID_NONE   0x00000000

◆ CAN_INT_INTID_STATUS

#define CAN_INT_INTID_STATUS   0x00008000

◆ CAN_MSG1INT_INTPND_M

#define CAN_MSG1INT_INTPND_M   0x0000FFFF

◆ CAN_MSG1INT_INTPND_S

#define CAN_MSG1INT_INTPND_S   0

◆ CAN_MSG1VAL_MSGVAL_M

#define CAN_MSG1VAL_MSGVAL_M   0x0000FFFF

◆ CAN_MSG1VAL_MSGVAL_S

#define CAN_MSG1VAL_MSGVAL_S   0

◆ CAN_MSG2INT_INTPND_M

#define CAN_MSG2INT_INTPND_M   0x0000FFFF

◆ CAN_MSG2INT_INTPND_S

#define CAN_MSG2INT_INTPND_S   0

◆ CAN_MSG2VAL_MSGVAL_M

#define CAN_MSG2VAL_MSGVAL_M   0x0000FFFF

◆ CAN_MSG2VAL_MSGVAL_S

#define CAN_MSG2VAL_MSGVAL_S   0

◆ CAN_NWDA1_NEWDAT_M

#define CAN_NWDA1_NEWDAT_M   0x0000FFFF

◆ CAN_NWDA1_NEWDAT_S

#define CAN_NWDA1_NEWDAT_S   0

◆ CAN_NWDA2_NEWDAT_M

#define CAN_NWDA2_NEWDAT_M   0x0000FFFF

◆ CAN_NWDA2_NEWDAT_S

#define CAN_NWDA2_NEWDAT_S   0

◆ CAN_STS_BOFF

#define CAN_STS_BOFF   0x00000080

◆ CAN_STS_EPASS

#define CAN_STS_EPASS   0x00000020

◆ CAN_STS_EWARN

#define CAN_STS_EWARN   0x00000040

◆ CAN_STS_LEC_ACK

#define CAN_STS_LEC_ACK   0x00000003

◆ CAN_STS_LEC_BIT0

#define CAN_STS_LEC_BIT0   0x00000005

◆ CAN_STS_LEC_BIT1

#define CAN_STS_LEC_BIT1   0x00000004

◆ CAN_STS_LEC_CRC

#define CAN_STS_LEC_CRC   0x00000006

◆ CAN_STS_LEC_FORM

#define CAN_STS_LEC_FORM   0x00000002

◆ CAN_STS_LEC_M

#define CAN_STS_LEC_M   0x00000007

◆ CAN_STS_LEC_NOEVENT

#define CAN_STS_LEC_NOEVENT   0x00000007

◆ CAN_STS_LEC_NONE

#define CAN_STS_LEC_NONE   0x00000000

◆ CAN_STS_LEC_STUFF

#define CAN_STS_LEC_STUFF   0x00000001

◆ CAN_STS_RXOK

#define CAN_STS_RXOK   0x00000010

◆ CAN_STS_TXOK

#define CAN_STS_TXOK   0x00000008

◆ CAN_TST_BASIC

#define CAN_TST_BASIC   0x00000004

◆ CAN_TST_LBACK

#define CAN_TST_LBACK   0x00000010

◆ CAN_TST_RX

#define CAN_TST_RX   0x00000080

◆ CAN_TST_SILENT

#define CAN_TST_SILENT   0x00000008

◆ CAN_TST_TX_CANCTL

#define CAN_TST_TX_CANCTL   0x00000000

◆ CAN_TST_TX_DOMINANT

#define CAN_TST_TX_DOMINANT   0x00000040

◆ CAN_TST_TX_M

#define CAN_TST_TX_M   0x00000060

◆ CAN_TST_TX_RECESSIVE

#define CAN_TST_TX_RECESSIVE   0x00000060

◆ CAN_TST_TX_SAMPLE

#define CAN_TST_TX_SAMPLE   0x00000020

◆ CAN_TXRQ1_TXRQST_M

#define CAN_TXRQ1_TXRQST_M   0x0000FFFF

◆ CAN_TXRQ1_TXRQST_S

#define CAN_TXRQ1_TXRQST_S   0

◆ CAN_TXRQ2_TXRQST_M

#define CAN_TXRQ2_TXRQST_M   0x0000FFFF

◆ CAN_TXRQ2_TXRQST_S

#define CAN_TXRQ2_TXRQST_S   0

◆ COMP_ACCTL0_ASRCP_M

#define COMP_ACCTL0_ASRCP_M   0x00000600

◆ COMP_ACCTL0_ASRCP_PIN

#define COMP_ACCTL0_ASRCP_PIN   0x00000000

◆ COMP_ACCTL0_ASRCP_PIN0

#define COMP_ACCTL0_ASRCP_PIN0   0x00000200

◆ COMP_ACCTL0_ASRCP_REF

#define COMP_ACCTL0_ASRCP_REF   0x00000400

◆ COMP_ACCTL0_CINV

#define COMP_ACCTL0_CINV   0x00000002

◆ COMP_ACCTL0_ISEN_BOTH

#define COMP_ACCTL0_ISEN_BOTH   0x0000000C

◆ COMP_ACCTL0_ISEN_FALL

#define COMP_ACCTL0_ISEN_FALL   0x00000004

◆ COMP_ACCTL0_ISEN_LEVEL

#define COMP_ACCTL0_ISEN_LEVEL   0x00000000

◆ COMP_ACCTL0_ISEN_M

#define COMP_ACCTL0_ISEN_M   0x0000000C

◆ COMP_ACCTL0_ISEN_RISE

#define COMP_ACCTL0_ISEN_RISE   0x00000008

◆ COMP_ACCTL0_ISLVAL

#define COMP_ACCTL0_ISLVAL   0x00000010

◆ COMP_ACCTL0_R

#define COMP_ACCTL0_R   (*((volatile u32 *)0x4003C024))

◆ COMP_ACCTL0_TOEN

#define COMP_ACCTL0_TOEN   0x00000800

◆ COMP_ACCTL0_TSEN_BOTH

#define COMP_ACCTL0_TSEN_BOTH   0x00000060

◆ COMP_ACCTL0_TSEN_FALL

#define COMP_ACCTL0_TSEN_FALL   0x00000020

◆ COMP_ACCTL0_TSEN_LEVEL

#define COMP_ACCTL0_TSEN_LEVEL   0x00000000

◆ COMP_ACCTL0_TSEN_M

#define COMP_ACCTL0_TSEN_M   0x00000060

◆ COMP_ACCTL0_TSEN_RISE

#define COMP_ACCTL0_TSEN_RISE   0x00000040

◆ COMP_ACCTL0_TSLVAL

#define COMP_ACCTL0_TSLVAL   0x00000080

◆ COMP_ACCTL1_ASRCP_M

#define COMP_ACCTL1_ASRCP_M   0x00000600

◆ COMP_ACCTL1_ASRCP_PIN

#define COMP_ACCTL1_ASRCP_PIN   0x00000000

◆ COMP_ACCTL1_ASRCP_PIN0

#define COMP_ACCTL1_ASRCP_PIN0   0x00000200

◆ COMP_ACCTL1_ASRCP_REF

#define COMP_ACCTL1_ASRCP_REF   0x00000400

◆ COMP_ACCTL1_CINV

#define COMP_ACCTL1_CINV   0x00000002

◆ COMP_ACCTL1_ISEN_BOTH

#define COMP_ACCTL1_ISEN_BOTH   0x0000000C

◆ COMP_ACCTL1_ISEN_FALL

#define COMP_ACCTL1_ISEN_FALL   0x00000004

◆ COMP_ACCTL1_ISEN_LEVEL

#define COMP_ACCTL1_ISEN_LEVEL   0x00000000

◆ COMP_ACCTL1_ISEN_M

#define COMP_ACCTL1_ISEN_M   0x0000000C

◆ COMP_ACCTL1_ISEN_RISE

#define COMP_ACCTL1_ISEN_RISE   0x00000008

◆ COMP_ACCTL1_ISLVAL

#define COMP_ACCTL1_ISLVAL   0x00000010

◆ COMP_ACCTL1_R

#define COMP_ACCTL1_R   (*((volatile u32 *)0x4003C044))

◆ COMP_ACCTL1_TOEN

#define COMP_ACCTL1_TOEN   0x00000800

◆ COMP_ACCTL1_TSEN_BOTH

#define COMP_ACCTL1_TSEN_BOTH   0x00000060

◆ COMP_ACCTL1_TSEN_FALL

#define COMP_ACCTL1_TSEN_FALL   0x00000020

◆ COMP_ACCTL1_TSEN_LEVEL

#define COMP_ACCTL1_TSEN_LEVEL   0x00000000

◆ COMP_ACCTL1_TSEN_M

#define COMP_ACCTL1_TSEN_M   0x00000060

◆ COMP_ACCTL1_TSEN_RISE

#define COMP_ACCTL1_TSEN_RISE   0x00000040

◆ COMP_ACCTL1_TSLVAL

#define COMP_ACCTL1_TSLVAL   0x00000080

◆ COMP_ACINTEN_IN0

#define COMP_ACINTEN_IN0   0x00000001

◆ COMP_ACINTEN_IN1

#define COMP_ACINTEN_IN1   0x00000002

◆ COMP_ACINTEN_R

#define COMP_ACINTEN_R   (*((volatile u32 *)0x4003C008))

◆ COMP_ACMIS_IN0

#define COMP_ACMIS_IN0   0x00000001

◆ COMP_ACMIS_IN1

#define COMP_ACMIS_IN1   0x00000002

◆ COMP_ACMIS_R

#define COMP_ACMIS_R   (*((volatile u32 *)0x4003C000))

◆ COMP_ACREFCTL_EN

#define COMP_ACREFCTL_EN   0x00000200

◆ COMP_ACREFCTL_R

#define COMP_ACREFCTL_R   (*((volatile u32 *)0x4003C010))

◆ COMP_ACREFCTL_RNG

#define COMP_ACREFCTL_RNG   0x00000100

◆ COMP_ACREFCTL_VREF_M

#define COMP_ACREFCTL_VREF_M   0x0000000F

◆ COMP_ACREFCTL_VREF_S

#define COMP_ACREFCTL_VREF_S   0

◆ COMP_ACRIS_IN0

#define COMP_ACRIS_IN0   0x00000001

◆ COMP_ACRIS_IN1

#define COMP_ACRIS_IN1   0x00000002

◆ COMP_ACRIS_R

#define COMP_ACRIS_R   (*((volatile u32 *)0x4003C004))

◆ COMP_ACSTAT0_OVAL

#define COMP_ACSTAT0_OVAL   0x00000002

◆ COMP_ACSTAT0_R

#define COMP_ACSTAT0_R   (*((volatile u32 *)0x4003C020))

◆ COMP_ACSTAT1_OVAL

#define COMP_ACSTAT1_OVAL   0x00000002

◆ COMP_ACSTAT1_R

#define COMP_ACSTAT1_R   (*((volatile u32 *)0x4003C040))

◆ COMP_PP_C0O

#define COMP_PP_C0O   0x00010000

◆ COMP_PP_C1O

#define COMP_PP_C1O   0x00020000

◆ COMP_PP_CMP0

#define COMP_PP_CMP0   0x00000001

◆ COMP_PP_CMP1

#define COMP_PP_CMP1   0x00000002

◆ COMP_PP_R

#define COMP_PP_R   (*((volatile u32 *)0x4003CFC0))

◆ EEPROM_EEBLOCK_BLOCK_M

#define EEPROM_EEBLOCK_BLOCK_M   0x0000FFFF

◆ EEPROM_EEBLOCK_BLOCK_S

#define EEPROM_EEBLOCK_BLOCK_S   0

◆ EEPROM_EEBLOCK_R

#define EEPROM_EEBLOCK_R   (*((volatile u32 *)0x400AF004))

◆ EEPROM_EEDBGME_KEY_M

#define EEPROM_EEDBGME_KEY_M   0xFFFF0000

◆ EEPROM_EEDBGME_KEY_S

#define EEPROM_EEDBGME_KEY_S   16

◆ EEPROM_EEDBGME_ME

#define EEPROM_EEDBGME_ME   0x00000001

◆ EEPROM_EEDBGME_R

#define EEPROM_EEDBGME_R   (*((volatile u32 *)0x400AF080))

◆ EEPROM_EEDONE_NOPERM

#define EEPROM_EEDONE_NOPERM   0x00000010

◆ EEPROM_EEDONE_R

#define EEPROM_EEDONE_R   (*((volatile u32 *)0x400AF018))

◆ EEPROM_EEDONE_WKCOPY

#define EEPROM_EEDONE_WKCOPY   0x00000008

◆ EEPROM_EEDONE_WKERASE

#define EEPROM_EEDONE_WKERASE   0x00000004

◆ EEPROM_EEDONE_WORKING

#define EEPROM_EEDONE_WORKING   0x00000001

◆ EEPROM_EEDONE_WRBUSY

#define EEPROM_EEDONE_WRBUSY   0x00000020

◆ EEPROM_EEHIDE_HN_M

#define EEPROM_EEHIDE_HN_M   0xFFFFFFFE

◆ EEPROM_EEHIDE_R

#define EEPROM_EEHIDE_R   (*((volatile u32 *)0x400AF050))

◆ EEPROM_EEINT_INT

#define EEPROM_EEINT_INT   0x00000001

◆ EEPROM_EEINT_R

#define EEPROM_EEINT_R   (*((volatile u32 *)0x400AF040))

◆ EEPROM_EEOFFSET_OFFSET_M

#define EEPROM_EEOFFSET_OFFSET_M    0x0000000F

◆ EEPROM_EEOFFSET_OFFSET_S

#define EEPROM_EEOFFSET_OFFSET_S    0

◆ EEPROM_EEOFFSET_R

#define EEPROM_EEOFFSET_R   (*((volatile u32 *)0x400AF008))

◆ EEPROM_EEPASS0_PASS_M

#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF

◆ EEPROM_EEPASS0_PASS_S

#define EEPROM_EEPASS0_PASS_S   0

◆ EEPROM_EEPASS0_R

#define EEPROM_EEPASS0_R   (*((volatile u32 *)0x400AF034))

◆ EEPROM_EEPASS1_PASS_M

#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF

◆ EEPROM_EEPASS1_PASS_S

#define EEPROM_EEPASS1_PASS_S   0

◆ EEPROM_EEPASS1_R

#define EEPROM_EEPASS1_R   (*((volatile u32 *)0x400AF038))

◆ EEPROM_EEPASS2_PASS_M

#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF

◆ EEPROM_EEPASS2_PASS_S

#define EEPROM_EEPASS2_PASS_S   0

◆ EEPROM_EEPASS2_R

#define EEPROM_EEPASS2_R   (*((volatile u32 *)0x400AF03C))

◆ EEPROM_EEPROT_ACC

#define EEPROM_EEPROT_ACC   0x00000008

◆ EEPROM_EEPROT_PROT_M

#define EEPROM_EEPROT_PROT_M   0x00000007

◆ EEPROM_EEPROT_PROT_RONPW

#define EEPROM_EEPROT_PROT_RONPW    0x00000002

◆ EEPROM_EEPROT_PROT_RWNPW

#define EEPROM_EEPROT_PROT_RWNPW    0x00000000

◆ EEPROM_EEPROT_PROT_RWPW

#define EEPROM_EEPROT_PROT_RWPW   0x00000001

◆ EEPROM_EEPROT_R

#define EEPROM_EEPROT_R   (*((volatile u32 *)0x400AF030))

◆ EEPROM_EERDWR_R

#define EEPROM_EERDWR_R   (*((volatile u32 *)0x400AF010))

◆ EEPROM_EERDWR_VALUE_M

#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF

◆ EEPROM_EERDWR_VALUE_S

#define EEPROM_EERDWR_VALUE_S   0

◆ EEPROM_EERDWRINC_R

#define EEPROM_EERDWRINC_R   (*((volatile u32 *)0x400AF014))

◆ EEPROM_EERDWRINC_VALUE_M

#define EEPROM_EERDWRINC_VALUE_M    0xFFFFFFFF

◆ EEPROM_EERDWRINC_VALUE_S

#define EEPROM_EERDWRINC_VALUE_S    0

◆ EEPROM_EESIZE_BLKCNT_M

#define EEPROM_EESIZE_BLKCNT_M   0x07FF0000

◆ EEPROM_EESIZE_BLKCNT_S

#define EEPROM_EESIZE_BLKCNT_S   16

◆ EEPROM_EESIZE_R

#define EEPROM_EESIZE_R   (*((volatile u32 *)0x400AF000))

◆ EEPROM_EESIZE_WORDCNT_M

#define EEPROM_EESIZE_WORDCNT_M   0x0000FFFF

◆ EEPROM_EESIZE_WORDCNT_S

#define EEPROM_EESIZE_WORDCNT_S   0

◆ EEPROM_EESUPP_ERETRY

#define EEPROM_EESUPP_ERETRY   0x00000004

◆ EEPROM_EESUPP_PRETRY

#define EEPROM_EESUPP_PRETRY   0x00000008

◆ EEPROM_EESUPP_R

#define EEPROM_EESUPP_R   (*((volatile u32 *)0x400AF01C))

◆ EEPROM_EEUNLOCK_R

#define EEPROM_EEUNLOCK_R   (*((volatile u32 *)0x400AF020))

◆ EEPROM_EEUNLOCK_UNLOCK_M

#define EEPROM_EEUNLOCK_UNLOCK_M    0xFFFFFFFF

◆ EEPROM_PP_R

#define EEPROM_PP_R   (*((volatile u32 *)0x400AFFC0))

◆ EEPROM_PP_SIZE_M

#define EEPROM_PP_SIZE_M   0x0000001F

◆ EEPROM_PP_SIZE_S

#define EEPROM_PP_SIZE_S   0

◆ FLASH_BOOTCFG_DBG0

#define FLASH_BOOTCFG_DBG0   0x00000001

◆ FLASH_BOOTCFG_DBG1

#define FLASH_BOOTCFG_DBG1   0x00000002

◆ FLASH_BOOTCFG_EN

#define FLASH_BOOTCFG_EN   0x00000100

◆ FLASH_BOOTCFG_KEY

#define FLASH_BOOTCFG_KEY   0x00000010

◆ FLASH_BOOTCFG_NW

#define FLASH_BOOTCFG_NW   0x80000000

◆ FLASH_BOOTCFG_PIN_0

#define FLASH_BOOTCFG_PIN_0   0x00000000

◆ FLASH_BOOTCFG_PIN_1

#define FLASH_BOOTCFG_PIN_1   0x00000400

◆ FLASH_BOOTCFG_PIN_2

#define FLASH_BOOTCFG_PIN_2   0x00000800

◆ FLASH_BOOTCFG_PIN_3

#define FLASH_BOOTCFG_PIN_3   0x00000C00

◆ FLASH_BOOTCFG_PIN_4

#define FLASH_BOOTCFG_PIN_4   0x00001000

◆ FLASH_BOOTCFG_PIN_5

#define FLASH_BOOTCFG_PIN_5   0x00001400

◆ FLASH_BOOTCFG_PIN_6

#define FLASH_BOOTCFG_PIN_6   0x00001800

◆ FLASH_BOOTCFG_PIN_7

#define FLASH_BOOTCFG_PIN_7   0x00001C00

◆ FLASH_BOOTCFG_PIN_M

#define FLASH_BOOTCFG_PIN_M   0x00001C00

◆ FLASH_BOOTCFG_POL

#define FLASH_BOOTCFG_POL   0x00000200

◆ FLASH_BOOTCFG_PORT_A

#define FLASH_BOOTCFG_PORT_A   0x00000000

◆ FLASH_BOOTCFG_PORT_B

#define FLASH_BOOTCFG_PORT_B   0x00002000

◆ FLASH_BOOTCFG_PORT_C

#define FLASH_BOOTCFG_PORT_C   0x00004000

◆ FLASH_BOOTCFG_PORT_D

#define FLASH_BOOTCFG_PORT_D   0x00006000

◆ FLASH_BOOTCFG_PORT_E

#define FLASH_BOOTCFG_PORT_E   0x00008000

◆ FLASH_BOOTCFG_PORT_F

#define FLASH_BOOTCFG_PORT_F   0x0000A000

◆ FLASH_BOOTCFG_PORT_G

#define FLASH_BOOTCFG_PORT_G   0x0000C000

◆ FLASH_BOOTCFG_PORT_H

#define FLASH_BOOTCFG_PORT_H   0x0000E000

◆ FLASH_BOOTCFG_PORT_M

#define FLASH_BOOTCFG_PORT_M   0x0000E000

◆ FLASH_BOOTCFG_R

#define FLASH_BOOTCFG_R   (*((volatile u32 *)0x400FE1D0))

◆ FLASH_FCIM_AMASK

#define FLASH_FCIM_AMASK   0x00000001

◆ FLASH_FCIM_EMASK

#define FLASH_FCIM_EMASK   0x00000004

◆ FLASH_FCIM_ERMASK

#define FLASH_FCIM_ERMASK   0x00000800

◆ FLASH_FCIM_INVDMASK

#define FLASH_FCIM_INVDMASK   0x00000400

◆ FLASH_FCIM_PMASK

#define FLASH_FCIM_PMASK   0x00000002

◆ FLASH_FCIM_PROGMASK

#define FLASH_FCIM_PROGMASK   0x00002000

◆ FLASH_FCIM_R

#define FLASH_FCIM_R   (*((volatile u32 *)0x400FD010))

◆ FLASH_FCIM_VOLTMASK

#define FLASH_FCIM_VOLTMASK   0x00000200

◆ FLASH_FCMISC_AMISC

#define FLASH_FCMISC_AMISC   0x00000001

◆ FLASH_FCMISC_EMISC

#define FLASH_FCMISC_EMISC   0x00000004

◆ FLASH_FCMISC_ERMISC

#define FLASH_FCMISC_ERMISC   0x00000800

◆ FLASH_FCMISC_INVDMISC

#define FLASH_FCMISC_INVDMISC   0x00000400

◆ FLASH_FCMISC_PMISC

#define FLASH_FCMISC_PMISC   0x00000002

◆ FLASH_FCMISC_PROGMISC

#define FLASH_FCMISC_PROGMISC   0x00002000

◆ FLASH_FCMISC_R

#define FLASH_FCMISC_R   (*((volatile u32 *)0x400FD014))

◆ FLASH_FCMISC_VOLTMISC

#define FLASH_FCMISC_VOLTMISC   0x00000200

◆ FLASH_FCRIS_ARIS

#define FLASH_FCRIS_ARIS   0x00000001

◆ FLASH_FCRIS_ERIS

#define FLASH_FCRIS_ERIS   0x00000004

◆ FLASH_FCRIS_ERRIS

#define FLASH_FCRIS_ERRIS   0x00000800

◆ FLASH_FCRIS_INVDRIS

#define FLASH_FCRIS_INVDRIS   0x00000400

◆ FLASH_FCRIS_PRIS

#define FLASH_FCRIS_PRIS   0x00000002

◆ FLASH_FCRIS_PROGRIS

#define FLASH_FCRIS_PROGRIS   0x00002000

◆ FLASH_FCRIS_R

#define FLASH_FCRIS_R   (*((volatile u32 *)0x400FD00C))

◆ FLASH_FCRIS_VOLTRIS

#define FLASH_FCRIS_VOLTRIS   0x00000200

◆ FLASH_FMA_OFFSET_M

#define FLASH_FMA_OFFSET_M   0x0003FFFF

◆ FLASH_FMA_OFFSET_S

#define FLASH_FMA_OFFSET_S   0

◆ FLASH_FMA_R

#define FLASH_FMA_R   (*((volatile u32 *)0x400FD000))

◆ FLASH_FMC2_R

#define FLASH_FMC2_R   (*((volatile u32 *)0x400FD020))

◆ FLASH_FMC2_WRBUF

#define FLASH_FMC2_WRBUF   0x00000001

◆ FLASH_FMC_COMT

#define FLASH_FMC_COMT   0x00000008

◆ FLASH_FMC_ERASE

#define FLASH_FMC_ERASE   0x00000002

◆ FLASH_FMC_MERASE

#define FLASH_FMC_MERASE   0x00000004

◆ FLASH_FMC_R

#define FLASH_FMC_R   (*((volatile u32 *)0x400FD008))

◆ FLASH_FMC_WRITE

#define FLASH_FMC_WRITE   0x00000001

◆ FLASH_FMC_WRKEY

#define FLASH_FMC_WRKEY   0xA4420000

◆ FLASH_FMD_DATA_M

#define FLASH_FMD_DATA_M   0xFFFFFFFF

◆ FLASH_FMD_DATA_S

#define FLASH_FMD_DATA_S   0

◆ FLASH_FMD_R

#define FLASH_FMD_R   (*((volatile u32 *)0x400FD004))

◆ FLASH_FMPPE0_R

#define FLASH_FMPPE0_R   (*((volatile u32 *)0x400FE400))

◆ FLASH_FMPPE1_R

#define FLASH_FMPPE1_R   (*((volatile u32 *)0x400FE404))

◆ FLASH_FMPPE2_R

#define FLASH_FMPPE2_R   (*((volatile u32 *)0x400FE408))

◆ FLASH_FMPPE3_R

#define FLASH_FMPPE3_R   (*((volatile u32 *)0x400FE40C))

◆ FLASH_FMPRE0_R

#define FLASH_FMPRE0_R   (*((volatile u32 *)0x400FE200))

◆ FLASH_FMPRE1_R

#define FLASH_FMPRE1_R   (*((volatile u32 *)0x400FE204))

◆ FLASH_FMPRE2_R

#define FLASH_FMPRE2_R   (*((volatile u32 *)0x400FE208))

◆ FLASH_FMPRE3_R

#define FLASH_FMPRE3_R   (*((volatile u32 *)0x400FE20C))

◆ FLASH_FSIZE_R

#define FLASH_FSIZE_R   (*((volatile u32 *)0x400FDFC0))

◆ FLASH_FSIZE_SIZE_256KB

#define FLASH_FSIZE_SIZE_256KB   0x0000007F

◆ FLASH_FSIZE_SIZE_M

#define FLASH_FSIZE_SIZE_M   0x0000FFFF

◆ FLASH_FWBN_DATA_M

#define FLASH_FWBN_DATA_M   0xFFFFFFFF

◆ FLASH_FWBN_R

#define FLASH_FWBN_R   (*((volatile u32 *)0x400FD100))

◆ FLASH_FWBVAL_FWB_M

#define FLASH_FWBVAL_FWB_M   0xFFFFFFFF

◆ FLASH_FWBVAL_R

#define FLASH_FWBVAL_R   (*((volatile u32 *)0x400FD030))

◆ FLASH_RMCTL_BA

#define FLASH_RMCTL_BA   0x00000001

◆ FLASH_RMCTL_R

#define FLASH_RMCTL_R   (*((volatile u32 *)0x400FE0F0))

◆ FLASH_ROMSWMAP_R

#define FLASH_ROMSWMAP_R   (*((volatile u32 *)0x400FDFCC))

◆ FLASH_ROMSWMAP_SAFERTOS

#define FLASH_ROMSWMAP_SAFERTOS   0x00000001

◆ FLASH_SSIZE_R

#define FLASH_SSIZE_R   (*((volatile u32 *)0x400FDFC4))

◆ FLASH_SSIZE_SIZE_32KB

#define FLASH_SSIZE_SIZE_32KB   0x0000007F

◆ FLASH_SSIZE_SIZE_M

#define FLASH_SSIZE_SIZE_M   0x0000FFFF

◆ FLASH_USERREG0_DATA_M

#define FLASH_USERREG0_DATA_M   0xFFFFFFFF

◆ FLASH_USERREG0_DATA_S

#define FLASH_USERREG0_DATA_S   0

◆ FLASH_USERREG0_R

#define FLASH_USERREG0_R   (*((volatile u32 *)0x400FE1E0))

◆ FLASH_USERREG1_DATA_M

#define FLASH_USERREG1_DATA_M   0xFFFFFFFF

◆ FLASH_USERREG1_DATA_S

#define FLASH_USERREG1_DATA_S   0

◆ FLASH_USERREG1_R

#define FLASH_USERREG1_R   (*((volatile u32 *)0x400FE1E4))

◆ FLASH_USERREG2_DATA_M

#define FLASH_USERREG2_DATA_M   0xFFFFFFFF

◆ FLASH_USERREG2_DATA_S

#define FLASH_USERREG2_DATA_S   0

◆ FLASH_USERREG2_R

#define FLASH_USERREG2_R   (*((volatile u32 *)0x400FE1E8))

◆ FLASH_USERREG3_DATA_M

#define FLASH_USERREG3_DATA_M   0xFFFFFFFF

◆ FLASH_USERREG3_DATA_S

#define FLASH_USERREG3_DATA_S   0

◆ FLASH_USERREG3_R

#define FLASH_USERREG3_R   (*((volatile u32 *)0x400FE1EC))

◆ GPIO_ICR_GPIO_M

#define GPIO_ICR_GPIO_M   0x000000FF

◆ GPIO_ICR_GPIO_S

#define GPIO_ICR_GPIO_S   0

◆ GPIO_IM_GPIO_M

#define GPIO_IM_GPIO_M   0x000000FF

◆ GPIO_IM_GPIO_S

#define GPIO_IM_GPIO_S   0

◆ GPIO_LOCK_KEY

#define GPIO_LOCK_KEY   0x4C4F434B

◆ GPIO_LOCK_LOCKED

#define GPIO_LOCK_LOCKED   0x00000001

◆ GPIO_LOCK_M

#define GPIO_LOCK_M   0xFFFFFFFF

◆ GPIO_LOCK_UNLOCKED

#define GPIO_LOCK_UNLOCKED   0x00000000

◆ GPIO_MIS_GPIO_M

#define GPIO_MIS_GPIO_M   0x000000FF

◆ GPIO_MIS_GPIO_S

#define GPIO_MIS_GPIO_S   0

◆ GPIO_PCTL_PA0_CAN1RX

#define GPIO_PCTL_PA0_CAN1RX   0x00000008

◆ GPIO_PCTL_PA0_M

#define GPIO_PCTL_PA0_M   0x0000000F

◆ GPIO_PCTL_PA0_U0RX

#define GPIO_PCTL_PA0_U0RX   0x00000001

◆ GPIO_PCTL_PA1_CAN1TX

#define GPIO_PCTL_PA1_CAN1TX   0x00000080

◆ GPIO_PCTL_PA1_M

#define GPIO_PCTL_PA1_M   0x000000F0

◆ GPIO_PCTL_PA1_U0TX

#define GPIO_PCTL_PA1_U0TX   0x00000010

◆ GPIO_PCTL_PA2_M

#define GPIO_PCTL_PA2_M   0x00000F00

◆ GPIO_PCTL_PA2_SSI0CLK

#define GPIO_PCTL_PA2_SSI0CLK   0x00000200

◆ GPIO_PCTL_PA3_M

#define GPIO_PCTL_PA3_M   0x0000F000

◆ GPIO_PCTL_PA3_SSI0FSS

#define GPIO_PCTL_PA3_SSI0FSS   0x00002000

◆ GPIO_PCTL_PA4_M

#define GPIO_PCTL_PA4_M   0x000F0000

◆ GPIO_PCTL_PA4_SSI0RX

#define GPIO_PCTL_PA4_SSI0RX   0x00020000

◆ GPIO_PCTL_PA5_M

#define GPIO_PCTL_PA5_M   0x00F00000

◆ GPIO_PCTL_PA5_SSI0TX

#define GPIO_PCTL_PA5_SSI0TX   0x00200000

◆ GPIO_PCTL_PA6_I2C1SCL

#define GPIO_PCTL_PA6_I2C1SCL   0x03000000

◆ GPIO_PCTL_PA6_M

#define GPIO_PCTL_PA6_M   0x0F000000

◆ GPIO_PCTL_PA6_M1PWM2

#define GPIO_PCTL_PA6_M1PWM2   0x05000000

◆ GPIO_PCTL_PA7_I2C1SDA

#define GPIO_PCTL_PA7_I2C1SDA   0x30000000

◆ GPIO_PCTL_PA7_M

#define GPIO_PCTL_PA7_M   0xF0000000

◆ GPIO_PCTL_PA7_M1PWM3

#define GPIO_PCTL_PA7_M1PWM3   0x50000000

◆ GPIO_PCTL_PB0_M

#define GPIO_PCTL_PB0_M   0x0000000F

◆ GPIO_PCTL_PB0_T2CCP0

#define GPIO_PCTL_PB0_T2CCP0   0x00000007

◆ GPIO_PCTL_PB0_U1RX

#define GPIO_PCTL_PB0_U1RX   0x00000001

◆ GPIO_PCTL_PB0_USB0ID

#define GPIO_PCTL_PB0_USB0ID   0x00000000

◆ GPIO_PCTL_PB1_M

#define GPIO_PCTL_PB1_M   0x000000F0

◆ GPIO_PCTL_PB1_T2CCP1

#define GPIO_PCTL_PB1_T2CCP1   0x00000070

◆ GPIO_PCTL_PB1_U1TX

#define GPIO_PCTL_PB1_U1TX   0x00000010

◆ GPIO_PCTL_PB1_USB0VBUS

#define GPIO_PCTL_PB1_USB0VBUS   0x00000000

◆ GPIO_PCTL_PB2_I2C0SCL

#define GPIO_PCTL_PB2_I2C0SCL   0x00000300

◆ GPIO_PCTL_PB2_M

#define GPIO_PCTL_PB2_M   0x00000F00

◆ GPIO_PCTL_PB2_T3CCP0

#define GPIO_PCTL_PB2_T3CCP0   0x00000700

◆ GPIO_PCTL_PB3_I2C0SDA

#define GPIO_PCTL_PB3_I2C0SDA   0x00003000

◆ GPIO_PCTL_PB3_M

#define GPIO_PCTL_PB3_M   0x0000F000

◆ GPIO_PCTL_PB3_T3CCP1

#define GPIO_PCTL_PB3_T3CCP1   0x00007000

◆ GPIO_PCTL_PB4_CAN0RX

#define GPIO_PCTL_PB4_CAN0RX   0x00080000

◆ GPIO_PCTL_PB4_M

#define GPIO_PCTL_PB4_M   0x000F0000

◆ GPIO_PCTL_PB4_M0PWM2

#define GPIO_PCTL_PB4_M0PWM2   0x00040000

◆ GPIO_PCTL_PB4_SSI2CLK

#define GPIO_PCTL_PB4_SSI2CLK   0x00020000

◆ GPIO_PCTL_PB4_T1CCP0

#define GPIO_PCTL_PB4_T1CCP0   0x00070000

◆ GPIO_PCTL_PB5_CAN0TX

#define GPIO_PCTL_PB5_CAN0TX   0x00800000

◆ GPIO_PCTL_PB5_M

#define GPIO_PCTL_PB5_M   0x00F00000

◆ GPIO_PCTL_PB5_M0PWM3

#define GPIO_PCTL_PB5_M0PWM3   0x00400000

◆ GPIO_PCTL_PB5_SSI2FSS

#define GPIO_PCTL_PB5_SSI2FSS   0x00200000

◆ GPIO_PCTL_PB5_T1CCP1

#define GPIO_PCTL_PB5_T1CCP1   0x00700000

◆ GPIO_PCTL_PB6_M

#define GPIO_PCTL_PB6_M   0x0F000000

◆ GPIO_PCTL_PB6_M0PWM0

#define GPIO_PCTL_PB6_M0PWM0   0x04000000

◆ GPIO_PCTL_PB6_SSI2RX

#define GPIO_PCTL_PB6_SSI2RX   0x02000000

◆ GPIO_PCTL_PB6_T0CCP0

#define GPIO_PCTL_PB6_T0CCP0   0x07000000

◆ GPIO_PCTL_PB7_M

#define GPIO_PCTL_PB7_M   0xF0000000

◆ GPIO_PCTL_PB7_M0PWM1

#define GPIO_PCTL_PB7_M0PWM1   0x40000000

◆ GPIO_PCTL_PB7_SSI2TX

#define GPIO_PCTL_PB7_SSI2TX   0x20000000

◆ GPIO_PCTL_PB7_T0CCP1

#define GPIO_PCTL_PB7_T0CCP1   0x70000000

◆ GPIO_PCTL_PC0_M

#define GPIO_PCTL_PC0_M   0x0000000F

◆ GPIO_PCTL_PC0_T4CCP0

#define GPIO_PCTL_PC0_T4CCP0   0x00000007

◆ GPIO_PCTL_PC0_TCK

#define GPIO_PCTL_PC0_TCK   0x00000001

◆ GPIO_PCTL_PC1_M

#define GPIO_PCTL_PC1_M   0x000000F0

◆ GPIO_PCTL_PC1_T4CCP1

#define GPIO_PCTL_PC1_T4CCP1   0x00000070

◆ GPIO_PCTL_PC1_TMS

#define GPIO_PCTL_PC1_TMS   0x00000010

◆ GPIO_PCTL_PC2_M

#define GPIO_PCTL_PC2_M   0x00000F00

◆ GPIO_PCTL_PC2_T5CCP0

#define GPIO_PCTL_PC2_T5CCP0   0x00000700

◆ GPIO_PCTL_PC2_TDI

#define GPIO_PCTL_PC2_TDI   0x00000100

◆ GPIO_PCTL_PC3_M

#define GPIO_PCTL_PC3_M   0x0000F000

◆ GPIO_PCTL_PC3_T5CCP1

#define GPIO_PCTL_PC3_T5CCP1   0x00007000

◆ GPIO_PCTL_PC3_TDO

#define GPIO_PCTL_PC3_TDO   0x00001000

◆ GPIO_PCTL_PC4_IDX1

#define GPIO_PCTL_PC4_IDX1   0x00060000

◆ GPIO_PCTL_PC4_M

#define GPIO_PCTL_PC4_M   0x000F0000

◆ GPIO_PCTL_PC4_M0PWM6

#define GPIO_PCTL_PC4_M0PWM6   0x00040000

◆ GPIO_PCTL_PC4_U1RTS

#define GPIO_PCTL_PC4_U1RTS   0x00080000

◆ GPIO_PCTL_PC4_U1RX

#define GPIO_PCTL_PC4_U1RX   0x00020000

◆ GPIO_PCTL_PC4_U4RX

#define GPIO_PCTL_PC4_U4RX   0x00010000

◆ GPIO_PCTL_PC4_WT0CCP0

#define GPIO_PCTL_PC4_WT0CCP0   0x00070000

◆ GPIO_PCTL_PC5_M

#define GPIO_PCTL_PC5_M   0x00F00000

◆ GPIO_PCTL_PC5_M0PWM7

#define GPIO_PCTL_PC5_M0PWM7   0x00400000

◆ GPIO_PCTL_PC5_PHA1

#define GPIO_PCTL_PC5_PHA1   0x00600000

◆ GPIO_PCTL_PC5_U1CTS

#define GPIO_PCTL_PC5_U1CTS   0x00800000

◆ GPIO_PCTL_PC5_U1TX

#define GPIO_PCTL_PC5_U1TX   0x00200000

◆ GPIO_PCTL_PC5_U4TX

#define GPIO_PCTL_PC5_U4TX   0x00100000

◆ GPIO_PCTL_PC5_WT0CCP1

#define GPIO_PCTL_PC5_WT0CCP1   0x00700000

◆ GPIO_PCTL_PC6_M

#define GPIO_PCTL_PC6_M   0x0F000000

◆ GPIO_PCTL_PC6_PHB1

#define GPIO_PCTL_PC6_PHB1   0x06000000

◆ GPIO_PCTL_PC6_U3RX

#define GPIO_PCTL_PC6_U3RX   0x01000000

◆ GPIO_PCTL_PC6_USB0EPEN

#define GPIO_PCTL_PC6_USB0EPEN   0x08000000

◆ GPIO_PCTL_PC6_WT1CCP0

#define GPIO_PCTL_PC6_WT1CCP0   0x07000000

◆ GPIO_PCTL_PC7_M

#define GPIO_PCTL_PC7_M   0xF0000000

◆ GPIO_PCTL_PC7_U3TX

#define GPIO_PCTL_PC7_U3TX   0x10000000

◆ GPIO_PCTL_PC7_USB0PFLT

#define GPIO_PCTL_PC7_USB0PFLT   0x80000000

◆ GPIO_PCTL_PC7_WT1CCP1

#define GPIO_PCTL_PC7_WT1CCP1   0x70000000

◆ GPIO_PCTL_PD0_AIN7

#define GPIO_PCTL_PD0_AIN7   0x00000000

◆ GPIO_PCTL_PD0_I2C3SCL

#define GPIO_PCTL_PD0_I2C3SCL   0x00000003

◆ GPIO_PCTL_PD0_M

#define GPIO_PCTL_PD0_M   0x0000000F

◆ GPIO_PCTL_PD0_M0PWM6

#define GPIO_PCTL_PD0_M0PWM6   0x00000004

◆ GPIO_PCTL_PD0_M1PWM0

#define GPIO_PCTL_PD0_M1PWM0   0x00000005

◆ GPIO_PCTL_PD0_SSI1CLK

#define GPIO_PCTL_PD0_SSI1CLK   0x00000002

◆ GPIO_PCTL_PD0_SSI3CLK

#define GPIO_PCTL_PD0_SSI3CLK   0x00000001

◆ GPIO_PCTL_PD0_WT2CCP0

#define GPIO_PCTL_PD0_WT2CCP0   0x00000007

◆ GPIO_PCTL_PD1_AIN6

#define GPIO_PCTL_PD1_AIN6   0x00000000

◆ GPIO_PCTL_PD1_I2C3SDA

#define GPIO_PCTL_PD1_I2C3SDA   0x00000030

◆ GPIO_PCTL_PD1_M

#define GPIO_PCTL_PD1_M   0x000000F0

◆ GPIO_PCTL_PD1_M0PWM7

#define GPIO_PCTL_PD1_M0PWM7   0x00000040

◆ GPIO_PCTL_PD1_M1PWM1

#define GPIO_PCTL_PD1_M1PWM1   0x00000050

◆ GPIO_PCTL_PD1_SSI1FSS

#define GPIO_PCTL_PD1_SSI1FSS   0x00000020

◆ GPIO_PCTL_PD1_SSI3FSS

#define GPIO_PCTL_PD1_SSI3FSS   0x00000010

◆ GPIO_PCTL_PD1_WT2CCP1

#define GPIO_PCTL_PD1_WT2CCP1   0x00000070

◆ GPIO_PCTL_PD2_AIN5

#define GPIO_PCTL_PD2_AIN5   0x00000000

◆ GPIO_PCTL_PD2_M

#define GPIO_PCTL_PD2_M   0x00000F00

◆ GPIO_PCTL_PD2_M0FAULT0

#define GPIO_PCTL_PD2_M0FAULT0   0x00000400

◆ GPIO_PCTL_PD2_SSI1RX

#define GPIO_PCTL_PD2_SSI1RX   0x00000200

◆ GPIO_PCTL_PD2_SSI3RX

#define GPIO_PCTL_PD2_SSI3RX   0x00000100

◆ GPIO_PCTL_PD2_USB0EPEN

#define GPIO_PCTL_PD2_USB0EPEN   0x00000800

◆ GPIO_PCTL_PD2_WT3CCP0

#define GPIO_PCTL_PD2_WT3CCP0   0x00000700

◆ GPIO_PCTL_PD3_AIN4

#define GPIO_PCTL_PD3_AIN4   0x00000000

◆ GPIO_PCTL_PD3_IDX0

#define GPIO_PCTL_PD3_IDX0   0x00006000

◆ GPIO_PCTL_PD3_M

#define GPIO_PCTL_PD3_M   0x0000F000

◆ GPIO_PCTL_PD3_SSI1TX

#define GPIO_PCTL_PD3_SSI1TX   0x00002000

◆ GPIO_PCTL_PD3_SSI3TX

#define GPIO_PCTL_PD3_SSI3TX   0x00001000

◆ GPIO_PCTL_PD3_USB0PFLT

#define GPIO_PCTL_PD3_USB0PFLT   0x00008000

◆ GPIO_PCTL_PD3_WT3CCP1

#define GPIO_PCTL_PD3_WT3CCP1   0x00007000

◆ GPIO_PCTL_PD4_M

#define GPIO_PCTL_PD4_M   0x000F0000

◆ GPIO_PCTL_PD4_U6RX

#define GPIO_PCTL_PD4_U6RX   0x00010000

◆ GPIO_PCTL_PD4_USB0DM

#define GPIO_PCTL_PD4_USB0DM   0x00000000

◆ GPIO_PCTL_PD4_WT4CCP0

#define GPIO_PCTL_PD4_WT4CCP0   0x00070000

◆ GPIO_PCTL_PD5_M

#define GPIO_PCTL_PD5_M   0x00F00000

◆ GPIO_PCTL_PD5_U6TX

#define GPIO_PCTL_PD5_U6TX   0x00100000

◆ GPIO_PCTL_PD5_USB0DP

#define GPIO_PCTL_PD5_USB0DP   0x00000000

◆ GPIO_PCTL_PD5_WT4CCP1

#define GPIO_PCTL_PD5_WT4CCP1   0x00700000

◆ GPIO_PCTL_PD6_M

#define GPIO_PCTL_PD6_M   0x0F000000

◆ GPIO_PCTL_PD6_M0FAULT0

#define GPIO_PCTL_PD6_M0FAULT0   0x04000000

◆ GPIO_PCTL_PD6_PHA0

#define GPIO_PCTL_PD6_PHA0   0x06000000

◆ GPIO_PCTL_PD6_U2RX

#define GPIO_PCTL_PD6_U2RX   0x01000000

◆ GPIO_PCTL_PD6_WT5CCP0

#define GPIO_PCTL_PD6_WT5CCP0   0x07000000

◆ GPIO_PCTL_PD7_M

#define GPIO_PCTL_PD7_M   0xF0000000

◆ GPIO_PCTL_PD7_NMI

#define GPIO_PCTL_PD7_NMI   0x80000000

◆ GPIO_PCTL_PD7_PHB0

#define GPIO_PCTL_PD7_PHB0   0x60000000

◆ GPIO_PCTL_PD7_U2TX

#define GPIO_PCTL_PD7_U2TX   0x10000000

◆ GPIO_PCTL_PD7_WT5CCP1

#define GPIO_PCTL_PD7_WT5CCP1   0x70000000

◆ GPIO_PCTL_PE0_AIN3

#define GPIO_PCTL_PE0_AIN3   0x00000000

◆ GPIO_PCTL_PE0_M

#define GPIO_PCTL_PE0_M   0x0000000F

◆ GPIO_PCTL_PE0_U7RX

#define GPIO_PCTL_PE0_U7RX   0x00000001

◆ GPIO_PCTL_PE1_AIN2

#define GPIO_PCTL_PE1_AIN2   0x00000000

◆ GPIO_PCTL_PE1_M

#define GPIO_PCTL_PE1_M   0x000000F0

◆ GPIO_PCTL_PE1_U7TX

#define GPIO_PCTL_PE1_U7TX   0x00000010

◆ GPIO_PCTL_PE2_AIN1

#define GPIO_PCTL_PE2_AIN1   0x00000000

◆ GPIO_PCTL_PE2_M

#define GPIO_PCTL_PE2_M   0x00000F00

◆ GPIO_PCTL_PE3_AIN0

#define GPIO_PCTL_PE3_AIN0   0x00000000

◆ GPIO_PCTL_PE3_M

#define GPIO_PCTL_PE3_M   0x0000F000

◆ GPIO_PCTL_PE4_AIN9

#define GPIO_PCTL_PE4_AIN9   0x00000000

◆ GPIO_PCTL_PE4_CAN0RX

#define GPIO_PCTL_PE4_CAN0RX   0x00080000

◆ GPIO_PCTL_PE4_I2C2SCL

#define GPIO_PCTL_PE4_I2C2SCL   0x00030000

◆ GPIO_PCTL_PE4_M

#define GPIO_PCTL_PE4_M   0x000F0000

◆ GPIO_PCTL_PE4_M0PWM4

#define GPIO_PCTL_PE4_M0PWM4   0x00040000

◆ GPIO_PCTL_PE4_M1PWM2

#define GPIO_PCTL_PE4_M1PWM2   0x00050000

◆ GPIO_PCTL_PE4_U5RX

#define GPIO_PCTL_PE4_U5RX   0x00010000

◆ GPIO_PCTL_PE5_AIN8

#define GPIO_PCTL_PE5_AIN8   0x00000000

◆ GPIO_PCTL_PE5_CAN0TX

#define GPIO_PCTL_PE5_CAN0TX   0x00800000

◆ GPIO_PCTL_PE5_I2C2SDA

#define GPIO_PCTL_PE5_I2C2SDA   0x00300000

◆ GPIO_PCTL_PE5_M

#define GPIO_PCTL_PE5_M   0x00F00000

◆ GPIO_PCTL_PE5_M0PWM5

#define GPIO_PCTL_PE5_M0PWM5   0x00400000

◆ GPIO_PCTL_PE5_M1PWM3

#define GPIO_PCTL_PE5_M1PWM3   0x00500000

◆ GPIO_PCTL_PE5_U5TX

#define GPIO_PCTL_PE5_U5TX   0x00100000

◆ GPIO_PCTL_PF0_C0O

#define GPIO_PCTL_PF0_C0O   0x00000009

◆ GPIO_PCTL_PF0_CAN0RX

#define GPIO_PCTL_PF0_CAN0RX   0x00000003

◆ GPIO_PCTL_PF0_M

#define GPIO_PCTL_PF0_M   0x0000000F

◆ GPIO_PCTL_PF0_M1PWM4

#define GPIO_PCTL_PF0_M1PWM4   0x00000005

◆ GPIO_PCTL_PF0_NMI

#define GPIO_PCTL_PF0_NMI   0x00000008

◆ GPIO_PCTL_PF0_PHA0

#define GPIO_PCTL_PF0_PHA0   0x00000006

◆ GPIO_PCTL_PF0_SSI1RX

#define GPIO_PCTL_PF0_SSI1RX   0x00000002

◆ GPIO_PCTL_PF0_T0CCP0

#define GPIO_PCTL_PF0_T0CCP0   0x00000007

◆ GPIO_PCTL_PF0_U1RTS

#define GPIO_PCTL_PF0_U1RTS   0x00000001

◆ GPIO_PCTL_PF1_C1O

#define GPIO_PCTL_PF1_C1O   0x00000090

◆ GPIO_PCTL_PF1_M

#define GPIO_PCTL_PF1_M   0x000000F0

◆ GPIO_PCTL_PF1_M1PWM5

#define GPIO_PCTL_PF1_M1PWM5   0x00000050

◆ GPIO_PCTL_PF1_PHB0

#define GPIO_PCTL_PF1_PHB0   0x00000060

◆ GPIO_PCTL_PF1_SSI1TX

#define GPIO_PCTL_PF1_SSI1TX   0x00000020

◆ GPIO_PCTL_PF1_T0CCP1

#define GPIO_PCTL_PF1_T0CCP1   0x00000070

◆ GPIO_PCTL_PF1_TRD1

#define GPIO_PCTL_PF1_TRD1   0x000000E0

◆ GPIO_PCTL_PF1_U1CTS

#define GPIO_PCTL_PF1_U1CTS   0x00000010

◆ GPIO_PCTL_PF2_M

#define GPIO_PCTL_PF2_M   0x00000F00

◆ GPIO_PCTL_PF2_M0FAULT0

#define GPIO_PCTL_PF2_M0FAULT0   0x00000400

◆ GPIO_PCTL_PF2_M1PWM6

#define GPIO_PCTL_PF2_M1PWM6   0x00000500

◆ GPIO_PCTL_PF2_SSI1CLK

#define GPIO_PCTL_PF2_SSI1CLK   0x00000200

◆ GPIO_PCTL_PF2_T1CCP0

#define GPIO_PCTL_PF2_T1CCP0   0x00000700

◆ GPIO_PCTL_PF2_TRD0

#define GPIO_PCTL_PF2_TRD0   0x00000E00

◆ GPIO_PCTL_PF3_CAN0TX

#define GPIO_PCTL_PF3_CAN0TX   0x00003000

◆ GPIO_PCTL_PF3_M

#define GPIO_PCTL_PF3_M   0x0000F000

◆ GPIO_PCTL_PF3_M1PWM7

#define GPIO_PCTL_PF3_M1PWM7   0x00005000

◆ GPIO_PCTL_PF3_SSI1FSS

#define GPIO_PCTL_PF3_SSI1FSS   0x00002000

◆ GPIO_PCTL_PF3_T1CCP1

#define GPIO_PCTL_PF3_T1CCP1   0x00007000

◆ GPIO_PCTL_PF3_TRCLK

#define GPIO_PCTL_PF3_TRCLK   0x0000E000

◆ GPIO_PCTL_PF4_IDX0

#define GPIO_PCTL_PF4_IDX0   0x00060000

◆ GPIO_PCTL_PF4_M

#define GPIO_PCTL_PF4_M   0x000F0000

◆ GPIO_PCTL_PF4_M1FAULT0

#define GPIO_PCTL_PF4_M1FAULT0   0x00050000

◆ GPIO_PCTL_PF4_T2CCP0

#define GPIO_PCTL_PF4_T2CCP0   0x00070000

◆ GPIO_PCTL_PF4_USB0EPEN

#define GPIO_PCTL_PF4_USB0EPEN   0x00080000

◆ GPIO_PORTA_ADCCTL_R

#define GPIO_PORTA_ADCCTL_R   (*((volatile u32 *)0x40004530))

◆ GPIO_PORTA_AFSEL_R

#define GPIO_PORTA_AFSEL_R   (*((volatile u32 *)0x40004420))

◆ GPIO_PORTA_AHB_ADCCTL_R

#define GPIO_PORTA_AHB_ADCCTL_R   (*((volatile u32 *)0x40058530))

◆ GPIO_PORTA_AHB_AFSEL_R

#define GPIO_PORTA_AHB_AFSEL_R   (*((volatile u32 *)0x40058420))

◆ GPIO_PORTA_AHB_AMSEL_R

#define GPIO_PORTA_AHB_AMSEL_R   (*((volatile u32 *)0x40058528))

◆ GPIO_PORTA_AHB_CR_R

#define GPIO_PORTA_AHB_CR_R   (*((volatile u32 *)0x40058524))

◆ GPIO_PORTA_AHB_DATA_BITS_R

#define GPIO_PORTA_AHB_DATA_BITS_R    ((volatile u32 *)0x40058000)

◆ GPIO_PORTA_AHB_DATA_R

#define GPIO_PORTA_AHB_DATA_R   (*((volatile u32 *)0x400583FC))

◆ GPIO_PORTA_AHB_DEN_R

#define GPIO_PORTA_AHB_DEN_R   (*((volatile u32 *)0x4005851C))

◆ GPIO_PORTA_AHB_DIR_R

#define GPIO_PORTA_AHB_DIR_R   (*((volatile u32 *)0x40058400))

◆ GPIO_PORTA_AHB_DMACTL_R

#define GPIO_PORTA_AHB_DMACTL_R   (*((volatile u32 *)0x40058534))

◆ GPIO_PORTA_AHB_DR2R_R

#define GPIO_PORTA_AHB_DR2R_R   (*((volatile u32 *)0x40058500))

◆ GPIO_PORTA_AHB_DR4R_R

#define GPIO_PORTA_AHB_DR4R_R   (*((volatile u32 *)0x40058504))

◆ GPIO_PORTA_AHB_DR8R_R

#define GPIO_PORTA_AHB_DR8R_R   (*((volatile u32 *)0x40058508))

◆ GPIO_PORTA_AHB_IBE_R

#define GPIO_PORTA_AHB_IBE_R   (*((volatile u32 *)0x40058408))

◆ GPIO_PORTA_AHB_ICR_R

#define GPIO_PORTA_AHB_ICR_R   (*((volatile u32 *)0x4005841C))

◆ GPIO_PORTA_AHB_IEV_R

#define GPIO_PORTA_AHB_IEV_R   (*((volatile u32 *)0x4005840C))

◆ GPIO_PORTA_AHB_IM_R

#define GPIO_PORTA_AHB_IM_R   (*((volatile u32 *)0x40058410))

◆ GPIO_PORTA_AHB_IS_R

#define GPIO_PORTA_AHB_IS_R   (*((volatile u32 *)0x40058404))

◆ GPIO_PORTA_AHB_LOCK_R

#define GPIO_PORTA_AHB_LOCK_R   (*((volatile u32 *)0x40058520))

◆ GPIO_PORTA_AHB_MIS_R

#define GPIO_PORTA_AHB_MIS_R   (*((volatile u32 *)0x40058418))

◆ GPIO_PORTA_AHB_ODR_R

#define GPIO_PORTA_AHB_ODR_R   (*((volatile u32 *)0x4005850C))

◆ GPIO_PORTA_AHB_PCTL_R

#define GPIO_PORTA_AHB_PCTL_R   (*((volatile u32 *)0x4005852C))

◆ GPIO_PORTA_AHB_PDR_R

#define GPIO_PORTA_AHB_PDR_R   (*((volatile u32 *)0x40058514))

◆ GPIO_PORTA_AHB_PUR_R

#define GPIO_PORTA_AHB_PUR_R   (*((volatile u32 *)0x40058510))

◆ GPIO_PORTA_AHB_RIS_R

#define GPIO_PORTA_AHB_RIS_R   (*((volatile u32 *)0x40058414))

◆ GPIO_PORTA_AHB_SLR_R

#define GPIO_PORTA_AHB_SLR_R   (*((volatile u32 *)0x40058518))

◆ GPIO_PORTA_AMSEL_R

#define GPIO_PORTA_AMSEL_R   (*((volatile u32 *)0x40004528))

◆ GPIO_PORTA_CR_R

#define GPIO_PORTA_CR_R   (*((volatile u32 *)0x40004524))

◆ GPIO_PORTA_DATA_BITS_R

#define GPIO_PORTA_DATA_BITS_R   ((volatile u32 *)0x40004000)

◆ GPIO_PORTA_DATA_R

#define GPIO_PORTA_DATA_R   (*((volatile u32 *)0x400043FC))

◆ GPIO_PORTA_DEN_R

#define GPIO_PORTA_DEN_R   (*((volatile u32 *)0x4000451C))

◆ GPIO_PORTA_DIR_R

#define GPIO_PORTA_DIR_R   (*((volatile u32 *)0x40004400))

◆ GPIO_PORTA_DMACTL_R

#define GPIO_PORTA_DMACTL_R   (*((volatile u32 *)0x40004534))

◆ GPIO_PORTA_DR2R_R

#define GPIO_PORTA_DR2R_R   (*((volatile u32 *)0x40004500))

◆ GPIO_PORTA_DR4R_R

#define GPIO_PORTA_DR4R_R   (*((volatile u32 *)0x40004504))

◆ GPIO_PORTA_DR8R_R

#define GPIO_PORTA_DR8R_R   (*((volatile u32 *)0x40004508))

◆ GPIO_PORTA_IBE_R

#define GPIO_PORTA_IBE_R   (*((volatile u32 *)0x40004408))

◆ GPIO_PORTA_ICR_R

#define GPIO_PORTA_ICR_R   (*((volatile u32 *)0x4000441C))

◆ GPIO_PORTA_IEV_R

#define GPIO_PORTA_IEV_R   (*((volatile u32 *)0x4000440C))

◆ GPIO_PORTA_IM_R

#define GPIO_PORTA_IM_R   (*((volatile u32 *)0x40004410))

◆ GPIO_PORTA_IS_R

#define GPIO_PORTA_IS_R   (*((volatile u32 *)0x40004404))

◆ GPIO_PORTA_LOCK_R

#define GPIO_PORTA_LOCK_R   (*((volatile u32 *)0x40004520))

◆ GPIO_PORTA_MIS_R

#define GPIO_PORTA_MIS_R   (*((volatile u32 *)0x40004418))

◆ GPIO_PORTA_ODR_R

#define GPIO_PORTA_ODR_R   (*((volatile u32 *)0x4000450C))

◆ GPIO_PORTA_PCTL_R

#define GPIO_PORTA_PCTL_R   (*((volatile u32 *)0x4000452C))

◆ GPIO_PORTA_PDR_R

#define GPIO_PORTA_PDR_R   (*((volatile u32 *)0x40004514))

◆ GPIO_PORTA_PUR_R

#define GPIO_PORTA_PUR_R   (*((volatile u32 *)0x40004510))

◆ GPIO_PORTA_RIS_R

#define GPIO_PORTA_RIS_R   (*((volatile u32 *)0x40004414))

◆ GPIO_PORTA_SLR_R

#define GPIO_PORTA_SLR_R   (*((volatile u32 *)0x40004518))

◆ GPIO_PORTB_ADCCTL_R

#define GPIO_PORTB_ADCCTL_R   (*((volatile u32 *)0x40005530))

◆ GPIO_PORTB_AFSEL_R

#define GPIO_PORTB_AFSEL_R   (*((volatile u32 *)0x40005420))

◆ GPIO_PORTB_AHB_ADCCTL_R

#define GPIO_PORTB_AHB_ADCCTL_R   (*((volatile u32 *)0x40059530))

◆ GPIO_PORTB_AHB_AFSEL_R

#define GPIO_PORTB_AHB_AFSEL_R   (*((volatile u32 *)0x40059420))

◆ GPIO_PORTB_AHB_AMSEL_R

#define GPIO_PORTB_AHB_AMSEL_R   (*((volatile u32 *)0x40059528))

◆ GPIO_PORTB_AHB_CR_R

#define GPIO_PORTB_AHB_CR_R   (*((volatile u32 *)0x40059524))

◆ GPIO_PORTB_AHB_DATA_BITS_R

#define GPIO_PORTB_AHB_DATA_BITS_R    ((volatile u32 *)0x40059000)

◆ GPIO_PORTB_AHB_DATA_R

#define GPIO_PORTB_AHB_DATA_R   (*((volatile u32 *)0x400593FC))

◆ GPIO_PORTB_AHB_DEN_R

#define GPIO_PORTB_AHB_DEN_R   (*((volatile u32 *)0x4005951C))

◆ GPIO_PORTB_AHB_DIR_R

#define GPIO_PORTB_AHB_DIR_R   (*((volatile u32 *)0x40059400))

◆ GPIO_PORTB_AHB_DMACTL_R

#define GPIO_PORTB_AHB_DMACTL_R   (*((volatile u32 *)0x40059534))

◆ GPIO_PORTB_AHB_DR2R_R

#define GPIO_PORTB_AHB_DR2R_R   (*((volatile u32 *)0x40059500))

◆ GPIO_PORTB_AHB_DR4R_R

#define GPIO_PORTB_AHB_DR4R_R   (*((volatile u32 *)0x40059504))

◆ GPIO_PORTB_AHB_DR8R_R

#define GPIO_PORTB_AHB_DR8R_R   (*((volatile u32 *)0x40059508))

◆ GPIO_PORTB_AHB_IBE_R

#define GPIO_PORTB_AHB_IBE_R   (*((volatile u32 *)0x40059408))

◆ GPIO_PORTB_AHB_ICR_R

#define GPIO_PORTB_AHB_ICR_R   (*((volatile u32 *)0x4005941C))

◆ GPIO_PORTB_AHB_IEV_R

#define GPIO_PORTB_AHB_IEV_R   (*((volatile u32 *)0x4005940C))

◆ GPIO_PORTB_AHB_IM_R

#define GPIO_PORTB_AHB_IM_R   (*((volatile u32 *)0x40059410))

◆ GPIO_PORTB_AHB_IS_R

#define GPIO_PORTB_AHB_IS_R   (*((volatile u32 *)0x40059404))

◆ GPIO_PORTB_AHB_LOCK_R

#define GPIO_PORTB_AHB_LOCK_R   (*((volatile u32 *)0x40059520))

◆ GPIO_PORTB_AHB_MIS_R

#define GPIO_PORTB_AHB_MIS_R   (*((volatile u32 *)0x40059418))

◆ GPIO_PORTB_AHB_ODR_R

#define GPIO_PORTB_AHB_ODR_R   (*((volatile u32 *)0x4005950C))

◆ GPIO_PORTB_AHB_PCTL_R

#define GPIO_PORTB_AHB_PCTL_R   (*((volatile u32 *)0x4005952C))

◆ GPIO_PORTB_AHB_PDR_R

#define GPIO_PORTB_AHB_PDR_R   (*((volatile u32 *)0x40059514))

◆ GPIO_PORTB_AHB_PUR_R

#define GPIO_PORTB_AHB_PUR_R   (*((volatile u32 *)0x40059510))

◆ GPIO_PORTB_AHB_RIS_R

#define GPIO_PORTB_AHB_RIS_R   (*((volatile u32 *)0x40059414))

◆ GPIO_PORTB_AHB_SLR_R

#define GPIO_PORTB_AHB_SLR_R   (*((volatile u32 *)0x40059518))

◆ GPIO_PORTB_AMSEL_R

#define GPIO_PORTB_AMSEL_R   (*((volatile u32 *)0x40005528))

◆ GPIO_PORTB_CR_R

#define GPIO_PORTB_CR_R   (*((volatile u32 *)0x40005524))

◆ GPIO_PORTB_DATA_BITS_R

#define GPIO_PORTB_DATA_BITS_R   ((volatile u32 *)0x40005000)

◆ GPIO_PORTB_DATA_R

#define GPIO_PORTB_DATA_R   (*((volatile u32 *)0x400053FC))

◆ GPIO_PORTB_DEN_R

#define GPIO_PORTB_DEN_R   (*((volatile u32 *)0x4000551C))

◆ GPIO_PORTB_DIR_R

#define GPIO_PORTB_DIR_R   (*((volatile u32 *)0x40005400))

◆ GPIO_PORTB_DMACTL_R

#define GPIO_PORTB_DMACTL_R   (*((volatile u32 *)0x40005534))

◆ GPIO_PORTB_DR2R_R

#define GPIO_PORTB_DR2R_R   (*((volatile u32 *)0x40005500))

◆ GPIO_PORTB_DR4R_R

#define GPIO_PORTB_DR4R_R   (*((volatile u32 *)0x40005504))

◆ GPIO_PORTB_DR8R_R

#define GPIO_PORTB_DR8R_R   (*((volatile u32 *)0x40005508))

◆ GPIO_PORTB_IBE_R

#define GPIO_PORTB_IBE_R   (*((volatile u32 *)0x40005408))

◆ GPIO_PORTB_ICR_R

#define GPIO_PORTB_ICR_R   (*((volatile u32 *)0x4000541C))

◆ GPIO_PORTB_IEV_R

#define GPIO_PORTB_IEV_R   (*((volatile u32 *)0x4000540C))

◆ GPIO_PORTB_IM_R

#define GPIO_PORTB_IM_R   (*((volatile u32 *)0x40005410))

◆ GPIO_PORTB_IS_R

#define GPIO_PORTB_IS_R   (*((volatile u32 *)0x40005404))

◆ GPIO_PORTB_LOCK_R

#define GPIO_PORTB_LOCK_R   (*((volatile u32 *)0x40005520))

◆ GPIO_PORTB_MIS_R

#define GPIO_PORTB_MIS_R   (*((volatile u32 *)0x40005418))

◆ GPIO_PORTB_ODR_R

#define GPIO_PORTB_ODR_R   (*((volatile u32 *)0x4000550C))

◆ GPIO_PORTB_PCTL_R

#define GPIO_PORTB_PCTL_R   (*((volatile u32 *)0x4000552C))

◆ GPIO_PORTB_PDR_R

#define GPIO_PORTB_PDR_R   (*((volatile u32 *)0x40005514))

◆ GPIO_PORTB_PUR_R

#define GPIO_PORTB_PUR_R   (*((volatile u32 *)0x40005510))

◆ GPIO_PORTB_RIS_R

#define GPIO_PORTB_RIS_R   (*((volatile u32 *)0x40005414))

◆ GPIO_PORTB_SLR_R

#define GPIO_PORTB_SLR_R   (*((volatile u32 *)0x40005518))

◆ GPIO_PORTC_ADCCTL_R

#define GPIO_PORTC_ADCCTL_R   (*((volatile u32 *)0x40006530))

◆ GPIO_PORTC_AFSEL_R

#define GPIO_PORTC_AFSEL_R   (*((volatile u32 *)0x40006420))

◆ GPIO_PORTC_AHB_ADCCTL_R

#define GPIO_PORTC_AHB_ADCCTL_R   (*((volatile u32 *)0x4005A530))

◆ GPIO_PORTC_AHB_AFSEL_R

#define GPIO_PORTC_AHB_AFSEL_R   (*((volatile u32 *)0x4005A420))

◆ GPIO_PORTC_AHB_AMSEL_R

#define GPIO_PORTC_AHB_AMSEL_R   (*((volatile u32 *)0x4005A528))

◆ GPIO_PORTC_AHB_CR_R

#define GPIO_PORTC_AHB_CR_R   (*((volatile u32 *)0x4005A524))

◆ GPIO_PORTC_AHB_DATA_BITS_R

#define GPIO_PORTC_AHB_DATA_BITS_R    ((volatile u32 *)0x4005A000)

◆ GPIO_PORTC_AHB_DATA_R

#define GPIO_PORTC_AHB_DATA_R   (*((volatile u32 *)0x4005A3FC))

◆ GPIO_PORTC_AHB_DEN_R

#define GPIO_PORTC_AHB_DEN_R   (*((volatile u32 *)0x4005A51C))

◆ GPIO_PORTC_AHB_DIR_R

#define GPIO_PORTC_AHB_DIR_R   (*((volatile u32 *)0x4005A400))

◆ GPIO_PORTC_AHB_DMACTL_R

#define GPIO_PORTC_AHB_DMACTL_R   (*((volatile u32 *)0x4005A534))

◆ GPIO_PORTC_AHB_DR2R_R

#define GPIO_PORTC_AHB_DR2R_R   (*((volatile u32 *)0x4005A500))

◆ GPIO_PORTC_AHB_DR4R_R

#define GPIO_PORTC_AHB_DR4R_R   (*((volatile u32 *)0x4005A504))

◆ GPIO_PORTC_AHB_DR8R_R

#define GPIO_PORTC_AHB_DR8R_R   (*((volatile u32 *)0x4005A508))

◆ GPIO_PORTC_AHB_IBE_R

#define GPIO_PORTC_AHB_IBE_R   (*((volatile u32 *)0x4005A408))

◆ GPIO_PORTC_AHB_ICR_R

#define GPIO_PORTC_AHB_ICR_R   (*((volatile u32 *)0x4005A41C))

◆ GPIO_PORTC_AHB_IEV_R

#define GPIO_PORTC_AHB_IEV_R   (*((volatile u32 *)0x4005A40C))

◆ GPIO_PORTC_AHB_IM_R

#define GPIO_PORTC_AHB_IM_R   (*((volatile u32 *)0x4005A410))

◆ GPIO_PORTC_AHB_IS_R

#define GPIO_PORTC_AHB_IS_R   (*((volatile u32 *)0x4005A404))

◆ GPIO_PORTC_AHB_LOCK_R

#define GPIO_PORTC_AHB_LOCK_R   (*((volatile u32 *)0x4005A520))

◆ GPIO_PORTC_AHB_MIS_R

#define GPIO_PORTC_AHB_MIS_R   (*((volatile u32 *)0x4005A418))

◆ GPIO_PORTC_AHB_ODR_R

#define GPIO_PORTC_AHB_ODR_R   (*((volatile u32 *)0x4005A50C))

◆ GPIO_PORTC_AHB_PCTL_R

#define GPIO_PORTC_AHB_PCTL_R   (*((volatile u32 *)0x4005A52C))

◆ GPIO_PORTC_AHB_PDR_R

#define GPIO_PORTC_AHB_PDR_R   (*((volatile u32 *)0x4005A514))

◆ GPIO_PORTC_AHB_PUR_R

#define GPIO_PORTC_AHB_PUR_R   (*((volatile u32 *)0x4005A510))

◆ GPIO_PORTC_AHB_RIS_R

#define GPIO_PORTC_AHB_RIS_R   (*((volatile u32 *)0x4005A414))

◆ GPIO_PORTC_AHB_SLR_R

#define GPIO_PORTC_AHB_SLR_R   (*((volatile u32 *)0x4005A518))

◆ GPIO_PORTC_AMSEL_R

#define GPIO_PORTC_AMSEL_R   (*((volatile u32 *)0x40006528))

◆ GPIO_PORTC_CR_R

#define GPIO_PORTC_CR_R   (*((volatile u32 *)0x40006524))

◆ GPIO_PORTC_DATA_BITS_R

#define GPIO_PORTC_DATA_BITS_R   ((volatile u32 *)0x40006000)

◆ GPIO_PORTC_DATA_R

#define GPIO_PORTC_DATA_R   (*((volatile u32 *)0x400063FC))

◆ GPIO_PORTC_DEN_R

#define GPIO_PORTC_DEN_R   (*((volatile u32 *)0x4000651C))

◆ GPIO_PORTC_DIR_R

#define GPIO_PORTC_DIR_R   (*((volatile u32 *)0x40006400))

◆ GPIO_PORTC_DMACTL_R

#define GPIO_PORTC_DMACTL_R   (*((volatile u32 *)0x40006534))

◆ GPIO_PORTC_DR2R_R

#define GPIO_PORTC_DR2R_R   (*((volatile u32 *)0x40006500))

◆ GPIO_PORTC_DR4R_R

#define GPIO_PORTC_DR4R_R   (*((volatile u32 *)0x40006504))

◆ GPIO_PORTC_DR8R_R

#define GPIO_PORTC_DR8R_R   (*((volatile u32 *)0x40006508))

◆ GPIO_PORTC_IBE_R

#define GPIO_PORTC_IBE_R   (*((volatile u32 *)0x40006408))

◆ GPIO_PORTC_ICR_R

#define GPIO_PORTC_ICR_R   (*((volatile u32 *)0x4000641C))

◆ GPIO_PORTC_IEV_R

#define GPIO_PORTC_IEV_R   (*((volatile u32 *)0x4000640C))

◆ GPIO_PORTC_IM_R

#define GPIO_PORTC_IM_R   (*((volatile u32 *)0x40006410))

◆ GPIO_PORTC_IS_R

#define GPIO_PORTC_IS_R   (*((volatile u32 *)0x40006404))

◆ GPIO_PORTC_LOCK_R

#define GPIO_PORTC_LOCK_R   (*((volatile u32 *)0x40006520))

◆ GPIO_PORTC_MIS_R

#define GPIO_PORTC_MIS_R   (*((volatile u32 *)0x40006418))

◆ GPIO_PORTC_ODR_R

#define GPIO_PORTC_ODR_R   (*((volatile u32 *)0x4000650C))

◆ GPIO_PORTC_PCTL_R

#define GPIO_PORTC_PCTL_R   (*((volatile u32 *)0x4000652C))

◆ GPIO_PORTC_PDR_R

#define GPIO_PORTC_PDR_R   (*((volatile u32 *)0x40006514))

◆ GPIO_PORTC_PUR_R

#define GPIO_PORTC_PUR_R   (*((volatile u32 *)0x40006510))

◆ GPIO_PORTC_RIS_R

#define GPIO_PORTC_RIS_R   (*((volatile u32 *)0x40006414))

◆ GPIO_PORTC_SLR_R

#define GPIO_PORTC_SLR_R   (*((volatile u32 *)0x40006518))

◆ GPIO_PORTD_ADCCTL_R

#define GPIO_PORTD_ADCCTL_R   (*((volatile u32 *)0x40007530))

◆ GPIO_PORTD_AFSEL_R

#define GPIO_PORTD_AFSEL_R   (*((volatile u32 *)0x40007420))

◆ GPIO_PORTD_AHB_ADCCTL_R

#define GPIO_PORTD_AHB_ADCCTL_R   (*((volatile u32 *)0x4005B530))

◆ GPIO_PORTD_AHB_AFSEL_R

#define GPIO_PORTD_AHB_AFSEL_R   (*((volatile u32 *)0x4005B420))

◆ GPIO_PORTD_AHB_AMSEL_R

#define GPIO_PORTD_AHB_AMSEL_R   (*((volatile u32 *)0x4005B528))

◆ GPIO_PORTD_AHB_CR_R

#define GPIO_PORTD_AHB_CR_R   (*((volatile u32 *)0x4005B524))

◆ GPIO_PORTD_AHB_DATA_BITS_R

#define GPIO_PORTD_AHB_DATA_BITS_R    ((volatile u32 *)0x4005B000)

◆ GPIO_PORTD_AHB_DATA_R

#define GPIO_PORTD_AHB_DATA_R   (*((volatile u32 *)0x4005B3FC))

◆ GPIO_PORTD_AHB_DEN_R

#define GPIO_PORTD_AHB_DEN_R   (*((volatile u32 *)0x4005B51C))

◆ GPIO_PORTD_AHB_DIR_R

#define GPIO_PORTD_AHB_DIR_R   (*((volatile u32 *)0x4005B400))

◆ GPIO_PORTD_AHB_DMACTL_R

#define GPIO_PORTD_AHB_DMACTL_R   (*((volatile u32 *)0x4005B534))

◆ GPIO_PORTD_AHB_DR2R_R

#define GPIO_PORTD_AHB_DR2R_R   (*((volatile u32 *)0x4005B500))

◆ GPIO_PORTD_AHB_DR4R_R

#define GPIO_PORTD_AHB_DR4R_R   (*((volatile u32 *)0x4005B504))

◆ GPIO_PORTD_AHB_DR8R_R

#define GPIO_PORTD_AHB_DR8R_R   (*((volatile u32 *)0x4005B508))

◆ GPIO_PORTD_AHB_IBE_R

#define GPIO_PORTD_AHB_IBE_R   (*((volatile u32 *)0x4005B408))

◆ GPIO_PORTD_AHB_ICR_R

#define GPIO_PORTD_AHB_ICR_R   (*((volatile u32 *)0x4005B41C))

◆ GPIO_PORTD_AHB_IEV_R

#define GPIO_PORTD_AHB_IEV_R   (*((volatile u32 *)0x4005B40C))

◆ GPIO_PORTD_AHB_IM_R

#define GPIO_PORTD_AHB_IM_R   (*((volatile u32 *)0x4005B410))

◆ GPIO_PORTD_AHB_IS_R

#define GPIO_PORTD_AHB_IS_R   (*((volatile u32 *)0x4005B404))

◆ GPIO_PORTD_AHB_LOCK_R

#define GPIO_PORTD_AHB_LOCK_R   (*((volatile u32 *)0x4005B520))

◆ GPIO_PORTD_AHB_MIS_R

#define GPIO_PORTD_AHB_MIS_R   (*((volatile u32 *)0x4005B418))

◆ GPIO_PORTD_AHB_ODR_R

#define GPIO_PORTD_AHB_ODR_R   (*((volatile u32 *)0x4005B50C))

◆ GPIO_PORTD_AHB_PCTL_R

#define GPIO_PORTD_AHB_PCTL_R   (*((volatile u32 *)0x4005B52C))

◆ GPIO_PORTD_AHB_PDR_R

#define GPIO_PORTD_AHB_PDR_R   (*((volatile u32 *)0x4005B514))

◆ GPIO_PORTD_AHB_PUR_R

#define GPIO_PORTD_AHB_PUR_R   (*((volatile u32 *)0x4005B510))

◆ GPIO_PORTD_AHB_RIS_R

#define GPIO_PORTD_AHB_RIS_R   (*((volatile u32 *)0x4005B414))

◆ GPIO_PORTD_AHB_SLR_R

#define GPIO_PORTD_AHB_SLR_R   (*((volatile u32 *)0x4005B518))

◆ GPIO_PORTD_AMSEL_R

#define GPIO_PORTD_AMSEL_R   (*((volatile u32 *)0x40007528))

◆ GPIO_PORTD_CR_R

#define GPIO_PORTD_CR_R   (*((volatile u32 *)0x40007524))

◆ GPIO_PORTD_DATA_BITS_R

#define GPIO_PORTD_DATA_BITS_R   ((volatile u32 *)0x40007000)

◆ GPIO_PORTD_DATA_R

#define GPIO_PORTD_DATA_R   (*((volatile u32 *)0x400073FC))

◆ GPIO_PORTD_DEN_R

#define GPIO_PORTD_DEN_R   (*((volatile u32 *)0x4000751C))

◆ GPIO_PORTD_DIR_R

#define GPIO_PORTD_DIR_R   (*((volatile u32 *)0x40007400))

◆ GPIO_PORTD_DMACTL_R

#define GPIO_PORTD_DMACTL_R   (*((volatile u32 *)0x40007534))

◆ GPIO_PORTD_DR2R_R

#define GPIO_PORTD_DR2R_R   (*((volatile u32 *)0x40007500))

◆ GPIO_PORTD_DR4R_R

#define GPIO_PORTD_DR4R_R   (*((volatile u32 *)0x40007504))

◆ GPIO_PORTD_DR8R_R

#define GPIO_PORTD_DR8R_R   (*((volatile u32 *)0x40007508))

◆ GPIO_PORTD_IBE_R

#define GPIO_PORTD_IBE_R   (*((volatile u32 *)0x40007408))

◆ GPIO_PORTD_ICR_R

#define GPIO_PORTD_ICR_R   (*((volatile u32 *)0x4000741C))

◆ GPIO_PORTD_IEV_R

#define GPIO_PORTD_IEV_R   (*((volatile u32 *)0x4000740C))

◆ GPIO_PORTD_IM_R

#define GPIO_PORTD_IM_R   (*((volatile u32 *)0x40007410))

◆ GPIO_PORTD_IS_R

#define GPIO_PORTD_IS_R   (*((volatile u32 *)0x40007404))

◆ GPIO_PORTD_LOCK_R

#define GPIO_PORTD_LOCK_R   (*((volatile u32 *)0x40007520))

◆ GPIO_PORTD_MIS_R

#define GPIO_PORTD_MIS_R   (*((volatile u32 *)0x40007418))

◆ GPIO_PORTD_ODR_R

#define GPIO_PORTD_ODR_R   (*((volatile u32 *)0x4000750C))

◆ GPIO_PORTD_PCTL_R

#define GPIO_PORTD_PCTL_R   (*((volatile u32 *)0x4000752C))

◆ GPIO_PORTD_PDR_R

#define GPIO_PORTD_PDR_R   (*((volatile u32 *)0x40007514))

◆ GPIO_PORTD_PUR_R

#define GPIO_PORTD_PUR_R   (*((volatile u32 *)0x40007510))

◆ GPIO_PORTD_RIS_R

#define GPIO_PORTD_RIS_R   (*((volatile u32 *)0x40007414))

◆ GPIO_PORTD_SLR_R

#define GPIO_PORTD_SLR_R   (*((volatile u32 *)0x40007518))

◆ GPIO_PORTE_ADCCTL_R

#define GPIO_PORTE_ADCCTL_R   (*((volatile u32 *)0x40024530))

◆ GPIO_PORTE_AFSEL_R

#define GPIO_PORTE_AFSEL_R   (*((volatile u32 *)0x40024420))

◆ GPIO_PORTE_AHB_ADCCTL_R

#define GPIO_PORTE_AHB_ADCCTL_R   (*((volatile u32 *)0x4005C530))

◆ GPIO_PORTE_AHB_AFSEL_R

#define GPIO_PORTE_AHB_AFSEL_R   (*((volatile u32 *)0x4005C420))

◆ GPIO_PORTE_AHB_AMSEL_R

#define GPIO_PORTE_AHB_AMSEL_R   (*((volatile u32 *)0x4005C528))

◆ GPIO_PORTE_AHB_CR_R

#define GPIO_PORTE_AHB_CR_R   (*((volatile u32 *)0x4005C524))

◆ GPIO_PORTE_AHB_DATA_BITS_R

#define GPIO_PORTE_AHB_DATA_BITS_R    ((volatile u32 *)0x4005C000)

◆ GPIO_PORTE_AHB_DATA_R

#define GPIO_PORTE_AHB_DATA_R   (*((volatile u32 *)0x4005C3FC))

◆ GPIO_PORTE_AHB_DEN_R

#define GPIO_PORTE_AHB_DEN_R   (*((volatile u32 *)0x4005C51C))

◆ GPIO_PORTE_AHB_DIR_R

#define GPIO_PORTE_AHB_DIR_R   (*((volatile u32 *)0x4005C400))

◆ GPIO_PORTE_AHB_DMACTL_R

#define GPIO_PORTE_AHB_DMACTL_R   (*((volatile u32 *)0x4005C534))

◆ GPIO_PORTE_AHB_DR2R_R

#define GPIO_PORTE_AHB_DR2R_R   (*((volatile u32 *)0x4005C500))

◆ GPIO_PORTE_AHB_DR4R_R

#define GPIO_PORTE_AHB_DR4R_R   (*((volatile u32 *)0x4005C504))

◆ GPIO_PORTE_AHB_DR8R_R

#define GPIO_PORTE_AHB_DR8R_R   (*((volatile u32 *)0x4005C508))

◆ GPIO_PORTE_AHB_IBE_R

#define GPIO_PORTE_AHB_IBE_R   (*((volatile u32 *)0x4005C408))

◆ GPIO_PORTE_AHB_ICR_R

#define GPIO_PORTE_AHB_ICR_R   (*((volatile u32 *)0x4005C41C))

◆ GPIO_PORTE_AHB_IEV_R

#define GPIO_PORTE_AHB_IEV_R   (*((volatile u32 *)0x4005C40C))

◆ GPIO_PORTE_AHB_IM_R

#define GPIO_PORTE_AHB_IM_R   (*((volatile u32 *)0x4005C410))

◆ GPIO_PORTE_AHB_IS_R

#define GPIO_PORTE_AHB_IS_R   (*((volatile u32 *)0x4005C404))

◆ GPIO_PORTE_AHB_LOCK_R

#define GPIO_PORTE_AHB_LOCK_R   (*((volatile u32 *)0x4005C520))

◆ GPIO_PORTE_AHB_MIS_R

#define GPIO_PORTE_AHB_MIS_R   (*((volatile u32 *)0x4005C418))

◆ GPIO_PORTE_AHB_ODR_R

#define GPIO_PORTE_AHB_ODR_R   (*((volatile u32 *)0x4005C50C))

◆ GPIO_PORTE_AHB_PCTL_R

#define GPIO_PORTE_AHB_PCTL_R   (*((volatile u32 *)0x4005C52C))

◆ GPIO_PORTE_AHB_PDR_R

#define GPIO_PORTE_AHB_PDR_R   (*((volatile u32 *)0x4005C514))

◆ GPIO_PORTE_AHB_PUR_R

#define GPIO_PORTE_AHB_PUR_R   (*((volatile u32 *)0x4005C510))

◆ GPIO_PORTE_AHB_RIS_R

#define GPIO_PORTE_AHB_RIS_R   (*((volatile u32 *)0x4005C414))

◆ GPIO_PORTE_AHB_SLR_R

#define GPIO_PORTE_AHB_SLR_R   (*((volatile u32 *)0x4005C518))

◆ GPIO_PORTE_AMSEL_R

#define GPIO_PORTE_AMSEL_R   (*((volatile u32 *)0x40024528))

◆ GPIO_PORTE_CR_R

#define GPIO_PORTE_CR_R   (*((volatile u32 *)0x40024524))

◆ GPIO_PORTE_DATA_BITS_R

#define GPIO_PORTE_DATA_BITS_R   ((volatile u32 *)0x40024000)

◆ GPIO_PORTE_DATA_R

#define GPIO_PORTE_DATA_R   (*((volatile u32 *)0x400243FC))

◆ GPIO_PORTE_DEN_R

#define GPIO_PORTE_DEN_R   (*((volatile u32 *)0x4002451C))

◆ GPIO_PORTE_DIR_R

#define GPIO_PORTE_DIR_R   (*((volatile u32 *)0x40024400))

◆ GPIO_PORTE_DMACTL_R

#define GPIO_PORTE_DMACTL_R   (*((volatile u32 *)0x40024534))

◆ GPIO_PORTE_DR2R_R

#define GPIO_PORTE_DR2R_R   (*((volatile u32 *)0x40024500))

◆ GPIO_PORTE_DR4R_R

#define GPIO_PORTE_DR4R_R   (*((volatile u32 *)0x40024504))

◆ GPIO_PORTE_DR8R_R

#define GPIO_PORTE_DR8R_R   (*((volatile u32 *)0x40024508))

◆ GPIO_PORTE_IBE_R

#define GPIO_PORTE_IBE_R   (*((volatile u32 *)0x40024408))

◆ GPIO_PORTE_ICR_R

#define GPIO_PORTE_ICR_R   (*((volatile u32 *)0x4002441C))

◆ GPIO_PORTE_IEV_R

#define GPIO_PORTE_IEV_R   (*((volatile u32 *)0x4002440C))

◆ GPIO_PORTE_IM_R

#define GPIO_PORTE_IM_R   (*((volatile u32 *)0x40024410))

◆ GPIO_PORTE_IS_R

#define GPIO_PORTE_IS_R   (*((volatile u32 *)0x40024404))

◆ GPIO_PORTE_LOCK_R

#define GPIO_PORTE_LOCK_R   (*((volatile u32 *)0x40024520))

◆ GPIO_PORTE_MIS_R

#define GPIO_PORTE_MIS_R   (*((volatile u32 *)0x40024418))

◆ GPIO_PORTE_ODR_R

#define GPIO_PORTE_ODR_R   (*((volatile u32 *)0x4002450C))

◆ GPIO_PORTE_PCTL_R

#define GPIO_PORTE_PCTL_R   (*((volatile u32 *)0x4002452C))

◆ GPIO_PORTE_PDR_R

#define GPIO_PORTE_PDR_R   (*((volatile u32 *)0x40024514))

◆ GPIO_PORTE_PUR_R

#define GPIO_PORTE_PUR_R   (*((volatile u32 *)0x40024510))

◆ GPIO_PORTE_RIS_R

#define GPIO_PORTE_RIS_R   (*((volatile u32 *)0x40024414))

◆ GPIO_PORTE_SLR_R

#define GPIO_PORTE_SLR_R   (*((volatile u32 *)0x40024518))

◆ GPIO_PORTF_ADCCTL_R

#define GPIO_PORTF_ADCCTL_R   (*((volatile u32 *)0x40025530))

◆ GPIO_PORTF_AFSEL_R

#define GPIO_PORTF_AFSEL_R   (*((volatile u32 *)0x40025420))

◆ GPIO_PORTF_AHB_ADCCTL_R

#define GPIO_PORTF_AHB_ADCCTL_R   (*((volatile u32 *)0x4005D530))

◆ GPIO_PORTF_AHB_AFSEL_R

#define GPIO_PORTF_AHB_AFSEL_R   (*((volatile u32 *)0x4005D420))

◆ GPIO_PORTF_AHB_AMSEL_R

#define GPIO_PORTF_AHB_AMSEL_R   (*((volatile u32 *)0x4005D528))

◆ GPIO_PORTF_AHB_CR_R

#define GPIO_PORTF_AHB_CR_R   (*((volatile u32 *)0x4005D524))

◆ GPIO_PORTF_AHB_DATA_BITS_R

#define GPIO_PORTF_AHB_DATA_BITS_R    ((volatile u32 *)0x4005D000)

◆ GPIO_PORTF_AHB_DATA_R

#define GPIO_PORTF_AHB_DATA_R   (*((volatile u32 *)0x4005D3FC))

◆ GPIO_PORTF_AHB_DEN_R

#define GPIO_PORTF_AHB_DEN_R   (*((volatile u32 *)0x4005D51C))

◆ GPIO_PORTF_AHB_DIR_R

#define GPIO_PORTF_AHB_DIR_R   (*((volatile u32 *)0x4005D400))

◆ GPIO_PORTF_AHB_DMACTL_R

#define GPIO_PORTF_AHB_DMACTL_R   (*((volatile u32 *)0x4005D534))

◆ GPIO_PORTF_AHB_DR2R_R

#define GPIO_PORTF_AHB_DR2R_R   (*((volatile u32 *)0x4005D500))

◆ GPIO_PORTF_AHB_DR4R_R

#define GPIO_PORTF_AHB_DR4R_R   (*((volatile u32 *)0x4005D504))

◆ GPIO_PORTF_AHB_DR8R_R

#define GPIO_PORTF_AHB_DR8R_R   (*((volatile u32 *)0x4005D508))

◆ GPIO_PORTF_AHB_IBE_R

#define GPIO_PORTF_AHB_IBE_R   (*((volatile u32 *)0x4005D408))

◆ GPIO_PORTF_AHB_ICR_R

#define GPIO_PORTF_AHB_ICR_R   (*((volatile u32 *)0x4005D41C))

◆ GPIO_PORTF_AHB_IEV_R

#define GPIO_PORTF_AHB_IEV_R   (*((volatile u32 *)0x4005D40C))

◆ GPIO_PORTF_AHB_IM_R

#define GPIO_PORTF_AHB_IM_R   (*((volatile u32 *)0x4005D410))

◆ GPIO_PORTF_AHB_IS_R

#define GPIO_PORTF_AHB_IS_R   (*((volatile u32 *)0x4005D404))

◆ GPIO_PORTF_AHB_LOCK_R

#define GPIO_PORTF_AHB_LOCK_R   (*((volatile u32 *)0x4005D520))

◆ GPIO_PORTF_AHB_MIS_R

#define GPIO_PORTF_AHB_MIS_R   (*((volatile u32 *)0x4005D418))

◆ GPIO_PORTF_AHB_ODR_R

#define GPIO_PORTF_AHB_ODR_R   (*((volatile u32 *)0x4005D50C))

◆ GPIO_PORTF_AHB_PCTL_R

#define GPIO_PORTF_AHB_PCTL_R   (*((volatile u32 *)0x4005D52C))

◆ GPIO_PORTF_AHB_PDR_R

#define GPIO_PORTF_AHB_PDR_R   (*((volatile u32 *)0x4005D514))

◆ GPIO_PORTF_AHB_PUR_R

#define GPIO_PORTF_AHB_PUR_R   (*((volatile u32 *)0x4005D510))

◆ GPIO_PORTF_AHB_RIS_R

#define GPIO_PORTF_AHB_RIS_R   (*((volatile u32 *)0x4005D414))

◆ GPIO_PORTF_AHB_SLR_R

#define GPIO_PORTF_AHB_SLR_R   (*((volatile u32 *)0x4005D518))

◆ GPIO_PORTF_AMSEL_R

#define GPIO_PORTF_AMSEL_R   (*((volatile u32 *)0x40025528))

◆ GPIO_PORTF_CR_R

#define GPIO_PORTF_CR_R   (*((volatile u32 *)0x40025524))

◆ GPIO_PORTF_DATA_BITS_R

#define GPIO_PORTF_DATA_BITS_R   ((volatile u32 *)0x40025000)

◆ GPIO_PORTF_DATA_R

#define GPIO_PORTF_DATA_R   (*((volatile u32 *)0x400253FC))

◆ GPIO_PORTF_DEN_R

#define GPIO_PORTF_DEN_R   (*((volatile u32 *)0x4002551C))

◆ GPIO_PORTF_DIR_R

#define GPIO_PORTF_DIR_R   (*((volatile u32 *)0x40025400))

◆ GPIO_PORTF_DMACTL_R

#define GPIO_PORTF_DMACTL_R   (*((volatile u32 *)0x40025534))

◆ GPIO_PORTF_DR2R_R

#define GPIO_PORTF_DR2R_R   (*((volatile u32 *)0x40025500))

◆ GPIO_PORTF_DR4R_R

#define GPIO_PORTF_DR4R_R   (*((volatile u32 *)0x40025504))

◆ GPIO_PORTF_DR8R_R

#define GPIO_PORTF_DR8R_R   (*((volatile u32 *)0x40025508))

◆ GPIO_PORTF_IBE_R

#define GPIO_PORTF_IBE_R   (*((volatile u32 *)0x40025408))

◆ GPIO_PORTF_ICR_R

#define GPIO_PORTF_ICR_R   (*((volatile u32 *)0x4002541C))

◆ GPIO_PORTF_IEV_R

#define GPIO_PORTF_IEV_R   (*((volatile u32 *)0x4002540C))

◆ GPIO_PORTF_IM_R

#define GPIO_PORTF_IM_R   (*((volatile u32 *)0x40025410))

◆ GPIO_PORTF_IS_R

#define GPIO_PORTF_IS_R   (*((volatile u32 *)0x40025404))

◆ GPIO_PORTF_LOCK_R

#define GPIO_PORTF_LOCK_R   (*((volatile u32 *)0x40025520))

◆ GPIO_PORTF_MIS_R

#define GPIO_PORTF_MIS_R   (*((volatile u32 *)0x40025418))

◆ GPIO_PORTF_ODR_R

#define GPIO_PORTF_ODR_R   (*((volatile u32 *)0x4002550C))

◆ GPIO_PORTF_PCTL_R

#define GPIO_PORTF_PCTL_R   (*((volatile u32 *)0x4002552C))

◆ GPIO_PORTF_PDR_R

#define GPIO_PORTF_PDR_R   (*((volatile u32 *)0x40025514))

◆ GPIO_PORTF_PUR_R

#define GPIO_PORTF_PUR_R   (*((volatile u32 *)0x40025510))

◆ GPIO_PORTF_RIS_R

#define GPIO_PORTF_RIS_R   (*((volatile u32 *)0x40025414))

◆ GPIO_PORTF_SLR_R

#define GPIO_PORTF_SLR_R   (*((volatile u32 *)0x40025518))

◆ GPIO_RIS_GPIO_M

#define GPIO_RIS_GPIO_M   0x000000FF

◆ GPIO_RIS_GPIO_S

#define GPIO_RIS_GPIO_S   0

◆ HIB_CTL_BATCHK

#define HIB_CTL_BATCHK   0x00000400

◆ HIB_CTL_BATWKEN

#define HIB_CTL_BATWKEN   0x00000200

◆ HIB_CTL_CLK32EN

#define HIB_CTL_CLK32EN   0x00000040

◆ HIB_CTL_HIBREQ

#define HIB_CTL_HIBREQ   0x00000002

◆ HIB_CTL_OSCBYP

#define HIB_CTL_OSCBYP   0x00010000

◆ HIB_CTL_OSCDRV

#define HIB_CTL_OSCDRV   0x00020000

◆ HIB_CTL_PINWEN

#define HIB_CTL_PINWEN   0x00000010

◆ HIB_CTL_R

#define HIB_CTL_R   (*((volatile u32 *)0x400FC010))

◆ HIB_CTL_RTCEN

#define HIB_CTL_RTCEN   0x00000001

◆ HIB_CTL_RTCWEN

#define HIB_CTL_RTCWEN   0x00000008

◆ HIB_CTL_VABORT

#define HIB_CTL_VABORT   0x00000080

◆ HIB_CTL_VBATSEL_1_9V

#define HIB_CTL_VBATSEL_1_9V   0x00000000

◆ HIB_CTL_VBATSEL_2_1V

#define HIB_CTL_VBATSEL_2_1V   0x00002000

◆ HIB_CTL_VBATSEL_2_3V

#define HIB_CTL_VBATSEL_2_3V   0x00004000

◆ HIB_CTL_VBATSEL_2_5V

#define HIB_CTL_VBATSEL_2_5V   0x00006000

◆ HIB_CTL_VBATSEL_M

#define HIB_CTL_VBATSEL_M   0x00006000

◆ HIB_CTL_VDD3ON

#define HIB_CTL_VDD3ON   0x00000100

◆ HIB_CTL_WRC

#define HIB_CTL_WRC   0x80000000

◆ HIB_DATA_R

#define HIB_DATA_R   (*((volatile u32 *)0x400FC030))

◆ HIB_DATA_RTD_M

#define HIB_DATA_RTD_M   0xFFFFFFFF

◆ HIB_DATA_RTD_S

#define HIB_DATA_RTD_S   0

◆ HIB_IC_EXTW

#define HIB_IC_EXTW   0x00000008

◆ HIB_IC_LOWBAT

#define HIB_IC_LOWBAT   0x00000004

◆ HIB_IC_R

#define HIB_IC_R   (*((volatile u32 *)0x400FC020))

◆ HIB_IC_RTCALT0

#define HIB_IC_RTCALT0   0x00000001

◆ HIB_IC_WC

#define HIB_IC_WC   0x00000010

◆ HIB_IM_EXTW

#define HIB_IM_EXTW   0x00000008

◆ HIB_IM_LOWBAT

#define HIB_IM_LOWBAT   0x00000004

◆ HIB_IM_R

#define HIB_IM_R   (*((volatile u32 *)0x400FC014))

◆ HIB_IM_RTCALT0

#define HIB_IM_RTCALT0   0x00000001

◆ HIB_IM_WC

#define HIB_IM_WC   0x00000010

◆ HIB_MIS_EXTW

#define HIB_MIS_EXTW   0x00000008

◆ HIB_MIS_LOWBAT

#define HIB_MIS_LOWBAT   0x00000004

◆ HIB_MIS_R

#define HIB_MIS_R   (*((volatile u32 *)0x400FC01C))

◆ HIB_MIS_RTCALT0

#define HIB_MIS_RTCALT0   0x00000001

◆ HIB_MIS_WC

#define HIB_MIS_WC   0x00000010

◆ HIB_RIS_EXTW

#define HIB_RIS_EXTW   0x00000008

◆ HIB_RIS_LOWBAT

#define HIB_RIS_LOWBAT   0x00000004

◆ HIB_RIS_R

#define HIB_RIS_R   (*((volatile u32 *)0x400FC018))

◆ HIB_RIS_RTCALT0

#define HIB_RIS_RTCALT0   0x00000001

◆ HIB_RIS_WC

#define HIB_RIS_WC   0x00000010

◆ HIB_RTCC_M

#define HIB_RTCC_M   0xFFFFFFFF

◆ HIB_RTCC_R

#define HIB_RTCC_R   (*((volatile u32 *)0x400FC000))

◆ HIB_RTCC_S

#define HIB_RTCC_S   0

◆ HIB_RTCLD_M

#define HIB_RTCLD_M   0xFFFFFFFF

◆ HIB_RTCLD_R

#define HIB_RTCLD_R   (*((volatile u32 *)0x400FC00C))

◆ HIB_RTCLD_S

#define HIB_RTCLD_S   0

◆ HIB_RTCM0_M

#define HIB_RTCM0_M   0xFFFFFFFF

◆ HIB_RTCM0_R

#define HIB_RTCM0_R   (*((volatile u32 *)0x400FC004))

◆ HIB_RTCM0_S

#define HIB_RTCM0_S   0

◆ HIB_RTCSS_R

#define HIB_RTCSS_R   (*((volatile u32 *)0x400FC028))

◆ HIB_RTCSS_RTCSSC_M

#define HIB_RTCSS_RTCSSC_M   0x00007FFF

◆ HIB_RTCSS_RTCSSC_S

#define HIB_RTCSS_RTCSSC_S   0

◆ HIB_RTCSS_RTCSSM_M

#define HIB_RTCSS_RTCSSM_M   0x7FFF0000

◆ HIB_RTCSS_RTCSSM_S

#define HIB_RTCSS_RTCSSM_S   16

◆ HIB_RTCT_R

#define HIB_RTCT_R   (*((volatile u32 *)0x400FC024))

◆ HIB_RTCT_TRIM_M

#define HIB_RTCT_TRIM_M   0x0000FFFF

◆ HIB_RTCT_TRIM_S

#define HIB_RTCT_TRIM_S   0

◆ I2C0_MBMON_R

#define I2C0_MBMON_R   (*((volatile u32 *)0x4002002C))

◆ I2C0_MCLKOCNT_R

#define I2C0_MCLKOCNT_R   (*((volatile u32 *)0x40020024))

◆ I2C0_MCR2_R

#define I2C0_MCR2_R   (*((volatile u32 *)0x40020038))

◆ I2C0_MCR_R

#define I2C0_MCR_R   (*((volatile u32 *)0x40020020))

◆ I2C0_MCS_R

#define I2C0_MCS_R   (*((volatile u32 *)0x40020004))

◆ I2C0_MDR_R

#define I2C0_MDR_R   (*((volatile u32 *)0x40020008))

◆ I2C0_MICR_R

#define I2C0_MICR_R   (*((volatile u32 *)0x4002001C))

◆ I2C0_MIMR_R

#define I2C0_MIMR_R   (*((volatile u32 *)0x40020010))

◆ I2C0_MMIS_R

#define I2C0_MMIS_R   (*((volatile u32 *)0x40020018))

◆ I2C0_MRIS_R

#define I2C0_MRIS_R   (*((volatile u32 *)0x40020014))

◆ I2C0_MSA_R

#define I2C0_MSA_R   (*((volatile u32 *)0x40020000))

◆ I2C0_MTPR_R

#define I2C0_MTPR_R   (*((volatile u32 *)0x4002000C))

◆ I2C0_PC_R

#define I2C0_PC_R   (*((volatile u32 *)0x40020FC4))

◆ I2C0_PP_R

#define I2C0_PP_R   (*((volatile u32 *)0x40020FC0))

◆ I2C0_SACKCTL_R

#define I2C0_SACKCTL_R   (*((volatile u32 *)0x40020820))

◆ I2C0_SCSR_R

#define I2C0_SCSR_R   (*((volatile u32 *)0x40020804))

◆ I2C0_SDR_R

#define I2C0_SDR_R   (*((volatile u32 *)0x40020808))

◆ I2C0_SICR_R

#define I2C0_SICR_R   (*((volatile u32 *)0x40020818))

◆ I2C0_SIMR_R

#define I2C0_SIMR_R   (*((volatile u32 *)0x4002080C))

◆ I2C0_SMIS_R

#define I2C0_SMIS_R   (*((volatile u32 *)0x40020814))

◆ I2C0_SOAR2_R

#define I2C0_SOAR2_R   (*((volatile u32 *)0x4002081C))

◆ I2C0_SOAR_R

#define I2C0_SOAR_R   (*((volatile u32 *)0x40020800))

◆ I2C0_SRIS_R

#define I2C0_SRIS_R   (*((volatile u32 *)0x40020810))

◆ I2C1_MBMON_R

#define I2C1_MBMON_R   (*((volatile u32 *)0x4002102C))

◆ I2C1_MCLKOCNT_R

#define I2C1_MCLKOCNT_R   (*((volatile u32 *)0x40021024))

◆ I2C1_MCR2_R

#define I2C1_MCR2_R   (*((volatile u32 *)0x40021038))

◆ I2C1_MCR_R

#define I2C1_MCR_R   (*((volatile u32 *)0x40021020))

◆ I2C1_MCS_R

#define I2C1_MCS_R   (*((volatile u32 *)0x40021004))

◆ I2C1_MDR_R

#define I2C1_MDR_R   (*((volatile u32 *)0x40021008))

◆ I2C1_MICR_R

#define I2C1_MICR_R   (*((volatile u32 *)0x4002101C))

◆ I2C1_MIMR_R

#define I2C1_MIMR_R   (*((volatile u32 *)0x40021010))

◆ I2C1_MMIS_R

#define I2C1_MMIS_R   (*((volatile u32 *)0x40021018))

◆ I2C1_MRIS_R

#define I2C1_MRIS_R   (*((volatile u32 *)0x40021014))

◆ I2C1_MSA_R

#define I2C1_MSA_R   (*((volatile u32 *)0x40021000))

◆ I2C1_MTPR_R

#define I2C1_MTPR_R   (*((volatile u32 *)0x4002100C))

◆ I2C1_PC_R

#define I2C1_PC_R   (*((volatile u32 *)0x40021FC4))

◆ I2C1_PP_R

#define I2C1_PP_R   (*((volatile u32 *)0x40021FC0))

◆ I2C1_SACKCTL_R

#define I2C1_SACKCTL_R   (*((volatile u32 *)0x40021820))

◆ I2C1_SCSR_R

#define I2C1_SCSR_R   (*((volatile u32 *)0x40021804))

◆ I2C1_SDR_R

#define I2C1_SDR_R   (*((volatile u32 *)0x40021808))

◆ I2C1_SICR_R

#define I2C1_SICR_R   (*((volatile u32 *)0x40021818))

◆ I2C1_SIMR_R

#define I2C1_SIMR_R   (*((volatile u32 *)0x4002180C))

◆ I2C1_SMIS_R

#define I2C1_SMIS_R   (*((volatile u32 *)0x40021814))

◆ I2C1_SOAR2_R

#define I2C1_SOAR2_R   (*((volatile u32 *)0x4002181C))

◆ I2C1_SOAR_R

#define I2C1_SOAR_R   (*((volatile u32 *)0x40021800))

◆ I2C1_SRIS_R

#define I2C1_SRIS_R   (*((volatile u32 *)0x40021810))

◆ I2C2_MBMON_R

#define I2C2_MBMON_R   (*((volatile u32 *)0x4002202C))

◆ I2C2_MCLKOCNT_R

#define I2C2_MCLKOCNT_R   (*((volatile u32 *)0x40022024))

◆ I2C2_MCR2_R

#define I2C2_MCR2_R   (*((volatile u32 *)0x40022038))

◆ I2C2_MCR_R

#define I2C2_MCR_R   (*((volatile u32 *)0x40022020))

◆ I2C2_MCS_R

#define I2C2_MCS_R   (*((volatile u32 *)0x40022004))

◆ I2C2_MDR_R

#define I2C2_MDR_R   (*((volatile u32 *)0x40022008))

◆ I2C2_MICR_R

#define I2C2_MICR_R   (*((volatile u32 *)0x4002201C))

◆ I2C2_MIMR_R

#define I2C2_MIMR_R   (*((volatile u32 *)0x40022010))

◆ I2C2_MMIS_R

#define I2C2_MMIS_R   (*((volatile u32 *)0x40022018))

◆ I2C2_MRIS_R

#define I2C2_MRIS_R   (*((volatile u32 *)0x40022014))

◆ I2C2_MSA_R

#define I2C2_MSA_R   (*((volatile u32 *)0x40022000))

◆ I2C2_MTPR_R

#define I2C2_MTPR_R   (*((volatile u32 *)0x4002200C))

◆ I2C2_PC_R

#define I2C2_PC_R   (*((volatile u32 *)0x40022FC4))

◆ I2C2_PP_R

#define I2C2_PP_R   (*((volatile u32 *)0x40022FC0))

◆ I2C2_SACKCTL_R

#define I2C2_SACKCTL_R   (*((volatile u32 *)0x40022820))

◆ I2C2_SCSR_R

#define I2C2_SCSR_R   (*((volatile u32 *)0x40022804))

◆ I2C2_SDR_R

#define I2C2_SDR_R   (*((volatile u32 *)0x40022808))

◆ I2C2_SICR_R

#define I2C2_SICR_R   (*((volatile u32 *)0x40022818))

◆ I2C2_SIMR_R

#define I2C2_SIMR_R   (*((volatile u32 *)0x4002280C))

◆ I2C2_SMIS_R

#define I2C2_SMIS_R   (*((volatile u32 *)0x40022814))

◆ I2C2_SOAR2_R

#define I2C2_SOAR2_R   (*((volatile u32 *)0x4002281C))

◆ I2C2_SOAR_R

#define I2C2_SOAR_R   (*((volatile u32 *)0x40022800))

◆ I2C2_SRIS_R

#define I2C2_SRIS_R   (*((volatile u32 *)0x40022810))

◆ I2C3_MBMON_R

#define I2C3_MBMON_R   (*((volatile u32 *)0x4002302C))

◆ I2C3_MCLKOCNT_R

#define I2C3_MCLKOCNT_R   (*((volatile u32 *)0x40023024))

◆ I2C3_MCR2_R

#define I2C3_MCR2_R   (*((volatile u32 *)0x40023038))

◆ I2C3_MCR_R

#define I2C3_MCR_R   (*((volatile u32 *)0x40023020))

◆ I2C3_MCS_R

#define I2C3_MCS_R   (*((volatile u32 *)0x40023004))

◆ I2C3_MDR_R

#define I2C3_MDR_R   (*((volatile u32 *)0x40023008))

◆ I2C3_MICR_R

#define I2C3_MICR_R   (*((volatile u32 *)0x4002301C))

◆ I2C3_MIMR_R

#define I2C3_MIMR_R   (*((volatile u32 *)0x40023010))

◆ I2C3_MMIS_R

#define I2C3_MMIS_R   (*((volatile u32 *)0x40023018))

◆ I2C3_MRIS_R

#define I2C3_MRIS_R   (*((volatile u32 *)0x40023014))

◆ I2C3_MSA_R

#define I2C3_MSA_R   (*((volatile u32 *)0x40023000))

◆ I2C3_MTPR_R

#define I2C3_MTPR_R   (*((volatile u32 *)0x4002300C))

◆ I2C3_PC_R

#define I2C3_PC_R   (*((volatile u32 *)0x40023FC4))

◆ I2C3_PP_R

#define I2C3_PP_R   (*((volatile u32 *)0x40023FC0))

◆ I2C3_SACKCTL_R

#define I2C3_SACKCTL_R   (*((volatile u32 *)0x40023820))

◆ I2C3_SCSR_R

#define I2C3_SCSR_R   (*((volatile u32 *)0x40023804))

◆ I2C3_SDR_R

#define I2C3_SDR_R   (*((volatile u32 *)0x40023808))

◆ I2C3_SICR_R

#define I2C3_SICR_R   (*((volatile u32 *)0x40023818))

◆ I2C3_SIMR_R

#define I2C3_SIMR_R   (*((volatile u32 *)0x4002380C))

◆ I2C3_SMIS_R

#define I2C3_SMIS_R   (*((volatile u32 *)0x40023814))

◆ I2C3_SOAR2_R

#define I2C3_SOAR2_R   (*((volatile u32 *)0x4002381C))

◆ I2C3_SOAR_R

#define I2C3_SOAR_R   (*((volatile u32 *)0x40023800))

◆ I2C3_SRIS_R

#define I2C3_SRIS_R   (*((volatile u32 *)0x40023810))

◆ I2C_MBMON_SCL

#define I2C_MBMON_SCL   0x00000001

◆ I2C_MBMON_SDA

#define I2C_MBMON_SDA   0x00000002

◆ I2C_MCLKOCNT_CNTL_M

#define I2C_MCLKOCNT_CNTL_M   0x000000FF

◆ I2C_MCLKOCNT_CNTL_S

#define I2C_MCLKOCNT_CNTL_S   0

◆ I2C_MCR2_GFPW_1

#define I2C_MCR2_GFPW_1   0x00000010

◆ I2C_MCR2_GFPW_16

#define I2C_MCR2_GFPW_16   0x00000060

◆ I2C_MCR2_GFPW_2

#define I2C_MCR2_GFPW_2   0x00000020

◆ I2C_MCR2_GFPW_3

#define I2C_MCR2_GFPW_3   0x00000030

◆ I2C_MCR2_GFPW_31

#define I2C_MCR2_GFPW_31   0x00000070

◆ I2C_MCR2_GFPW_4

#define I2C_MCR2_GFPW_4   0x00000040

◆ I2C_MCR2_GFPW_8

#define I2C_MCR2_GFPW_8   0x00000050

◆ I2C_MCR2_GFPW_BYPASS

#define I2C_MCR2_GFPW_BYPASS   0x00000000

◆ I2C_MCR2_GFPW_M

#define I2C_MCR2_GFPW_M   0x00000070

◆ I2C_MCR_GFE

#define I2C_MCR_GFE   0x00000040

◆ I2C_MCR_LPBK

#define I2C_MCR_LPBK   0x00000001

◆ I2C_MCR_MFE

#define I2C_MCR_MFE   0x00000010

◆ I2C_MCR_SFE

#define I2C_MCR_SFE   0x00000020

◆ I2C_MCS_ACK

#define I2C_MCS_ACK   0x00000008

◆ I2C_MCS_ADRACK

#define I2C_MCS_ADRACK   0x00000004

◆ I2C_MCS_ARBLST

#define I2C_MCS_ARBLST   0x00000010

◆ I2C_MCS_BUSBSY

#define I2C_MCS_BUSBSY   0x00000040

◆ I2C_MCS_BUSY

#define I2C_MCS_BUSY   0x00000001

◆ I2C_MCS_CLKTO

#define I2C_MCS_CLKTO   0x00000080

◆ I2C_MCS_DATACK

#define I2C_MCS_DATACK   0x00000008

◆ I2C_MCS_ERROR

#define I2C_MCS_ERROR   0x00000002

◆ I2C_MCS_HS

#define I2C_MCS_HS   0x00000010

◆ I2C_MCS_IDLE

#define I2C_MCS_IDLE   0x00000020

◆ I2C_MCS_RUN

#define I2C_MCS_RUN   0x00000001

◆ I2C_MCS_START

#define I2C_MCS_START   0x00000002

◆ I2C_MCS_STOP

#define I2C_MCS_STOP   0x00000004

◆ I2C_MDR_DATA_M

#define I2C_MDR_DATA_M   0x000000FF

◆ I2C_MDR_DATA_S

#define I2C_MDR_DATA_S   0

◆ I2C_MICR_CLKIC

#define I2C_MICR_CLKIC   0x00000002

◆ I2C_MICR_IC

#define I2C_MICR_IC   0x00000001

◆ I2C_MIMR_CLKIM

#define I2C_MIMR_CLKIM   0x00000002

◆ I2C_MIMR_IM

#define I2C_MIMR_IM   0x00000001

◆ I2C_MMIS_CLKMIS

#define I2C_MMIS_CLKMIS   0x00000002

◆ I2C_MMIS_MIS

#define I2C_MMIS_MIS   0x00000001

◆ I2C_MRIS_CLKRIS

#define I2C_MRIS_CLKRIS   0x00000002

◆ I2C_MRIS_RIS

#define I2C_MRIS_RIS   0x00000001

◆ I2C_MSA_RS

#define I2C_MSA_RS   0x00000001

◆ I2C_MSA_SA_M

#define I2C_MSA_SA_M   0x000000FE

◆ I2C_MSA_SA_S

#define I2C_MSA_SA_S   1

◆ I2C_MTPR_HS

#define I2C_MTPR_HS   0x00000080

◆ I2C_MTPR_TPR_M

#define I2C_MTPR_TPR_M   0x0000007F

◆ I2C_MTPR_TPR_S

#define I2C_MTPR_TPR_S   0

◆ I2C_PC_HS

#define I2C_PC_HS   0x00000001

◆ I2C_PP_HS

#define I2C_PP_HS   0x00000001

◆ I2C_SACKCTL_ACKOEN

#define I2C_SACKCTL_ACKOEN   0x00000001

◆ I2C_SACKCTL_ACKOVAL

#define I2C_SACKCTL_ACKOVAL   0x00000002

◆ I2C_SCSR_DA

#define I2C_SCSR_DA   0x00000001

◆ I2C_SCSR_FBR

#define I2C_SCSR_FBR   0x00000004

◆ I2C_SCSR_OAR2SEL

#define I2C_SCSR_OAR2SEL   0x00000008

◆ I2C_SCSR_RREQ

#define I2C_SCSR_RREQ   0x00000001

◆ I2C_SCSR_TREQ

#define I2C_SCSR_TREQ   0x00000002

◆ I2C_SDR_DATA_M

#define I2C_SDR_DATA_M   0x000000FF

◆ I2C_SDR_DATA_S

#define I2C_SDR_DATA_S   0

◆ I2C_SICR_DATAIC

#define I2C_SICR_DATAIC   0x00000001

◆ I2C_SICR_STARTIC

#define I2C_SICR_STARTIC   0x00000002

◆ I2C_SICR_STOPIC

#define I2C_SICR_STOPIC   0x00000004

◆ I2C_SIMR_DATAIM

#define I2C_SIMR_DATAIM   0x00000001

◆ I2C_SIMR_STARTIM

#define I2C_SIMR_STARTIM   0x00000002

◆ I2C_SIMR_STOPIM

#define I2C_SIMR_STOPIM   0x00000004

◆ I2C_SMIS_DATAMIS

#define I2C_SMIS_DATAMIS   0x00000001

◆ I2C_SMIS_STARTMIS

#define I2C_SMIS_STARTMIS   0x00000002

◆ I2C_SMIS_STOPMIS

#define I2C_SMIS_STOPMIS   0x00000004

◆ I2C_SOAR2_OAR2_M

#define I2C_SOAR2_OAR2_M   0x0000007F

◆ I2C_SOAR2_OAR2_S

#define I2C_SOAR2_OAR2_S   0

◆ I2C_SOAR2_OAR2EN

#define I2C_SOAR2_OAR2EN   0x00000080

◆ I2C_SOAR_OAR_M

#define I2C_SOAR_OAR_M   0x0000007F

◆ I2C_SOAR_OAR_S

#define I2C_SOAR_OAR_S   0

◆ I2C_SRIS_DATARIS

#define I2C_SRIS_DATARIS   0x00000001

◆ I2C_SRIS_STARTRIS

#define I2C_SRIS_STARTRIS   0x00000002

◆ I2C_SRIS_STOPRIS

#define I2C_SRIS_STOPRIS   0x00000004

◆ INT_ADC0SS0

#define INT_ADC0SS0   30

◆ INT_ADC0SS1

#define INT_ADC0SS1   31

◆ INT_ADC0SS2

#define INT_ADC0SS2   32

◆ INT_ADC0SS3

#define INT_ADC0SS3   33

◆ INT_ADC1SS0

#define INT_ADC1SS0   64

◆ INT_ADC1SS1

#define INT_ADC1SS1   65

◆ INT_ADC1SS2

#define INT_ADC1SS2   66

◆ INT_ADC1SS3

#define INT_ADC1SS3   67

◆ INT_CAN0

#define INT_CAN0   55

◆ INT_CAN1

#define INT_CAN1   56

◆ INT_COMP0

#define INT_COMP0   41

◆ INT_COMP1

#define INT_COMP1   42

◆ INT_FLASH

#define INT_FLASH   45

◆ INT_GPIOA

#define INT_GPIOA   16

◆ INT_GPIOB

#define INT_GPIOB   17

◆ INT_GPIOC

#define INT_GPIOC   18

◆ INT_GPIOD

#define INT_GPIOD   19

◆ INT_GPIOE

#define INT_GPIOE   20

◆ INT_GPIOF

#define INT_GPIOF   46

◆ INT_HIBERNATE

#define INT_HIBERNATE   59

◆ INT_I2C0

#define INT_I2C0   24

◆ INT_I2C1

#define INT_I2C1   53

◆ INT_I2C2

#define INT_I2C2   84

◆ INT_I2C3

#define INT_I2C3   85

◆ INT_PWM0_0

#define INT_PWM0_0   26

◆ INT_PWM0_1

#define INT_PWM0_1   27

◆ INT_PWM0_2

#define INT_PWM0_2   28

◆ INT_PWM0_3

#define INT_PWM0_3   61

◆ INT_PWM0_FAULT

#define INT_PWM0_FAULT   25

◆ INT_PWM1_0

#define INT_PWM1_0   150

◆ INT_PWM1_1

#define INT_PWM1_1   151

◆ INT_PWM1_2

#define INT_PWM1_2   152

◆ INT_PWM1_3

#define INT_PWM1_3   153

◆ INT_PWM1_FAULT

#define INT_PWM1_FAULT   154

◆ INT_QEI0

#define INT_QEI0   29

◆ INT_QEI1

#define INT_QEI1   54

◆ INT_SSI0

#define INT_SSI0   23

◆ INT_SSI1

#define INT_SSI1   50

◆ INT_SSI2

#define INT_SSI2   73

◆ INT_SSI3

#define INT_SSI3   74

◆ INT_SYSCTL

#define INT_SYSCTL   44

◆ INT_SYSEXC

#define INT_SYSEXC   122

◆ INT_TIMER0A

#define INT_TIMER0A   35

◆ INT_TIMER0B

#define INT_TIMER0B   36

◆ INT_TIMER1A

#define INT_TIMER1A   37

◆ INT_TIMER1B

#define INT_TIMER1B   38

◆ INT_TIMER2A

#define INT_TIMER2A   39

◆ INT_TIMER2B

#define INT_TIMER2B   40

◆ INT_TIMER3A

#define INT_TIMER3A   51

◆ INT_TIMER3B

#define INT_TIMER3B   52

◆ INT_TIMER4A

#define INT_TIMER4A   86

◆ INT_TIMER4B

#define INT_TIMER4B   87

◆ INT_TIMER5A

#define INT_TIMER5A   108

◆ INT_TIMER5B

#define INT_TIMER5B   109

◆ INT_UART0

#define INT_UART0   21

◆ INT_UART1

#define INT_UART1   22

◆ INT_UART2

#define INT_UART2   49

◆ INT_UART3

#define INT_UART3   75

◆ INT_UART4

#define INT_UART4   76

◆ INT_UART5

#define INT_UART5   77

◆ INT_UART6

#define INT_UART6   78

◆ INT_UART7

#define INT_UART7   79

◆ INT_UDMA

#define INT_UDMA   62

◆ INT_UDMAERR

#define INT_UDMAERR   63

◆ INT_USB0

#define INT_USB0   60

◆ INT_WATCHDOG

#define INT_WATCHDOG   34

◆ INT_WTIMER0A

#define INT_WTIMER0A   110

◆ INT_WTIMER0B

#define INT_WTIMER0B   111

◆ INT_WTIMER1A

#define INT_WTIMER1A   112

◆ INT_WTIMER1B

#define INT_WTIMER1B   113

◆ INT_WTIMER2A

#define INT_WTIMER2A   114

◆ INT_WTIMER2B

#define INT_WTIMER2B   115

◆ INT_WTIMER3A

#define INT_WTIMER3A   116

◆ INT_WTIMER3B

#define INT_WTIMER3B   117

◆ INT_WTIMER4A

#define INT_WTIMER4A   118

◆ INT_WTIMER4B

#define INT_WTIMER4B   119

◆ INT_WTIMER5A

#define INT_WTIMER5A   120

◆ INT_WTIMER5B

#define INT_WTIMER5B   121

◆ NVIC_ACTIVE0_INT_M

#define NVIC_ACTIVE0_INT_M   0xFFFFFFFF

◆ NVIC_ACTIVE0_R

#define NVIC_ACTIVE0_R   (*((volatile u32 *)0xE000E300))

◆ NVIC_ACTIVE1_INT_M

#define NVIC_ACTIVE1_INT_M   0xFFFFFFFF

◆ NVIC_ACTIVE1_R

#define NVIC_ACTIVE1_R   (*((volatile u32 *)0xE000E304))

◆ NVIC_ACTIVE2_INT_M

#define NVIC_ACTIVE2_INT_M   0xFFFFFFFF

◆ NVIC_ACTIVE2_R

#define NVIC_ACTIVE2_R   (*((volatile u32 *)0xE000E308))

◆ NVIC_ACTIVE3_INT_M

#define NVIC_ACTIVE3_INT_M   0xFFFFFFFF

◆ NVIC_ACTIVE3_R

#define NVIC_ACTIVE3_R   (*((volatile u32 *)0xE000E30C))

◆ NVIC_ACTIVE4_INT_M

#define NVIC_ACTIVE4_INT_M   0x000007FF

◆ NVIC_ACTIVE4_R

#define NVIC_ACTIVE4_R   (*((volatile u32 *)0xE000E310))

◆ NVIC_ACTLR_DISFOLD

#define NVIC_ACTLR_DISFOLD   0x00000004

◆ NVIC_ACTLR_DISFPCA

#define NVIC_ACTLR_DISFPCA   0x00000100

◆ NVIC_ACTLR_DISMCYC

#define NVIC_ACTLR_DISMCYC   0x00000001

◆ NVIC_ACTLR_DISOOFP

#define NVIC_ACTLR_DISOOFP   0x00000200

◆ NVIC_ACTLR_DISWBUF

#define NVIC_ACTLR_DISWBUF   0x00000002

◆ NVIC_ACTLR_R

#define NVIC_ACTLR_R   (*((volatile u32 *)0xE000E008))

◆ NVIC_APINT_ENDIANESS

#define NVIC_APINT_ENDIANESS   0x00008000

◆ NVIC_APINT_PRIGROUP_0_8

#define NVIC_APINT_PRIGROUP_0_8   0x00000700

◆ NVIC_APINT_PRIGROUP_1_7

#define NVIC_APINT_PRIGROUP_1_7   0x00000600

◆ NVIC_APINT_PRIGROUP_2_6

#define NVIC_APINT_PRIGROUP_2_6   0x00000500

◆ NVIC_APINT_PRIGROUP_3_5

#define NVIC_APINT_PRIGROUP_3_5   0x00000400

◆ NVIC_APINT_PRIGROUP_4_4

#define NVIC_APINT_PRIGROUP_4_4   0x00000300

◆ NVIC_APINT_PRIGROUP_5_3

#define NVIC_APINT_PRIGROUP_5_3   0x00000200

◆ NVIC_APINT_PRIGROUP_6_2

#define NVIC_APINT_PRIGROUP_6_2   0x00000100

◆ NVIC_APINT_PRIGROUP_7_1

#define NVIC_APINT_PRIGROUP_7_1   0x00000000

◆ NVIC_APINT_PRIGROUP_M

#define NVIC_APINT_PRIGROUP_M   0x00000700

◆ NVIC_APINT_R

#define NVIC_APINT_R   (*((volatile u32 *)0xE000ED0C))

◆ NVIC_APINT_SYSRESETREQ

#define NVIC_APINT_SYSRESETREQ   0x00000004

◆ NVIC_APINT_VECT_CLR_ACT

#define NVIC_APINT_VECT_CLR_ACT   0x00000002

◆ NVIC_APINT_VECT_RESET

#define NVIC_APINT_VECT_RESET   0x00000001

◆ NVIC_APINT_VECTKEY

#define NVIC_APINT_VECTKEY   0x05FA0000

◆ NVIC_APINT_VECTKEY_M

#define NVIC_APINT_VECTKEY_M   0xFFFF0000

◆ NVIC_CFG_CTRL_BASE_THR

#define NVIC_CFG_CTRL_BASE_THR   0x00000001

◆ NVIC_CFG_CTRL_BFHFNMIGN

#define NVIC_CFG_CTRL_BFHFNMIGN   0x00000100

◆ NVIC_CFG_CTRL_DIV0

#define NVIC_CFG_CTRL_DIV0   0x00000010

◆ NVIC_CFG_CTRL_MAIN_PEND

#define NVIC_CFG_CTRL_MAIN_PEND   0x00000002

◆ NVIC_CFG_CTRL_R

#define NVIC_CFG_CTRL_R   (*((volatile u32 *)0xE000ED14))

◆ NVIC_CFG_CTRL_STKALIGN

#define NVIC_CFG_CTRL_STKALIGN   0x00000200

◆ NVIC_CFG_CTRL_UNALIGNED

#define NVIC_CFG_CTRL_UNALIGNED   0x00000008

◆ NVIC_CPAC_CP10_DIS

#define NVIC_CPAC_CP10_DIS   0x00000000

◆ NVIC_CPAC_CP10_FULL

#define NVIC_CPAC_CP10_FULL   0x00300000

◆ NVIC_CPAC_CP10_M

#define NVIC_CPAC_CP10_M   0x00300000

◆ NVIC_CPAC_CP10_PRIV

#define NVIC_CPAC_CP10_PRIV   0x00100000

◆ NVIC_CPAC_CP11_DIS

#define NVIC_CPAC_CP11_DIS   0x00000000

◆ NVIC_CPAC_CP11_FULL

#define NVIC_CPAC_CP11_FULL   0x00C00000

◆ NVIC_CPAC_CP11_M

#define NVIC_CPAC_CP11_M   0x00C00000

◆ NVIC_CPAC_CP11_PRIV

#define NVIC_CPAC_CP11_PRIV   0x00400000

◆ NVIC_CPAC_R

#define NVIC_CPAC_R   (*((volatile u32 *)0xE000ED88))

◆ NVIC_CPUID_CON_M

#define NVIC_CPUID_CON_M   0x000F0000

◆ NVIC_CPUID_IMP_ARM

#define NVIC_CPUID_IMP_ARM   0x41000000

◆ NVIC_CPUID_IMP_M

#define NVIC_CPUID_IMP_M   0xFF000000

◆ NVIC_CPUID_PARTNO_CM4

#define NVIC_CPUID_PARTNO_CM4   0x0000C240

◆ NVIC_CPUID_PARTNO_M

#define NVIC_CPUID_PARTNO_M   0x0000FFF0

◆ NVIC_CPUID_R

#define NVIC_CPUID_R   (*((volatile u32 *)0xE000ED00))

◆ NVIC_CPUID_REV_M

#define NVIC_CPUID_REV_M   0x0000000F

◆ NVIC_CPUID_VAR_M

#define NVIC_CPUID_VAR_M   0x00F00000

◆ NVIC_DBG_CTRL_C_DEBUGEN

#define NVIC_DBG_CTRL_C_DEBUGEN   0x00000001

◆ NVIC_DBG_CTRL_C_HALT

#define NVIC_DBG_CTRL_C_HALT   0x00000002

◆ NVIC_DBG_CTRL_C_MASKINT

#define NVIC_DBG_CTRL_C_MASKINT   0x00000008

◆ NVIC_DBG_CTRL_C_SNAPSTALL

#define NVIC_DBG_CTRL_C_SNAPSTALL    0x00000020

◆ NVIC_DBG_CTRL_C_STEP

#define NVIC_DBG_CTRL_C_STEP   0x00000004

◆ NVIC_DBG_CTRL_DBGKEY

#define NVIC_DBG_CTRL_DBGKEY   0xA05F0000

◆ NVIC_DBG_CTRL_DBGKEY_M

#define NVIC_DBG_CTRL_DBGKEY_M   0xFFFF0000

◆ NVIC_DBG_CTRL_R

#define NVIC_DBG_CTRL_R   (*((volatile u32 *)0xE000EDF0))

◆ NVIC_DBG_CTRL_S_HALT

#define NVIC_DBG_CTRL_S_HALT   0x00020000

◆ NVIC_DBG_CTRL_S_LOCKUP

#define NVIC_DBG_CTRL_S_LOCKUP   0x00080000

◆ NVIC_DBG_CTRL_S_REGRDY

#define NVIC_DBG_CTRL_S_REGRDY   0x00010000

◆ NVIC_DBG_CTRL_S_RESET_ST

#define NVIC_DBG_CTRL_S_RESET_ST    0x02000000

◆ NVIC_DBG_CTRL_S_RETIRE_ST

#define NVIC_DBG_CTRL_S_RETIRE_ST    0x01000000

◆ NVIC_DBG_CTRL_S_SLEEP

#define NVIC_DBG_CTRL_S_SLEEP   0x00040000

◆ NVIC_DBG_DATA_M

#define NVIC_DBG_DATA_M   0xFFFFFFFF

◆ NVIC_DBG_DATA_R

#define NVIC_DBG_DATA_R   (*((volatile u32 *)0xE000EDF8))

◆ NVIC_DBG_DATA_S

#define NVIC_DBG_DATA_S   0

◆ NVIC_DBG_INT_BUSERR

#define NVIC_DBG_INT_BUSERR   0x00000100

◆ NVIC_DBG_INT_CHKERR

#define NVIC_DBG_INT_CHKERR   0x00000040

◆ NVIC_DBG_INT_HARDERR

#define NVIC_DBG_INT_HARDERR   0x00000400

◆ NVIC_DBG_INT_INTERR

#define NVIC_DBG_INT_INTERR   0x00000200

◆ NVIC_DBG_INT_MMERR

#define NVIC_DBG_INT_MMERR   0x00000010

◆ NVIC_DBG_INT_NOCPERR

#define NVIC_DBG_INT_NOCPERR   0x00000020

◆ NVIC_DBG_INT_R

#define NVIC_DBG_INT_R   (*((volatile u32 *)0xE000EDFC))

◆ NVIC_DBG_INT_RESET

#define NVIC_DBG_INT_RESET   0x00000008

◆ NVIC_DBG_INT_RSTPENDCLR

#define NVIC_DBG_INT_RSTPENDCLR   0x00000004

◆ NVIC_DBG_INT_RSTPENDING

#define NVIC_DBG_INT_RSTPENDING   0x00000002

◆ NVIC_DBG_INT_RSTVCATCH

#define NVIC_DBG_INT_RSTVCATCH   0x00000001

◆ NVIC_DBG_INT_STATERR

#define NVIC_DBG_INT_STATERR   0x00000080

◆ NVIC_DBG_XFER_R

#define NVIC_DBG_XFER_R   (*((volatile u32 *)0xE000EDF4))

◆ NVIC_DBG_XFER_REG_CFBP

#define NVIC_DBG_XFER_REG_CFBP   0x00000014

◆ NVIC_DBG_XFER_REG_DSP

#define NVIC_DBG_XFER_REG_DSP   0x00000013

◆ NVIC_DBG_XFER_REG_FLAGS

#define NVIC_DBG_XFER_REG_FLAGS   0x00000010

◆ NVIC_DBG_XFER_REG_MSP

#define NVIC_DBG_XFER_REG_MSP   0x00000011

◆ NVIC_DBG_XFER_REG_PSP

#define NVIC_DBG_XFER_REG_PSP   0x00000012

◆ NVIC_DBG_XFER_REG_R0

#define NVIC_DBG_XFER_REG_R0   0x00000000

◆ NVIC_DBG_XFER_REG_R1

#define NVIC_DBG_XFER_REG_R1   0x00000001

◆ NVIC_DBG_XFER_REG_R10

#define NVIC_DBG_XFER_REG_R10   0x0000000A

◆ NVIC_DBG_XFER_REG_R11

#define NVIC_DBG_XFER_REG_R11   0x0000000B

◆ NVIC_DBG_XFER_REG_R12

#define NVIC_DBG_XFER_REG_R12   0x0000000C

◆ NVIC_DBG_XFER_REG_R13

#define NVIC_DBG_XFER_REG_R13   0x0000000D

◆ NVIC_DBG_XFER_REG_R14

#define NVIC_DBG_XFER_REG_R14   0x0000000E

◆ NVIC_DBG_XFER_REG_R15

#define NVIC_DBG_XFER_REG_R15   0x0000000F

◆ NVIC_DBG_XFER_REG_R2

#define NVIC_DBG_XFER_REG_R2   0x00000002

◆ NVIC_DBG_XFER_REG_R3

#define NVIC_DBG_XFER_REG_R3   0x00000003

◆ NVIC_DBG_XFER_REG_R4

#define NVIC_DBG_XFER_REG_R4   0x00000004

◆ NVIC_DBG_XFER_REG_R5

#define NVIC_DBG_XFER_REG_R5   0x00000005

◆ NVIC_DBG_XFER_REG_R6

#define NVIC_DBG_XFER_REG_R6   0x00000006

◆ NVIC_DBG_XFER_REG_R7

#define NVIC_DBG_XFER_REG_R7   0x00000007

◆ NVIC_DBG_XFER_REG_R8

#define NVIC_DBG_XFER_REG_R8   0x00000008

◆ NVIC_DBG_XFER_REG_R9

#define NVIC_DBG_XFER_REG_R9   0x00000009

◆ NVIC_DBG_XFER_REG_SEL_M

#define NVIC_DBG_XFER_REG_SEL_M   0x0000001F

◆ NVIC_DBG_XFER_REG_WNR

#define NVIC_DBG_XFER_REG_WNR   0x00010000

◆ NVIC_DEBUG_STAT_BKPT

#define NVIC_DEBUG_STAT_BKPT   0x00000002

◆ NVIC_DEBUG_STAT_DWTTRAP

#define NVIC_DEBUG_STAT_DWTTRAP   0x00000004

◆ NVIC_DEBUG_STAT_EXTRNL

#define NVIC_DEBUG_STAT_EXTRNL   0x00000010

◆ NVIC_DEBUG_STAT_HALTED

#define NVIC_DEBUG_STAT_HALTED   0x00000001

◆ NVIC_DEBUG_STAT_R

#define NVIC_DEBUG_STAT_R   (*((volatile u32 *)0xE000ED30))

◆ NVIC_DEBUG_STAT_VCATCH

#define NVIC_DEBUG_STAT_VCATCH   0x00000008

◆ NVIC_DIS0_INT_M

#define NVIC_DIS0_INT_M   0xFFFFFFFF

◆ NVIC_DIS0_R

#define NVIC_DIS0_R   (*((volatile u32 *)0xE000E180))

◆ NVIC_DIS1_INT_M

#define NVIC_DIS1_INT_M   0xFFFFFFFF

◆ NVIC_DIS1_R

#define NVIC_DIS1_R   (*((volatile u32 *)0xE000E184))

◆ NVIC_DIS2_INT_M

#define NVIC_DIS2_INT_M   0xFFFFFFFF

◆ NVIC_DIS2_R

#define NVIC_DIS2_R   (*((volatile u32 *)0xE000E188))

◆ NVIC_DIS3_INT_M

#define NVIC_DIS3_INT_M   0xFFFFFFFF

◆ NVIC_DIS3_R

#define NVIC_DIS3_R   (*((volatile u32 *)0xE000E18C))

◆ NVIC_DIS4_INT_M

#define NVIC_DIS4_INT_M   0x000007FF

◆ NVIC_DIS4_R

#define NVIC_DIS4_R   (*((volatile u32 *)0xE000E190))

◆ NVIC_EN0_INT_M

#define NVIC_EN0_INT_M   0xFFFFFFFF

◆ NVIC_EN0_R

#define NVIC_EN0_R   (*((volatile u32 *)0xE000E100))

◆ NVIC_EN1_INT_M

#define NVIC_EN1_INT_M   0xFFFFFFFF

◆ NVIC_EN1_R

#define NVIC_EN1_R   (*((volatile u32 *)0xE000E104))

◆ NVIC_EN2_INT_M

#define NVIC_EN2_INT_M   0xFFFFFFFF

◆ NVIC_EN2_R

#define NVIC_EN2_R   (*((volatile u32 *)0xE000E108))

◆ NVIC_EN3_INT_M

#define NVIC_EN3_INT_M   0xFFFFFFFF

◆ NVIC_EN3_R

#define NVIC_EN3_R   (*((volatile u32 *)0xE000E10C))

◆ NVIC_EN4_INT_M

#define NVIC_EN4_INT_M   0x000007FF

◆ NVIC_EN4_R

#define NVIC_EN4_R   (*((volatile u32 *)0xE000E110))

◆ NVIC_FAULT_ADDR_M

#define NVIC_FAULT_ADDR_M   0xFFFFFFFF

◆ NVIC_FAULT_ADDR_R

#define NVIC_FAULT_ADDR_R   (*((volatile u32 *)0xE000ED38))

◆ NVIC_FAULT_ADDR_S

#define NVIC_FAULT_ADDR_S   0

◆ NVIC_FAULT_STAT_BFARV

#define NVIC_FAULT_STAT_BFARV   0x00008000

◆ NVIC_FAULT_STAT_BLSPERR

#define NVIC_FAULT_STAT_BLSPERR   0x00002000

◆ NVIC_FAULT_STAT_BSTKE

#define NVIC_FAULT_STAT_BSTKE   0x00001000

◆ NVIC_FAULT_STAT_BUSTKE

#define NVIC_FAULT_STAT_BUSTKE   0x00000800

◆ NVIC_FAULT_STAT_DERR

#define NVIC_FAULT_STAT_DERR   0x00000002

◆ NVIC_FAULT_STAT_DIV0

#define NVIC_FAULT_STAT_DIV0   0x02000000

◆ NVIC_FAULT_STAT_IBUS

#define NVIC_FAULT_STAT_IBUS   0x00000100

◆ NVIC_FAULT_STAT_IERR

#define NVIC_FAULT_STAT_IERR   0x00000001

◆ NVIC_FAULT_STAT_IMPRE

#define NVIC_FAULT_STAT_IMPRE   0x00000400

◆ NVIC_FAULT_STAT_INVPC

#define NVIC_FAULT_STAT_INVPC   0x00040000

◆ NVIC_FAULT_STAT_INVSTAT

#define NVIC_FAULT_STAT_INVSTAT   0x00020000

◆ NVIC_FAULT_STAT_MLSPERR

#define NVIC_FAULT_STAT_MLSPERR   0x00000020

◆ NVIC_FAULT_STAT_MMARV

#define NVIC_FAULT_STAT_MMARV   0x00000080

◆ NVIC_FAULT_STAT_MSTKE

#define NVIC_FAULT_STAT_MSTKE   0x00000010

◆ NVIC_FAULT_STAT_MUSTKE

#define NVIC_FAULT_STAT_MUSTKE   0x00000008

◆ NVIC_FAULT_STAT_NOCP

#define NVIC_FAULT_STAT_NOCP   0x00080000

◆ NVIC_FAULT_STAT_PRECISE

#define NVIC_FAULT_STAT_PRECISE   0x00000200

◆ NVIC_FAULT_STAT_R

#define NVIC_FAULT_STAT_R   (*((volatile u32 *)0xE000ED28))

◆ NVIC_FAULT_STAT_UNALIGN

#define NVIC_FAULT_STAT_UNALIGN   0x01000000

◆ NVIC_FAULT_STAT_UNDEF

#define NVIC_FAULT_STAT_UNDEF   0x00010000

◆ NVIC_FPCA_ADDRESS_M

#define NVIC_FPCA_ADDRESS_M   0xFFFFFFF8

◆ NVIC_FPCA_ADDRESS_S

#define NVIC_FPCA_ADDRESS_S   3

◆ NVIC_FPCA_R

#define NVIC_FPCA_R   (*((volatile u32 *)0xE000EF38))

◆ NVIC_FPCC_ASPEN

#define NVIC_FPCC_ASPEN   0x80000000

◆ NVIC_FPCC_BFRDY

#define NVIC_FPCC_BFRDY   0x00000040

◆ NVIC_FPCC_HFRDY

#define NVIC_FPCC_HFRDY   0x00000010

◆ NVIC_FPCC_LSPACT

#define NVIC_FPCC_LSPACT   0x00000001

◆ NVIC_FPCC_LSPEN

#define NVIC_FPCC_LSPEN   0x40000000

◆ NVIC_FPCC_MMRDY

#define NVIC_FPCC_MMRDY   0x00000020

◆ NVIC_FPCC_MONRDY

#define NVIC_FPCC_MONRDY   0x00000100

◆ NVIC_FPCC_R

#define NVIC_FPCC_R   (*((volatile u32 *)0xE000EF34))

◆ NVIC_FPCC_THREAD

#define NVIC_FPCC_THREAD   0x00000008

◆ NVIC_FPCC_USER

#define NVIC_FPCC_USER   0x00000002

◆ NVIC_FPDSC_AHP

#define NVIC_FPDSC_AHP   0x04000000

◆ NVIC_FPDSC_DN

#define NVIC_FPDSC_DN   0x02000000

◆ NVIC_FPDSC_FZ

#define NVIC_FPDSC_FZ   0x01000000

◆ NVIC_FPDSC_R

#define NVIC_FPDSC_R   (*((volatile u32 *)0xE000EF3C))

◆ NVIC_FPDSC_RMODE_M

#define NVIC_FPDSC_RMODE_M   0x00C00000

◆ NVIC_FPDSC_RMODE_RM

#define NVIC_FPDSC_RMODE_RM   0x00800000

◆ NVIC_FPDSC_RMODE_RN

#define NVIC_FPDSC_RMODE_RN   0x00000000

◆ NVIC_FPDSC_RMODE_RP

#define NVIC_FPDSC_RMODE_RP   0x00400000

◆ NVIC_FPDSC_RMODE_RZ

#define NVIC_FPDSC_RMODE_RZ   0x00C00000

◆ NVIC_HFAULT_STAT_DBG

#define NVIC_HFAULT_STAT_DBG   0x80000000

◆ NVIC_HFAULT_STAT_FORCED

#define NVIC_HFAULT_STAT_FORCED   0x40000000

◆ NVIC_HFAULT_STAT_R

#define NVIC_HFAULT_STAT_R   (*((volatile u32 *)0xE000ED2C))

◆ NVIC_HFAULT_STAT_VECT

#define NVIC_HFAULT_STAT_VECT   0x00000002

◆ NVIC_INT_CTRL_ISR_PEND

#define NVIC_INT_CTRL_ISR_PEND   0x00400000

◆ NVIC_INT_CTRL_ISR_PRE

#define NVIC_INT_CTRL_ISR_PRE   0x00800000

◆ NVIC_INT_CTRL_NMI_SET

#define NVIC_INT_CTRL_NMI_SET   0x80000000

◆ NVIC_INT_CTRL_PEND_SV

#define NVIC_INT_CTRL_PEND_SV   0x10000000

◆ NVIC_INT_CTRL_PENDSTCLR

#define NVIC_INT_CTRL_PENDSTCLR   0x02000000

◆ NVIC_INT_CTRL_PENDSTSET

#define NVIC_INT_CTRL_PENDSTSET   0x04000000

◆ NVIC_INT_CTRL_R

#define NVIC_INT_CTRL_R   (*((volatile u32 *)0xE000ED04))

◆ NVIC_INT_CTRL_RET_BASE

#define NVIC_INT_CTRL_RET_BASE   0x00000800

◆ NVIC_INT_CTRL_UNPEND_SV

#define NVIC_INT_CTRL_UNPEND_SV   0x08000000

◆ NVIC_INT_CTRL_VEC_ACT_M

#define NVIC_INT_CTRL_VEC_ACT_M   0x000000FF

◆ NVIC_INT_CTRL_VEC_ACT_S

#define NVIC_INT_CTRL_VEC_ACT_S   0

◆ NVIC_INT_CTRL_VEC_PEN_BUS

#define NVIC_INT_CTRL_VEC_PEN_BUS    0x00005000

◆ NVIC_INT_CTRL_VEC_PEN_HARD

#define NVIC_INT_CTRL_VEC_PEN_HARD    0x00003000

◆ NVIC_INT_CTRL_VEC_PEN_M

#define NVIC_INT_CTRL_VEC_PEN_M   0x000FF000

◆ NVIC_INT_CTRL_VEC_PEN_MEM

#define NVIC_INT_CTRL_VEC_PEN_MEM    0x00004000

◆ NVIC_INT_CTRL_VEC_PEN_NMI

#define NVIC_INT_CTRL_VEC_PEN_NMI    0x00002000

◆ NVIC_INT_CTRL_VEC_PEN_PNDSV

#define NVIC_INT_CTRL_VEC_PEN_PNDSV    0x0000E000

◆ NVIC_INT_CTRL_VEC_PEN_SVC

#define NVIC_INT_CTRL_VEC_PEN_SVC    0x0000B000

◆ NVIC_INT_CTRL_VEC_PEN_TICK

#define NVIC_INT_CTRL_VEC_PEN_TICK    0x0000F000

◆ NVIC_INT_CTRL_VEC_PEN_USG

#define NVIC_INT_CTRL_VEC_PEN_USG    0x00006000

◆ NVIC_MM_ADDR_M

#define NVIC_MM_ADDR_M   0xFFFFFFFF

◆ NVIC_MM_ADDR_R

#define NVIC_MM_ADDR_R   (*((volatile u32 *)0xE000ED34))

◆ NVIC_MM_ADDR_S

#define NVIC_MM_ADDR_S   0

◆ NVIC_MPU_ATTR1_AP_M

#define NVIC_MPU_ATTR1_AP_M   0x07000000

◆ NVIC_MPU_ATTR1_BUFFRABLE

#define NVIC_MPU_ATTR1_BUFFRABLE    0x00010000

◆ NVIC_MPU_ATTR1_CACHEABLE

#define NVIC_MPU_ATTR1_CACHEABLE    0x00020000

◆ NVIC_MPU_ATTR1_ENABLE

#define NVIC_MPU_ATTR1_ENABLE   0x00000001

◆ NVIC_MPU_ATTR1_R

#define NVIC_MPU_ATTR1_R   (*((volatile u32 *)0xE000EDA8))

◆ NVIC_MPU_ATTR1_SHAREABLE

#define NVIC_MPU_ATTR1_SHAREABLE    0x00040000

◆ NVIC_MPU_ATTR1_SIZE_M

#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E

◆ NVIC_MPU_ATTR1_SRD_M

#define NVIC_MPU_ATTR1_SRD_M   0x0000FF00

◆ NVIC_MPU_ATTR1_TEX_M

#define NVIC_MPU_ATTR1_TEX_M   0x00380000

◆ NVIC_MPU_ATTR1_XN

#define NVIC_MPU_ATTR1_XN   0x10000000

◆ NVIC_MPU_ATTR2_AP_M

#define NVIC_MPU_ATTR2_AP_M   0x07000000

◆ NVIC_MPU_ATTR2_BUFFRABLE

#define NVIC_MPU_ATTR2_BUFFRABLE    0x00010000

◆ NVIC_MPU_ATTR2_CACHEABLE

#define NVIC_MPU_ATTR2_CACHEABLE    0x00020000

◆ NVIC_MPU_ATTR2_ENABLE

#define NVIC_MPU_ATTR2_ENABLE   0x00000001

◆ NVIC_MPU_ATTR2_R

#define NVIC_MPU_ATTR2_R   (*((volatile u32 *)0xE000EDB0))

◆ NVIC_MPU_ATTR2_SHAREABLE

#define NVIC_MPU_ATTR2_SHAREABLE    0x00040000

◆ NVIC_MPU_ATTR2_SIZE_M

#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E

◆ NVIC_MPU_ATTR2_SRD_M

#define NVIC_MPU_ATTR2_SRD_M   0x0000FF00

◆ NVIC_MPU_ATTR2_TEX_M

#define NVIC_MPU_ATTR2_TEX_M   0x00380000

◆ NVIC_MPU_ATTR2_XN

#define NVIC_MPU_ATTR2_XN   0x10000000

◆ NVIC_MPU_ATTR3_AP_M

#define NVIC_MPU_ATTR3_AP_M   0x07000000

◆ NVIC_MPU_ATTR3_BUFFRABLE

#define NVIC_MPU_ATTR3_BUFFRABLE    0x00010000

◆ NVIC_MPU_ATTR3_CACHEABLE

#define NVIC_MPU_ATTR3_CACHEABLE    0x00020000

◆ NVIC_MPU_ATTR3_ENABLE

#define NVIC_MPU_ATTR3_ENABLE   0x00000001

◆ NVIC_MPU_ATTR3_R

#define NVIC_MPU_ATTR3_R   (*((volatile u32 *)0xE000EDB8))

◆ NVIC_MPU_ATTR3_SHAREABLE

#define NVIC_MPU_ATTR3_SHAREABLE    0x00040000

◆ NVIC_MPU_ATTR3_SIZE_M

#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E

◆ NVIC_MPU_ATTR3_SRD_M

#define NVIC_MPU_ATTR3_SRD_M   0x0000FF00

◆ NVIC_MPU_ATTR3_TEX_M

#define NVIC_MPU_ATTR3_TEX_M   0x00380000

◆ NVIC_MPU_ATTR3_XN

#define NVIC_MPU_ATTR3_XN   0x10000000

◆ NVIC_MPU_ATTR_AP_M

#define NVIC_MPU_ATTR_AP_M   0x07000000

◆ NVIC_MPU_ATTR_BUFFRABLE

#define NVIC_MPU_ATTR_BUFFRABLE   0x00010000

◆ NVIC_MPU_ATTR_CACHEABLE

#define NVIC_MPU_ATTR_CACHEABLE   0x00020000

◆ NVIC_MPU_ATTR_ENABLE

#define NVIC_MPU_ATTR_ENABLE   0x00000001

◆ NVIC_MPU_ATTR_R

#define NVIC_MPU_ATTR_R   (*((volatile u32 *)0xE000EDA0))

◆ NVIC_MPU_ATTR_SHAREABLE

#define NVIC_MPU_ATTR_SHAREABLE   0x00040000

◆ NVIC_MPU_ATTR_SIZE_M

#define NVIC_MPU_ATTR_SIZE_M   0x0000003E

◆ NVIC_MPU_ATTR_SRD_M

#define NVIC_MPU_ATTR_SRD_M   0x0000FF00

◆ NVIC_MPU_ATTR_TEX_M

#define NVIC_MPU_ATTR_TEX_M   0x00380000

◆ NVIC_MPU_ATTR_XN

#define NVIC_MPU_ATTR_XN   0x10000000

◆ NVIC_MPU_BASE1_ADDR_M

#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0

◆ NVIC_MPU_BASE1_ADDR_S

#define NVIC_MPU_BASE1_ADDR_S   5

◆ NVIC_MPU_BASE1_R

#define NVIC_MPU_BASE1_R   (*((volatile u32 *)0xE000EDA4))

◆ NVIC_MPU_BASE1_REGION_M

#define NVIC_MPU_BASE1_REGION_M   0x00000007

◆ NVIC_MPU_BASE1_REGION_S

#define NVIC_MPU_BASE1_REGION_S   0

◆ NVIC_MPU_BASE1_VALID

#define NVIC_MPU_BASE1_VALID   0x00000010

◆ NVIC_MPU_BASE2_ADDR_M

#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0

◆ NVIC_MPU_BASE2_ADDR_S

#define NVIC_MPU_BASE2_ADDR_S   5

◆ NVIC_MPU_BASE2_R

#define NVIC_MPU_BASE2_R   (*((volatile u32 *)0xE000EDAC))

◆ NVIC_MPU_BASE2_REGION_M

#define NVIC_MPU_BASE2_REGION_M   0x00000007

◆ NVIC_MPU_BASE2_REGION_S

#define NVIC_MPU_BASE2_REGION_S   0

◆ NVIC_MPU_BASE2_VALID

#define NVIC_MPU_BASE2_VALID   0x00000010

◆ NVIC_MPU_BASE3_ADDR_M

#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0

◆ NVIC_MPU_BASE3_ADDR_S

#define NVIC_MPU_BASE3_ADDR_S   5

◆ NVIC_MPU_BASE3_R

#define NVIC_MPU_BASE3_R   (*((volatile u32 *)0xE000EDB4))

◆ NVIC_MPU_BASE3_REGION_M

#define NVIC_MPU_BASE3_REGION_M   0x00000007

◆ NVIC_MPU_BASE3_REGION_S

#define NVIC_MPU_BASE3_REGION_S   0

◆ NVIC_MPU_BASE3_VALID

#define NVIC_MPU_BASE3_VALID   0x00000010

◆ NVIC_MPU_BASE_ADDR_M

#define NVIC_MPU_BASE_ADDR_M   0xFFFFFFE0

◆ NVIC_MPU_BASE_ADDR_S

#define NVIC_MPU_BASE_ADDR_S   5

◆ NVIC_MPU_BASE_R

#define NVIC_MPU_BASE_R   (*((volatile u32 *)0xE000ED9C))

◆ NVIC_MPU_BASE_REGION_M

#define NVIC_MPU_BASE_REGION_M   0x00000007

◆ NVIC_MPU_BASE_REGION_S

#define NVIC_MPU_BASE_REGION_S   0

◆ NVIC_MPU_BASE_VALID

#define NVIC_MPU_BASE_VALID   0x00000010

◆ NVIC_MPU_CTRL_ENABLE

#define NVIC_MPU_CTRL_ENABLE   0x00000001

◆ NVIC_MPU_CTRL_HFNMIENA

#define NVIC_MPU_CTRL_HFNMIENA   0x00000002

◆ NVIC_MPU_CTRL_PRIVDEFEN

#define NVIC_MPU_CTRL_PRIVDEFEN   0x00000004

◆ NVIC_MPU_CTRL_R

#define NVIC_MPU_CTRL_R   (*((volatile u32 *)0xE000ED94))

◆ NVIC_MPU_NUMBER_M

#define NVIC_MPU_NUMBER_M   0x00000007

◆ NVIC_MPU_NUMBER_R

#define NVIC_MPU_NUMBER_R   (*((volatile u32 *)0xE000ED98))

◆ NVIC_MPU_NUMBER_S

#define NVIC_MPU_NUMBER_S   0

◆ NVIC_MPU_TYPE_DREGION_M

#define NVIC_MPU_TYPE_DREGION_M   0x0000FF00

◆ NVIC_MPU_TYPE_DREGION_S

#define NVIC_MPU_TYPE_DREGION_S   8

◆ NVIC_MPU_TYPE_IREGION_M

#define NVIC_MPU_TYPE_IREGION_M   0x00FF0000

◆ NVIC_MPU_TYPE_IREGION_S

#define NVIC_MPU_TYPE_IREGION_S   16

◆ NVIC_MPU_TYPE_R

#define NVIC_MPU_TYPE_R   (*((volatile u32 *)0xE000ED90))

◆ NVIC_MPU_TYPE_SEPARATE

#define NVIC_MPU_TYPE_SEPARATE   0x00000001

◆ NVIC_PEND0_INT_M

#define NVIC_PEND0_INT_M   0xFFFFFFFF

◆ NVIC_PEND0_R

#define NVIC_PEND0_R   (*((volatile u32 *)0xE000E200))

◆ NVIC_PEND1_INT_M

#define NVIC_PEND1_INT_M   0xFFFFFFFF

◆ NVIC_PEND1_R

#define NVIC_PEND1_R   (*((volatile u32 *)0xE000E204))

◆ NVIC_PEND2_INT_M

#define NVIC_PEND2_INT_M   0xFFFFFFFF

◆ NVIC_PEND2_R

#define NVIC_PEND2_R   (*((volatile u32 *)0xE000E208))

◆ NVIC_PEND3_INT_M

#define NVIC_PEND3_INT_M   0xFFFFFFFF

◆ NVIC_PEND3_R

#define NVIC_PEND3_R   (*((volatile u32 *)0xE000E20C))

◆ NVIC_PEND4_INT_M

#define NVIC_PEND4_INT_M   0x000007FF

◆ NVIC_PEND4_R

#define NVIC_PEND4_R   (*((volatile u32 *)0xE000E210))

◆ NVIC_PRI0_INT0_M

#define NVIC_PRI0_INT0_M   0x000000E0

◆ NVIC_PRI0_INT0_S

#define NVIC_PRI0_INT0_S   5

◆ NVIC_PRI0_INT1_M

#define NVIC_PRI0_INT1_M   0x0000E000

◆ NVIC_PRI0_INT1_S

#define NVIC_PRI0_INT1_S   13

◆ NVIC_PRI0_INT2_M

#define NVIC_PRI0_INT2_M   0x00E00000

◆ NVIC_PRI0_INT2_S

#define NVIC_PRI0_INT2_S   21

◆ NVIC_PRI0_INT3_M

#define NVIC_PRI0_INT3_M   0xE0000000

◆ NVIC_PRI0_INT3_S

#define NVIC_PRI0_INT3_S   29

◆ NVIC_PRI0_R

#define NVIC_PRI0_R   (*((volatile u32 *)0xE000E400))

◆ NVIC_PRI10_INT40_M

#define NVIC_PRI10_INT40_M   0x000000E0

◆ NVIC_PRI10_INT40_S

#define NVIC_PRI10_INT40_S   5

◆ NVIC_PRI10_INT41_M

#define NVIC_PRI10_INT41_M   0x0000E000

◆ NVIC_PRI10_INT41_S

#define NVIC_PRI10_INT41_S   13

◆ NVIC_PRI10_INT42_M

#define NVIC_PRI10_INT42_M   0x00E00000

◆ NVIC_PRI10_INT42_S

#define NVIC_PRI10_INT42_S   21

◆ NVIC_PRI10_INT43_M

#define NVIC_PRI10_INT43_M   0xE0000000

◆ NVIC_PRI10_INT43_S

#define NVIC_PRI10_INT43_S   29

◆ NVIC_PRI10_R

#define NVIC_PRI10_R   (*((volatile u32 *)0xE000E428))

◆ NVIC_PRI11_INT44_M

#define NVIC_PRI11_INT44_M   0x000000E0

◆ NVIC_PRI11_INT44_S

#define NVIC_PRI11_INT44_S   5

◆ NVIC_PRI11_INT45_M

#define NVIC_PRI11_INT45_M   0x0000E000

◆ NVIC_PRI11_INT45_S

#define NVIC_PRI11_INT45_S   13

◆ NVIC_PRI11_INT46_M

#define NVIC_PRI11_INT46_M   0x00E00000

◆ NVIC_PRI11_INT46_S

#define NVIC_PRI11_INT46_S   21

◆ NVIC_PRI11_INT47_M

#define NVIC_PRI11_INT47_M   0xE0000000

◆ NVIC_PRI11_INT47_S

#define NVIC_PRI11_INT47_S   29

◆ NVIC_PRI11_R

#define NVIC_PRI11_R   (*((volatile u32 *)0xE000E42C))

◆ NVIC_PRI12_INT48_M

#define NVIC_PRI12_INT48_M   0x000000E0

◆ NVIC_PRI12_INT48_S

#define NVIC_PRI12_INT48_S   5

◆ NVIC_PRI12_INT49_M

#define NVIC_PRI12_INT49_M   0x0000E000

◆ NVIC_PRI12_INT49_S

#define NVIC_PRI12_INT49_S   13

◆ NVIC_PRI12_INT50_M

#define NVIC_PRI12_INT50_M   0x00E00000

◆ NVIC_PRI12_INT50_S

#define NVIC_PRI12_INT50_S   21

◆ NVIC_PRI12_INT51_M

#define NVIC_PRI12_INT51_M   0xE0000000

◆ NVIC_PRI12_INT51_S

#define NVIC_PRI12_INT51_S   29

◆ NVIC_PRI12_R

#define NVIC_PRI12_R   (*((volatile u32 *)0xE000E430))

◆ NVIC_PRI13_INT52_M

#define NVIC_PRI13_INT52_M   0x000000E0

◆ NVIC_PRI13_INT52_S

#define NVIC_PRI13_INT52_S   5

◆ NVIC_PRI13_INT53_M

#define NVIC_PRI13_INT53_M   0x0000E000

◆ NVIC_PRI13_INT53_S

#define NVIC_PRI13_INT53_S   13

◆ NVIC_PRI13_INT54_M

#define NVIC_PRI13_INT54_M   0x00E00000

◆ NVIC_PRI13_INT54_S

#define NVIC_PRI13_INT54_S   21

◆ NVIC_PRI13_INT55_M

#define NVIC_PRI13_INT55_M   0xE0000000

◆ NVIC_PRI13_INT55_S

#define NVIC_PRI13_INT55_S   29

◆ NVIC_PRI13_R

#define NVIC_PRI13_R   (*((volatile u32 *)0xE000E434))

◆ NVIC_PRI14_INTA_M

#define NVIC_PRI14_INTA_M   0x000000E0

◆ NVIC_PRI14_INTA_S

#define NVIC_PRI14_INTA_S   5

◆ NVIC_PRI14_INTB_M

#define NVIC_PRI14_INTB_M   0x0000E000

◆ NVIC_PRI14_INTB_S

#define NVIC_PRI14_INTB_S   13

◆ NVIC_PRI14_INTC_M

#define NVIC_PRI14_INTC_M   0x00E00000

◆ NVIC_PRI14_INTC_S

#define NVIC_PRI14_INTC_S   21

◆ NVIC_PRI14_INTD_M

#define NVIC_PRI14_INTD_M   0xE0000000

◆ NVIC_PRI14_INTD_S

#define NVIC_PRI14_INTD_S   29

◆ NVIC_PRI14_R

#define NVIC_PRI14_R   (*((volatile u32 *)0xE000E438))

◆ NVIC_PRI15_INTA_M

#define NVIC_PRI15_INTA_M   0x000000E0

◆ NVIC_PRI15_INTA_S

#define NVIC_PRI15_INTA_S   5

◆ NVIC_PRI15_INTB_M

#define NVIC_PRI15_INTB_M   0x0000E000

◆ NVIC_PRI15_INTB_S

#define NVIC_PRI15_INTB_S   13

◆ NVIC_PRI15_INTC_M

#define NVIC_PRI15_INTC_M   0x00E00000

◆ NVIC_PRI15_INTC_S

#define NVIC_PRI15_INTC_S   21

◆ NVIC_PRI15_INTD_M

#define NVIC_PRI15_INTD_M   0xE0000000

◆ NVIC_PRI15_INTD_S

#define NVIC_PRI15_INTD_S   29

◆ NVIC_PRI15_R

#define NVIC_PRI15_R   (*((volatile u32 *)0xE000E43C))

◆ NVIC_PRI16_INTA_M

#define NVIC_PRI16_INTA_M   0x000000E0

◆ NVIC_PRI16_INTA_S

#define NVIC_PRI16_INTA_S   5

◆ NVIC_PRI16_INTB_M

#define NVIC_PRI16_INTB_M   0x0000E000

◆ NVIC_PRI16_INTB_S

#define NVIC_PRI16_INTB_S   13

◆ NVIC_PRI16_INTC_M

#define NVIC_PRI16_INTC_M   0x00E00000

◆ NVIC_PRI16_INTC_S

#define NVIC_PRI16_INTC_S   21

◆ NVIC_PRI16_INTD_M

#define NVIC_PRI16_INTD_M   0xE0000000

◆ NVIC_PRI16_INTD_S

#define NVIC_PRI16_INTD_S   29

◆ NVIC_PRI16_R

#define NVIC_PRI16_R   (*((volatile u32 *)0xE000E440))

◆ NVIC_PRI17_INTA_M

#define NVIC_PRI17_INTA_M   0x000000E0

◆ NVIC_PRI17_INTA_S

#define NVIC_PRI17_INTA_S   5

◆ NVIC_PRI17_INTB_M

#define NVIC_PRI17_INTB_M   0x0000E000

◆ NVIC_PRI17_INTB_S

#define NVIC_PRI17_INTB_S   13

◆ NVIC_PRI17_INTC_M

#define NVIC_PRI17_INTC_M   0x00E00000

◆ NVIC_PRI17_INTC_S

#define NVIC_PRI17_INTC_S   21

◆ NVIC_PRI17_INTD_M

#define NVIC_PRI17_INTD_M   0xE0000000

◆ NVIC_PRI17_INTD_S

#define NVIC_PRI17_INTD_S   29

◆ NVIC_PRI17_R

#define NVIC_PRI17_R   (*((volatile u32 *)0xE000E444))

◆ NVIC_PRI18_INTA_M

#define NVIC_PRI18_INTA_M   0x000000E0

◆ NVIC_PRI18_INTA_S

#define NVIC_PRI18_INTA_S   5

◆ NVIC_PRI18_INTB_M

#define NVIC_PRI18_INTB_M   0x0000E000

◆ NVIC_PRI18_INTB_S

#define NVIC_PRI18_INTB_S   13

◆ NVIC_PRI18_INTC_M

#define NVIC_PRI18_INTC_M   0x00E00000

◆ NVIC_PRI18_INTC_S

#define NVIC_PRI18_INTC_S   21

◆ NVIC_PRI18_INTD_M

#define NVIC_PRI18_INTD_M   0xE0000000

◆ NVIC_PRI18_INTD_S

#define NVIC_PRI18_INTD_S   29

◆ NVIC_PRI18_R

#define NVIC_PRI18_R   (*((volatile u32 *)0xE000E448))

◆ NVIC_PRI19_INTA_M

#define NVIC_PRI19_INTA_M   0x000000E0

◆ NVIC_PRI19_INTA_S

#define NVIC_PRI19_INTA_S   5

◆ NVIC_PRI19_INTB_M

#define NVIC_PRI19_INTB_M   0x0000E000

◆ NVIC_PRI19_INTB_S

#define NVIC_PRI19_INTB_S   13

◆ NVIC_PRI19_INTC_M

#define NVIC_PRI19_INTC_M   0x00E00000

◆ NVIC_PRI19_INTC_S

#define NVIC_PRI19_INTC_S   21

◆ NVIC_PRI19_INTD_M

#define NVIC_PRI19_INTD_M   0xE0000000

◆ NVIC_PRI19_INTD_S

#define NVIC_PRI19_INTD_S   29

◆ NVIC_PRI19_R

#define NVIC_PRI19_R   (*((volatile u32 *)0xE000E44C))

◆ NVIC_PRI1_INT4_M

#define NVIC_PRI1_INT4_M   0x000000E0

◆ NVIC_PRI1_INT4_S

#define NVIC_PRI1_INT4_S   5

◆ NVIC_PRI1_INT5_M

#define NVIC_PRI1_INT5_M   0x0000E000

◆ NVIC_PRI1_INT5_S

#define NVIC_PRI1_INT5_S   13

◆ NVIC_PRI1_INT6_M

#define NVIC_PRI1_INT6_M   0x00E00000

◆ NVIC_PRI1_INT6_S

#define NVIC_PRI1_INT6_S   21

◆ NVIC_PRI1_INT7_M

#define NVIC_PRI1_INT7_M   0xE0000000

◆ NVIC_PRI1_INT7_S

#define NVIC_PRI1_INT7_S   29

◆ NVIC_PRI1_R

#define NVIC_PRI1_R   (*((volatile u32 *)0xE000E404))

◆ NVIC_PRI20_INTA_M

#define NVIC_PRI20_INTA_M   0x000000E0

◆ NVIC_PRI20_INTA_S

#define NVIC_PRI20_INTA_S   5

◆ NVIC_PRI20_INTB_M

#define NVIC_PRI20_INTB_M   0x0000E000

◆ NVIC_PRI20_INTB_S

#define NVIC_PRI20_INTB_S   13

◆ NVIC_PRI20_INTC_M

#define NVIC_PRI20_INTC_M   0x00E00000

◆ NVIC_PRI20_INTC_S

#define NVIC_PRI20_INTC_S   21

◆ NVIC_PRI20_INTD_M

#define NVIC_PRI20_INTD_M   0xE0000000

◆ NVIC_PRI20_INTD_S

#define NVIC_PRI20_INTD_S   29

◆ NVIC_PRI20_R

#define NVIC_PRI20_R   (*((volatile u32 *)0xE000E450))

◆ NVIC_PRI21_INTA_M

#define NVIC_PRI21_INTA_M   0x000000E0

◆ NVIC_PRI21_INTA_S

#define NVIC_PRI21_INTA_S   5

◆ NVIC_PRI21_INTB_M

#define NVIC_PRI21_INTB_M   0x0000E000

◆ NVIC_PRI21_INTB_S

#define NVIC_PRI21_INTB_S   13

◆ NVIC_PRI21_INTC_M

#define NVIC_PRI21_INTC_M   0x00E00000

◆ NVIC_PRI21_INTC_S

#define NVIC_PRI21_INTC_S   21

◆ NVIC_PRI21_INTD_M

#define NVIC_PRI21_INTD_M   0xE0000000

◆ NVIC_PRI21_INTD_S

#define NVIC_PRI21_INTD_S   29

◆ NVIC_PRI21_R

#define NVIC_PRI21_R   (*((volatile u32 *)0xE000E454))

◆ NVIC_PRI22_INTA_M

#define NVIC_PRI22_INTA_M   0x000000E0

◆ NVIC_PRI22_INTA_S

#define NVIC_PRI22_INTA_S   5

◆ NVIC_PRI22_INTB_M

#define NVIC_PRI22_INTB_M   0x0000E000

◆ NVIC_PRI22_INTB_S

#define NVIC_PRI22_INTB_S   13

◆ NVIC_PRI22_INTC_M

#define NVIC_PRI22_INTC_M   0x00E00000

◆ NVIC_PRI22_INTC_S

#define NVIC_PRI22_INTC_S   21

◆ NVIC_PRI22_INTD_M

#define NVIC_PRI22_INTD_M   0xE0000000

◆ NVIC_PRI22_INTD_S

#define NVIC_PRI22_INTD_S   29

◆ NVIC_PRI22_R

#define NVIC_PRI22_R   (*((volatile u32 *)0xE000E458))

◆ NVIC_PRI23_INTA_M

#define NVIC_PRI23_INTA_M   0x000000E0

◆ NVIC_PRI23_INTA_S

#define NVIC_PRI23_INTA_S   5

◆ NVIC_PRI23_INTB_M

#define NVIC_PRI23_INTB_M   0x0000E000

◆ NVIC_PRI23_INTB_S

#define NVIC_PRI23_INTB_S   13

◆ NVIC_PRI23_INTC_M

#define NVIC_PRI23_INTC_M   0x00E00000

◆ NVIC_PRI23_INTC_S

#define NVIC_PRI23_INTC_S   21

◆ NVIC_PRI23_INTD_M

#define NVIC_PRI23_INTD_M   0xE0000000

◆ NVIC_PRI23_INTD_S

#define NVIC_PRI23_INTD_S   29

◆ NVIC_PRI23_R

#define NVIC_PRI23_R   (*((volatile u32 *)0xE000E45C))

◆ NVIC_PRI24_INTA_M

#define NVIC_PRI24_INTA_M   0x000000E0

◆ NVIC_PRI24_INTA_S

#define NVIC_PRI24_INTA_S   5

◆ NVIC_PRI24_INTB_M

#define NVIC_PRI24_INTB_M   0x0000E000

◆ NVIC_PRI24_INTB_S

#define NVIC_PRI24_INTB_S   13

◆ NVIC_PRI24_INTC_M

#define NVIC_PRI24_INTC_M   0x00E00000

◆ NVIC_PRI24_INTC_S

#define NVIC_PRI24_INTC_S   21

◆ NVIC_PRI24_INTD_M

#define NVIC_PRI24_INTD_M   0xE0000000

◆ NVIC_PRI24_INTD_S

#define NVIC_PRI24_INTD_S   29

◆ NVIC_PRI24_R

#define NVIC_PRI24_R   (*((volatile u32 *)0xE000E460))

◆ NVIC_PRI25_INTA_M

#define NVIC_PRI25_INTA_M   0x000000E0

◆ NVIC_PRI25_INTA_S

#define NVIC_PRI25_INTA_S   5

◆ NVIC_PRI25_INTB_M

#define NVIC_PRI25_INTB_M   0x0000E000

◆ NVIC_PRI25_INTB_S

#define NVIC_PRI25_INTB_S   13

◆ NVIC_PRI25_INTC_M

#define NVIC_PRI25_INTC_M   0x00E00000

◆ NVIC_PRI25_INTC_S

#define NVIC_PRI25_INTC_S   21

◆ NVIC_PRI25_INTD_M

#define NVIC_PRI25_INTD_M   0xE0000000

◆ NVIC_PRI25_INTD_S

#define NVIC_PRI25_INTD_S   29

◆ NVIC_PRI25_R

#define NVIC_PRI25_R   (*((volatile u32 *)0xE000E464))

◆ NVIC_PRI26_INTA_M

#define NVIC_PRI26_INTA_M   0x000000E0

◆ NVIC_PRI26_INTA_S

#define NVIC_PRI26_INTA_S   5

◆ NVIC_PRI26_INTB_M

#define NVIC_PRI26_INTB_M   0x0000E000

◆ NVIC_PRI26_INTB_S

#define NVIC_PRI26_INTB_S   13

◆ NVIC_PRI26_INTC_M

#define NVIC_PRI26_INTC_M   0x00E00000

◆ NVIC_PRI26_INTC_S

#define NVIC_PRI26_INTC_S   21

◆ NVIC_PRI26_INTD_M

#define NVIC_PRI26_INTD_M   0xE0000000

◆ NVIC_PRI26_INTD_S

#define NVIC_PRI26_INTD_S   29

◆ NVIC_PRI26_R

#define NVIC_PRI26_R   (*((volatile u32 *)0xE000E468))

◆ NVIC_PRI27_INTA_M

#define NVIC_PRI27_INTA_M   0x000000E0

◆ NVIC_PRI27_INTA_S

#define NVIC_PRI27_INTA_S   5

◆ NVIC_PRI27_INTB_M

#define NVIC_PRI27_INTB_M   0x0000E000

◆ NVIC_PRI27_INTB_S

#define NVIC_PRI27_INTB_S   13

◆ NVIC_PRI27_INTC_M

#define NVIC_PRI27_INTC_M   0x00E00000

◆ NVIC_PRI27_INTC_S

#define NVIC_PRI27_INTC_S   21

◆ NVIC_PRI27_INTD_M

#define NVIC_PRI27_INTD_M   0xE0000000

◆ NVIC_PRI27_INTD_S

#define NVIC_PRI27_INTD_S   29

◆ NVIC_PRI27_R

#define NVIC_PRI27_R   (*((volatile u32 *)0xE000E46C))

◆ NVIC_PRI28_INTA_M

#define NVIC_PRI28_INTA_M   0x000000E0

◆ NVIC_PRI28_INTA_S

#define NVIC_PRI28_INTA_S   5

◆ NVIC_PRI28_INTB_M

#define NVIC_PRI28_INTB_M   0x0000E000

◆ NVIC_PRI28_INTB_S

#define NVIC_PRI28_INTB_S   13

◆ NVIC_PRI28_INTC_M

#define NVIC_PRI28_INTC_M   0x00E00000

◆ NVIC_PRI28_INTC_S

#define NVIC_PRI28_INTC_S   21

◆ NVIC_PRI28_INTD_M

#define NVIC_PRI28_INTD_M   0xE0000000

◆ NVIC_PRI28_INTD_S

#define NVIC_PRI28_INTD_S   29

◆ NVIC_PRI28_R

#define NVIC_PRI28_R   (*((volatile u32 *)0xE000E470))

◆ NVIC_PRI29_INTA_M

#define NVIC_PRI29_INTA_M   0x000000E0

◆ NVIC_PRI29_INTA_S

#define NVIC_PRI29_INTA_S   5

◆ NVIC_PRI29_INTB_M

#define NVIC_PRI29_INTB_M   0x0000E000

◆ NVIC_PRI29_INTB_S

#define NVIC_PRI29_INTB_S   13

◆ NVIC_PRI29_INTC_M

#define NVIC_PRI29_INTC_M   0x00E00000

◆ NVIC_PRI29_INTC_S

#define NVIC_PRI29_INTC_S   21

◆ NVIC_PRI29_INTD_M

#define NVIC_PRI29_INTD_M   0xE0000000

◆ NVIC_PRI29_INTD_S

#define NVIC_PRI29_INTD_S   29

◆ NVIC_PRI29_R

#define NVIC_PRI29_R   (*((volatile u32 *)0xE000E474))

◆ NVIC_PRI2_INT10_M

#define NVIC_PRI2_INT10_M   0x00E00000

◆ NVIC_PRI2_INT10_S

#define NVIC_PRI2_INT10_S   21

◆ NVIC_PRI2_INT11_M

#define NVIC_PRI2_INT11_M   0xE0000000

◆ NVIC_PRI2_INT11_S

#define NVIC_PRI2_INT11_S   29

◆ NVIC_PRI2_INT8_M

#define NVIC_PRI2_INT8_M   0x000000E0

◆ NVIC_PRI2_INT8_S

#define NVIC_PRI2_INT8_S   5

◆ NVIC_PRI2_INT9_M

#define NVIC_PRI2_INT9_M   0x0000E000

◆ NVIC_PRI2_INT9_S

#define NVIC_PRI2_INT9_S   13

◆ NVIC_PRI2_R

#define NVIC_PRI2_R   (*((volatile u32 *)0xE000E408))

◆ NVIC_PRI30_INTA_M

#define NVIC_PRI30_INTA_M   0x000000E0

◆ NVIC_PRI30_INTA_S

#define NVIC_PRI30_INTA_S   5

◆ NVIC_PRI30_INTB_M

#define NVIC_PRI30_INTB_M   0x0000E000

◆ NVIC_PRI30_INTB_S

#define NVIC_PRI30_INTB_S   13

◆ NVIC_PRI30_INTC_M

#define NVIC_PRI30_INTC_M   0x00E00000

◆ NVIC_PRI30_INTC_S

#define NVIC_PRI30_INTC_S   21

◆ NVIC_PRI30_INTD_M

#define NVIC_PRI30_INTD_M   0xE0000000

◆ NVIC_PRI30_INTD_S

#define NVIC_PRI30_INTD_S   29

◆ NVIC_PRI30_R

#define NVIC_PRI30_R   (*((volatile u32 *)0xE000E478))

◆ NVIC_PRI31_INTA_M

#define NVIC_PRI31_INTA_M   0x000000E0

◆ NVIC_PRI31_INTA_S

#define NVIC_PRI31_INTA_S   5

◆ NVIC_PRI31_INTB_M

#define NVIC_PRI31_INTB_M   0x0000E000

◆ NVIC_PRI31_INTB_S

#define NVIC_PRI31_INTB_S   13

◆ NVIC_PRI31_INTC_M

#define NVIC_PRI31_INTC_M   0x00E00000

◆ NVIC_PRI31_INTC_S

#define NVIC_PRI31_INTC_S   21

◆ NVIC_PRI31_INTD_M

#define NVIC_PRI31_INTD_M   0xE0000000

◆ NVIC_PRI31_INTD_S

#define NVIC_PRI31_INTD_S   29

◆ NVIC_PRI31_R

#define NVIC_PRI31_R   (*((volatile u32 *)0xE000E47C))

◆ NVIC_PRI32_INTA_M

#define NVIC_PRI32_INTA_M   0x000000E0

◆ NVIC_PRI32_INTA_S

#define NVIC_PRI32_INTA_S   5

◆ NVIC_PRI32_INTB_M

#define NVIC_PRI32_INTB_M   0x0000E000

◆ NVIC_PRI32_INTB_S

#define NVIC_PRI32_INTB_S   13

◆ NVIC_PRI32_INTC_M

#define NVIC_PRI32_INTC_M   0x00E00000

◆ NVIC_PRI32_INTC_S

#define NVIC_PRI32_INTC_S   21

◆ NVIC_PRI32_INTD_M

#define NVIC_PRI32_INTD_M   0xE0000000

◆ NVIC_PRI32_INTD_S

#define NVIC_PRI32_INTD_S   29

◆ NVIC_PRI32_R

#define NVIC_PRI32_R   (*((volatile u32 *)0xE000E480))

◆ NVIC_PRI33_INTA_M

#define NVIC_PRI33_INTA_M   0x000000E0

◆ NVIC_PRI33_INTA_S

#define NVIC_PRI33_INTA_S   5

◆ NVIC_PRI33_INTB_M

#define NVIC_PRI33_INTB_M   0x0000E000

◆ NVIC_PRI33_INTB_S

#define NVIC_PRI33_INTB_S   13

◆ NVIC_PRI33_INTC_M

#define NVIC_PRI33_INTC_M   0x00E00000

◆ NVIC_PRI33_INTC_S

#define NVIC_PRI33_INTC_S   21

◆ NVIC_PRI33_INTD_M

#define NVIC_PRI33_INTD_M   0xE0000000

◆ NVIC_PRI33_INTD_S

#define NVIC_PRI33_INTD_S   29

◆ NVIC_PRI33_R

#define NVIC_PRI33_R   (*((volatile u32 *)0xE000E484))

◆ NVIC_PRI34_INTA_M

#define NVIC_PRI34_INTA_M   0x000000E0

◆ NVIC_PRI34_INTA_S

#define NVIC_PRI34_INTA_S   5

◆ NVIC_PRI34_INTB_M

#define NVIC_PRI34_INTB_M   0x0000E000

◆ NVIC_PRI34_INTB_S

#define NVIC_PRI34_INTB_S   13

◆ NVIC_PRI34_INTC_M

#define NVIC_PRI34_INTC_M   0x00E00000

◆ NVIC_PRI34_INTC_S

#define NVIC_PRI34_INTC_S   21

◆ NVIC_PRI34_INTD_M

#define NVIC_PRI34_INTD_M   0xE0000000

◆ NVIC_PRI34_INTD_S

#define NVIC_PRI34_INTD_S   29

◆ NVIC_PRI34_R

#define NVIC_PRI34_R   (*((volatile u32 *)0xE000E488))

◆ NVIC_PRI3_INT12_M

#define NVIC_PRI3_INT12_M   0x000000E0

◆ NVIC_PRI3_INT12_S

#define NVIC_PRI3_INT12_S   5

◆ NVIC_PRI3_INT13_M

#define NVIC_PRI3_INT13_M   0x0000E000

◆ NVIC_PRI3_INT13_S

#define NVIC_PRI3_INT13_S   13

◆ NVIC_PRI3_INT14_M

#define NVIC_PRI3_INT14_M   0x00E00000

◆ NVIC_PRI3_INT14_S

#define NVIC_PRI3_INT14_S   21

◆ NVIC_PRI3_INT15_M

#define NVIC_PRI3_INT15_M   0xE0000000

◆ NVIC_PRI3_INT15_S

#define NVIC_PRI3_INT15_S   29

◆ NVIC_PRI3_R

#define NVIC_PRI3_R   (*((volatile u32 *)0xE000E40C))

◆ NVIC_PRI4_INT16_M

#define NVIC_PRI4_INT16_M   0x000000E0

◆ NVIC_PRI4_INT16_S

#define NVIC_PRI4_INT16_S   5

◆ NVIC_PRI4_INT17_M

#define NVIC_PRI4_INT17_M   0x0000E000

◆ NVIC_PRI4_INT17_S

#define NVIC_PRI4_INT17_S   13

◆ NVIC_PRI4_INT18_M

#define NVIC_PRI4_INT18_M   0x00E00000

◆ NVIC_PRI4_INT18_S

#define NVIC_PRI4_INT18_S   21

◆ NVIC_PRI4_INT19_M

#define NVIC_PRI4_INT19_M   0xE0000000

◆ NVIC_PRI4_INT19_S

#define NVIC_PRI4_INT19_S   29

◆ NVIC_PRI4_R

#define NVIC_PRI4_R   (*((volatile u32 *)0xE000E410))

◆ NVIC_PRI5_INT20_M

#define NVIC_PRI5_INT20_M   0x000000E0

◆ NVIC_PRI5_INT20_S

#define NVIC_PRI5_INT20_S   5

◆ NVIC_PRI5_INT21_M

#define NVIC_PRI5_INT21_M   0x0000E000

◆ NVIC_PRI5_INT21_S

#define NVIC_PRI5_INT21_S   13

◆ NVIC_PRI5_INT22_M

#define NVIC_PRI5_INT22_M   0x00E00000

◆ NVIC_PRI5_INT22_S

#define NVIC_PRI5_INT22_S   21

◆ NVIC_PRI5_INT23_M

#define NVIC_PRI5_INT23_M   0xE0000000

◆ NVIC_PRI5_INT23_S

#define NVIC_PRI5_INT23_S   29

◆ NVIC_PRI5_R

#define NVIC_PRI5_R   (*((volatile u32 *)0xE000E414))

◆ NVIC_PRI6_INT24_M

#define NVIC_PRI6_INT24_M   0x000000E0

◆ NVIC_PRI6_INT24_S

#define NVIC_PRI6_INT24_S   5

◆ NVIC_PRI6_INT25_M

#define NVIC_PRI6_INT25_M   0x0000E000

◆ NVIC_PRI6_INT25_S

#define NVIC_PRI6_INT25_S   13

◆ NVIC_PRI6_INT26_M

#define NVIC_PRI6_INT26_M   0x00E00000

◆ NVIC_PRI6_INT26_S

#define NVIC_PRI6_INT26_S   21

◆ NVIC_PRI6_INT27_M

#define NVIC_PRI6_INT27_M   0xE0000000

◆ NVIC_PRI6_INT27_S

#define NVIC_PRI6_INT27_S   29

◆ NVIC_PRI6_R

#define NVIC_PRI6_R   (*((volatile u32 *)0xE000E418))

◆ NVIC_PRI7_INT28_M

#define NVIC_PRI7_INT28_M   0x000000E0

◆ NVIC_PRI7_INT28_S

#define NVIC_PRI7_INT28_S   5

◆ NVIC_PRI7_INT29_M

#define NVIC_PRI7_INT29_M   0x0000E000

◆ NVIC_PRI7_INT29_S

#define NVIC_PRI7_INT29_S   13

◆ NVIC_PRI7_INT30_M

#define NVIC_PRI7_INT30_M   0x00E00000

◆ NVIC_PRI7_INT30_S

#define NVIC_PRI7_INT30_S   21

◆ NVIC_PRI7_INT31_M

#define NVIC_PRI7_INT31_M   0xE0000000

◆ NVIC_PRI7_INT31_S

#define NVIC_PRI7_INT31_S   29

◆ NVIC_PRI7_R

#define NVIC_PRI7_R   (*((volatile u32 *)0xE000E41C))

◆ NVIC_PRI8_INT32_M

#define NVIC_PRI8_INT32_M   0x000000E0

◆ NVIC_PRI8_INT32_S

#define NVIC_PRI8_INT32_S   5

◆ NVIC_PRI8_INT33_M

#define NVIC_PRI8_INT33_M   0x0000E000

◆ NVIC_PRI8_INT33_S

#define NVIC_PRI8_INT33_S   13

◆ NVIC_PRI8_INT34_M

#define NVIC_PRI8_INT34_M   0x00E00000

◆ NVIC_PRI8_INT34_S

#define NVIC_PRI8_INT34_S   21

◆ NVIC_PRI8_INT35_M

#define NVIC_PRI8_INT35_M   0xE0000000

◆ NVIC_PRI8_INT35_S

#define NVIC_PRI8_INT35_S   29

◆ NVIC_PRI8_R

#define NVIC_PRI8_R   (*((volatile u32 *)0xE000E420))

◆ NVIC_PRI9_INT36_M

#define NVIC_PRI9_INT36_M   0x000000E0

◆ NVIC_PRI9_INT36_S

#define NVIC_PRI9_INT36_S   5

◆ NVIC_PRI9_INT37_M

#define NVIC_PRI9_INT37_M   0x0000E000

◆ NVIC_PRI9_INT37_S

#define NVIC_PRI9_INT37_S   13

◆ NVIC_PRI9_INT38_M

#define NVIC_PRI9_INT38_M   0x00E00000

◆ NVIC_PRI9_INT38_S

#define NVIC_PRI9_INT38_S   21

◆ NVIC_PRI9_INT39_M

#define NVIC_PRI9_INT39_M   0xE0000000

◆ NVIC_PRI9_INT39_S

#define NVIC_PRI9_INT39_S   29

◆ NVIC_PRI9_R

#define NVIC_PRI9_R   (*((volatile u32 *)0xE000E424))

◆ NVIC_ST_CTRL_CLK_SRC

#define NVIC_ST_CTRL_CLK_SRC   0x00000004

◆ NVIC_ST_CTRL_COUNT

#define NVIC_ST_CTRL_COUNT   0x00010000

◆ NVIC_ST_CTRL_ENABLE

#define NVIC_ST_CTRL_ENABLE   0x00000001

◆ NVIC_ST_CTRL_INTEN

#define NVIC_ST_CTRL_INTEN   0x00000002

◆ NVIC_ST_CTRL_R

#define NVIC_ST_CTRL_R   (*((volatile u32 *)0xE000E010))

◆ NVIC_ST_CURRENT_M

#define NVIC_ST_CURRENT_M   0x00FFFFFF

◆ NVIC_ST_CURRENT_R

#define NVIC_ST_CURRENT_R   (*((volatile u32 *)0xE000E018))

◆ NVIC_ST_CURRENT_S

#define NVIC_ST_CURRENT_S   0

◆ NVIC_ST_RELOAD_M

#define NVIC_ST_RELOAD_M   0x00FFFFFF

◆ NVIC_ST_RELOAD_R

#define NVIC_ST_RELOAD_R   (*((volatile u32 *)0xE000E014))

◆ NVIC_ST_RELOAD_S

#define NVIC_ST_RELOAD_S   0

◆ NVIC_SW_TRIG_INTID_M

#define NVIC_SW_TRIG_INTID_M   0x000000FF

◆ NVIC_SW_TRIG_INTID_S

#define NVIC_SW_TRIG_INTID_S   0

◆ NVIC_SW_TRIG_R

#define NVIC_SW_TRIG_R   (*((volatile u32 *)0xE000EF00))

◆ NVIC_SYS_CTRL_R

#define NVIC_SYS_CTRL_R   (*((volatile u32 *)0xE000ED10))

◆ NVIC_SYS_CTRL_SEVONPEND

#define NVIC_SYS_CTRL_SEVONPEND   0x00000010

◆ NVIC_SYS_CTRL_SLEEPDEEP

#define NVIC_SYS_CTRL_SLEEPDEEP   0x00000004

◆ NVIC_SYS_CTRL_SLEEPEXIT

#define NVIC_SYS_CTRL_SLEEPEXIT   0x00000002

◆ NVIC_SYS_HND_CTRL_BUS

#define NVIC_SYS_HND_CTRL_BUS   0x00020000

◆ NVIC_SYS_HND_CTRL_BUSA

#define NVIC_SYS_HND_CTRL_BUSA   0x00000002

◆ NVIC_SYS_HND_CTRL_BUSP

#define NVIC_SYS_HND_CTRL_BUSP   0x00004000

◆ NVIC_SYS_HND_CTRL_MEM

#define NVIC_SYS_HND_CTRL_MEM   0x00010000

◆ NVIC_SYS_HND_CTRL_MEMA

#define NVIC_SYS_HND_CTRL_MEMA   0x00000001

◆ NVIC_SYS_HND_CTRL_MEMP

#define NVIC_SYS_HND_CTRL_MEMP   0x00002000

◆ NVIC_SYS_HND_CTRL_MON

#define NVIC_SYS_HND_CTRL_MON   0x00000100

◆ NVIC_SYS_HND_CTRL_PNDSV

#define NVIC_SYS_HND_CTRL_PNDSV   0x00000400

◆ NVIC_SYS_HND_CTRL_R

#define NVIC_SYS_HND_CTRL_R   (*((volatile u32 *)0xE000ED24))

◆ NVIC_SYS_HND_CTRL_SVC

#define NVIC_SYS_HND_CTRL_SVC   0x00008000

◆ NVIC_SYS_HND_CTRL_SVCA

#define NVIC_SYS_HND_CTRL_SVCA   0x00000080

◆ NVIC_SYS_HND_CTRL_TICK

#define NVIC_SYS_HND_CTRL_TICK   0x00000800

◆ NVIC_SYS_HND_CTRL_USAGE

#define NVIC_SYS_HND_CTRL_USAGE   0x00040000

◆ NVIC_SYS_HND_CTRL_USAGEP

#define NVIC_SYS_HND_CTRL_USAGEP    0x00001000

◆ NVIC_SYS_HND_CTRL_USGA

#define NVIC_SYS_HND_CTRL_USGA   0x00000008

◆ NVIC_SYS_PRI1_BUS_M

#define NVIC_SYS_PRI1_BUS_M   0x0000E000

◆ NVIC_SYS_PRI1_BUS_S

#define NVIC_SYS_PRI1_BUS_S   13

◆ NVIC_SYS_PRI1_MEM_M

#define NVIC_SYS_PRI1_MEM_M   0x000000E0

◆ NVIC_SYS_PRI1_MEM_S

#define NVIC_SYS_PRI1_MEM_S   5

◆ NVIC_SYS_PRI1_R

#define NVIC_SYS_PRI1_R   (*((volatile u32 *)0xE000ED18))

◆ NVIC_SYS_PRI1_USAGE_M

#define NVIC_SYS_PRI1_USAGE_M   0x00E00000

◆ NVIC_SYS_PRI1_USAGE_S

#define NVIC_SYS_PRI1_USAGE_S   21

◆ NVIC_SYS_PRI2_R

#define NVIC_SYS_PRI2_R   (*((volatile u32 *)0xE000ED1C))

◆ NVIC_SYS_PRI2_SVC_M

#define NVIC_SYS_PRI2_SVC_M   0xE0000000

◆ NVIC_SYS_PRI2_SVC_S

#define NVIC_SYS_PRI2_SVC_S   29

◆ NVIC_SYS_PRI3_DEBUG_M

#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0

◆ NVIC_SYS_PRI3_DEBUG_S

#define NVIC_SYS_PRI3_DEBUG_S   5

◆ NVIC_SYS_PRI3_PENDSV_M

#define NVIC_SYS_PRI3_PENDSV_M   0x00E00000

◆ NVIC_SYS_PRI3_PENDSV_S

#define NVIC_SYS_PRI3_PENDSV_S   21

◆ NVIC_SYS_PRI3_R

#define NVIC_SYS_PRI3_R   (*((volatile u32 *)0xE000ED20))

◆ NVIC_SYS_PRI3_TICK_M

#define NVIC_SYS_PRI3_TICK_M   0xE0000000

◆ NVIC_SYS_PRI3_TICK_S

#define NVIC_SYS_PRI3_TICK_S   29

◆ NVIC_UNPEND0_INT_M

#define NVIC_UNPEND0_INT_M   0xFFFFFFFF

◆ NVIC_UNPEND0_R

#define NVIC_UNPEND0_R   (*((volatile u32 *)0xE000E280))

◆ NVIC_UNPEND1_INT_M

#define NVIC_UNPEND1_INT_M   0xFFFFFFFF

◆ NVIC_UNPEND1_R

#define NVIC_UNPEND1_R   (*((volatile u32 *)0xE000E284))

◆ NVIC_UNPEND2_INT_M

#define NVIC_UNPEND2_INT_M   0xFFFFFFFF

◆ NVIC_UNPEND2_R

#define NVIC_UNPEND2_R   (*((volatile u32 *)0xE000E288))

◆ NVIC_UNPEND3_INT_M

#define NVIC_UNPEND3_INT_M   0xFFFFFFFF

◆ NVIC_UNPEND3_R

#define NVIC_UNPEND3_R   (*((volatile u32 *)0xE000E28C))

◆ NVIC_UNPEND4_INT_M

#define NVIC_UNPEND4_INT_M   0x000007FF

◆ NVIC_UNPEND4_R

#define NVIC_UNPEND4_R   (*((volatile u32 *)0xE000E290))

◆ NVIC_VTABLE_OFFSET_M

#define NVIC_VTABLE_OFFSET_M   0xFFFFFC00

◆ NVIC_VTABLE_OFFSET_S

#define NVIC_VTABLE_OFFSET_S   10

◆ NVIC_VTABLE_R

#define NVIC_VTABLE_R   (*((volatile u32 *)0xE000ED08))

◆ PWM0_0_CMPA_R

#define PWM0_0_CMPA_R   (*((volatile u32 *)0x40028058))

◆ PWM0_0_CMPB_R

#define PWM0_0_CMPB_R   (*((volatile u32 *)0x4002805C))

◆ PWM0_0_COUNT_R

#define PWM0_0_COUNT_R   (*((volatile u32 *)0x40028054))

◆ PWM0_0_CTL_R

#define PWM0_0_CTL_R   (*((volatile u32 *)0x40028040))

◆ PWM0_0_DBCTL_R

#define PWM0_0_DBCTL_R   (*((volatile u32 *)0x40028068))

◆ PWM0_0_DBFALL_R

#define PWM0_0_DBFALL_R   (*((volatile u32 *)0x40028070))

◆ PWM0_0_DBRISE_R

#define PWM0_0_DBRISE_R   (*((volatile u32 *)0x4002806C))

◆ PWM0_0_FLTSEN_R

#define PWM0_0_FLTSEN_R   (*((volatile u32 *)0x40028800))

◆ PWM0_0_FLTSRC0_R

#define PWM0_0_FLTSRC0_R   (*((volatile u32 *)0x40028074))

◆ PWM0_0_FLTSRC1_R

#define PWM0_0_FLTSRC1_R   (*((volatile u32 *)0x40028078))

◆ PWM0_0_FLTSTAT0_R

#define PWM0_0_FLTSTAT0_R   (*((volatile u32 *)0x40028804))

◆ PWM0_0_FLTSTAT1_R

#define PWM0_0_FLTSTAT1_R   (*((volatile u32 *)0x40028808))

◆ PWM0_0_GENA_R

#define PWM0_0_GENA_R   (*((volatile u32 *)0x40028060))

◆ PWM0_0_GENB_R

#define PWM0_0_GENB_R   (*((volatile u32 *)0x40028064))

◆ PWM0_0_INTEN_R

#define PWM0_0_INTEN_R   (*((volatile u32 *)0x40028044))

◆ PWM0_0_ISC_R

#define PWM0_0_ISC_R   (*((volatile u32 *)0x4002804C))

◆ PWM0_0_LOAD_R

#define PWM0_0_LOAD_R   (*((volatile u32 *)0x40028050))

◆ PWM0_0_MINFLTPER_R

#define PWM0_0_MINFLTPER_R   (*((volatile u32 *)0x4002807C))

◆ PWM0_0_RIS_R

#define PWM0_0_RIS_R   (*((volatile u32 *)0x40028048))

◆ PWM0_1_CMPA_R

#define PWM0_1_CMPA_R   (*((volatile u32 *)0x40028098))

◆ PWM0_1_CMPB_R

#define PWM0_1_CMPB_R   (*((volatile u32 *)0x4002809C))

◆ PWM0_1_COUNT_R

#define PWM0_1_COUNT_R   (*((volatile u32 *)0x40028094))

◆ PWM0_1_CTL_R

#define PWM0_1_CTL_R   (*((volatile u32 *)0x40028080))

◆ PWM0_1_DBCTL_R

#define PWM0_1_DBCTL_R   (*((volatile u32 *)0x400280A8))

◆ PWM0_1_DBFALL_R

#define PWM0_1_DBFALL_R   (*((volatile u32 *)0x400280B0))

◆ PWM0_1_DBRISE_R

#define PWM0_1_DBRISE_R   (*((volatile u32 *)0x400280AC))

◆ PWM0_1_FLTSEN_R

#define PWM0_1_FLTSEN_R   (*((volatile u32 *)0x40028880))

◆ PWM0_1_FLTSRC0_R

#define PWM0_1_FLTSRC0_R   (*((volatile u32 *)0x400280B4))

◆ PWM0_1_FLTSRC1_R

#define PWM0_1_FLTSRC1_R   (*((volatile u32 *)0x400280B8))

◆ PWM0_1_FLTSTAT0_R

#define PWM0_1_FLTSTAT0_R   (*((volatile u32 *)0x40028884))

◆ PWM0_1_FLTSTAT1_R

#define PWM0_1_FLTSTAT1_R   (*((volatile u32 *)0x40028888))

◆ PWM0_1_GENA_R

#define PWM0_1_GENA_R   (*((volatile u32 *)0x400280A0))

◆ PWM0_1_GENB_R

#define PWM0_1_GENB_R   (*((volatile u32 *)0x400280A4))

◆ PWM0_1_INTEN_R

#define PWM0_1_INTEN_R   (*((volatile u32 *)0x40028084))

◆ PWM0_1_ISC_R

#define PWM0_1_ISC_R   (*((volatile u32 *)0x4002808C))

◆ PWM0_1_LOAD_R

#define PWM0_1_LOAD_R   (*((volatile u32 *)0x40028090))

◆ PWM0_1_MINFLTPER_R

#define PWM0_1_MINFLTPER_R   (*((volatile u32 *)0x400280BC))

◆ PWM0_1_RIS_R

#define PWM0_1_RIS_R   (*((volatile u32 *)0x40028088))

◆ PWM0_2_CMPA_R

#define PWM0_2_CMPA_R   (*((volatile u32 *)0x400280D8))

◆ PWM0_2_CMPB_R

#define PWM0_2_CMPB_R   (*((volatile u32 *)0x400280DC))

◆ PWM0_2_COUNT_R

#define PWM0_2_COUNT_R   (*((volatile u32 *)0x400280D4))

◆ PWM0_2_CTL_R

#define PWM0_2_CTL_R   (*((volatile u32 *)0x400280C0))

◆ PWM0_2_DBCTL_R

#define PWM0_2_DBCTL_R   (*((volatile u32 *)0x400280E8))

◆ PWM0_2_DBFALL_R

#define PWM0_2_DBFALL_R   (*((volatile u32 *)0x400280F0))

◆ PWM0_2_DBRISE_R

#define PWM0_2_DBRISE_R   (*((volatile u32 *)0x400280EC))

◆ PWM0_2_FLTSRC0_R

#define PWM0_2_FLTSRC0_R   (*((volatile u32 *)0x400280F4))

◆ PWM0_2_FLTSRC1_R

#define PWM0_2_FLTSRC1_R   (*((volatile u32 *)0x400280F8))

◆ PWM0_2_FLTSTAT0_R

#define PWM0_2_FLTSTAT0_R   (*((volatile u32 *)0x40028904))

◆ PWM0_2_FLTSTAT1_R

#define PWM0_2_FLTSTAT1_R   (*((volatile u32 *)0x40028908))

◆ PWM0_2_GENA_R

#define PWM0_2_GENA_R   (*((volatile u32 *)0x400280E0))

◆ PWM0_2_GENB_R

#define PWM0_2_GENB_R   (*((volatile u32 *)0x400280E4))

◆ PWM0_2_INTEN_R

#define PWM0_2_INTEN_R   (*((volatile u32 *)0x400280C4))

◆ PWM0_2_ISC_R

#define PWM0_2_ISC_R   (*((volatile u32 *)0x400280CC))

◆ PWM0_2_LOAD_R

#define PWM0_2_LOAD_R   (*((volatile u32 *)0x400280D0))

◆ PWM0_2_MINFLTPER_R

#define PWM0_2_MINFLTPER_R   (*((volatile u32 *)0x400280FC))

◆ PWM0_2_RIS_R

#define PWM0_2_RIS_R   (*((volatile u32 *)0x400280C8))

◆ PWM0_3_CMPA_R

#define PWM0_3_CMPA_R   (*((volatile u32 *)0x40028118))

◆ PWM0_3_CMPB_R

#define PWM0_3_CMPB_R   (*((volatile u32 *)0x4002811C))

◆ PWM0_3_COUNT_R

#define PWM0_3_COUNT_R   (*((volatile u32 *)0x40028114))

◆ PWM0_3_CTL_R

#define PWM0_3_CTL_R   (*((volatile u32 *)0x40028100))

◆ PWM0_3_DBCTL_R

#define PWM0_3_DBCTL_R   (*((volatile u32 *)0x40028128))

◆ PWM0_3_DBFALL_R

#define PWM0_3_DBFALL_R   (*((volatile u32 *)0x40028130))

◆ PWM0_3_DBRISE_R

#define PWM0_3_DBRISE_R   (*((volatile u32 *)0x4002812C))

◆ PWM0_3_FLTSRC0_R

#define PWM0_3_FLTSRC0_R   (*((volatile u32 *)0x40028134))

◆ PWM0_3_FLTSRC1_R

#define PWM0_3_FLTSRC1_R   (*((volatile u32 *)0x40028138))

◆ PWM0_3_FLTSTAT0_R

#define PWM0_3_FLTSTAT0_R   (*((volatile u32 *)0x40028984))

◆ PWM0_3_FLTSTAT1_R

#define PWM0_3_FLTSTAT1_R   (*((volatile u32 *)0x40028988))

◆ PWM0_3_GENA_R

#define PWM0_3_GENA_R   (*((volatile u32 *)0x40028120))

◆ PWM0_3_GENB_R

#define PWM0_3_GENB_R   (*((volatile u32 *)0x40028124))

◆ PWM0_3_INTEN_R

#define PWM0_3_INTEN_R   (*((volatile u32 *)0x40028104))

◆ PWM0_3_ISC_R

#define PWM0_3_ISC_R   (*((volatile u32 *)0x4002810C))

◆ PWM0_3_LOAD_R

#define PWM0_3_LOAD_R   (*((volatile u32 *)0x40028110))

◆ PWM0_3_MINFLTPER_R

#define PWM0_3_MINFLTPER_R   (*((volatile u32 *)0x4002813C))

◆ PWM0_3_RIS_R

#define PWM0_3_RIS_R   (*((volatile u32 *)0x40028108))

◆ PWM0_CTL_R

#define PWM0_CTL_R   (*((volatile u32 *)0x40028000))

◆ PWM0_ENABLE_R

#define PWM0_ENABLE_R   (*((volatile u32 *)0x40028008))

◆ PWM0_ENUPD_R

#define PWM0_ENUPD_R   (*((volatile u32 *)0x40028028))

◆ PWM0_FAULT_R

#define PWM0_FAULT_R   (*((volatile u32 *)0x40028010))

◆ PWM0_FAULTVAL_R

#define PWM0_FAULTVAL_R   (*((volatile u32 *)0x40028024))

◆ PWM0_INTEN_R

#define PWM0_INTEN_R   (*((volatile u32 *)0x40028014))

◆ PWM0_INVERT_R

#define PWM0_INVERT_R   (*((volatile u32 *)0x4002800C))

◆ PWM0_ISC_R

#define PWM0_ISC_R   (*((volatile u32 *)0x4002801C))

◆ PWM0_PP_R

#define PWM0_PP_R   (*((volatile u32 *)0x40028FC0))

◆ PWM0_RIS_R

#define PWM0_RIS_R   (*((volatile u32 *)0x40028018))

◆ PWM0_STATUS_R

#define PWM0_STATUS_R   (*((volatile u32 *)0x40028020))

◆ PWM0_SYNC_R

#define PWM0_SYNC_R   (*((volatile u32 *)0x40028004))

◆ PWM1_0_CMPA_R

#define PWM1_0_CMPA_R   (*((volatile u32 *)0x40029058))

◆ PWM1_0_CMPB_R

#define PWM1_0_CMPB_R   (*((volatile u32 *)0x4002905C))

◆ PWM1_0_COUNT_R

#define PWM1_0_COUNT_R   (*((volatile u32 *)0x40029054))

◆ PWM1_0_CTL_R

#define PWM1_0_CTL_R   (*((volatile u32 *)0x40029040))

◆ PWM1_0_DBCTL_R

#define PWM1_0_DBCTL_R   (*((volatile u32 *)0x40029068))

◆ PWM1_0_DBFALL_R

#define PWM1_0_DBFALL_R   (*((volatile u32 *)0x40029070))

◆ PWM1_0_DBRISE_R

#define PWM1_0_DBRISE_R   (*((volatile u32 *)0x4002906C))

◆ PWM1_0_FLTSEN_R

#define PWM1_0_FLTSEN_R   (*((volatile u32 *)0x40029800))

◆ PWM1_0_FLTSRC0_R

#define PWM1_0_FLTSRC0_R   (*((volatile u32 *)0x40029074))

◆ PWM1_0_FLTSRC1_R

#define PWM1_0_FLTSRC1_R   (*((volatile u32 *)0x40029078))

◆ PWM1_0_FLTSTAT0_R

#define PWM1_0_FLTSTAT0_R   (*((volatile u32 *)0x40029804))

◆ PWM1_0_FLTSTAT1_R

#define PWM1_0_FLTSTAT1_R   (*((volatile u32 *)0x40029808))

◆ PWM1_0_GENA_R

#define PWM1_0_GENA_R   (*((volatile u32 *)0x40029060))

◆ PWM1_0_GENB_R

#define PWM1_0_GENB_R   (*((volatile u32 *)0x40029064))

◆ PWM1_0_INTEN_R

#define PWM1_0_INTEN_R   (*((volatile u32 *)0x40029044))

◆ PWM1_0_ISC_R

#define PWM1_0_ISC_R   (*((volatile u32 *)0x4002904C))

◆ PWM1_0_LOAD_R

#define PWM1_0_LOAD_R   (*((volatile u32 *)0x40029050))

◆ PWM1_0_MINFLTPER_R

#define PWM1_0_MINFLTPER_R   (*((volatile u32 *)0x4002907C))

◆ PWM1_0_RIS_R

#define PWM1_0_RIS_R   (*((volatile u32 *)0x40029048))

◆ PWM1_1_CMPA_R

#define PWM1_1_CMPA_R   (*((volatile u32 *)0x40029098))

◆ PWM1_1_CMPB_R

#define PWM1_1_CMPB_R   (*((volatile u32 *)0x4002909C))

◆ PWM1_1_COUNT_R

#define PWM1_1_COUNT_R   (*((volatile u32 *)0x40029094))

◆ PWM1_1_CTL_R

#define PWM1_1_CTL_R   (*((volatile u32 *)0x40029080))

◆ PWM1_1_DBCTL_R

#define PWM1_1_DBCTL_R   (*((volatile u32 *)0x400290A8))

◆ PWM1_1_DBFALL_R

#define PWM1_1_DBFALL_R   (*((volatile u32 *)0x400290B0))

◆ PWM1_1_DBRISE_R

#define PWM1_1_DBRISE_R   (*((volatile u32 *)0x400290AC))

◆ PWM1_1_FLTSEN_R

#define PWM1_1_FLTSEN_R   (*((volatile u32 *)0x40029880))

◆ PWM1_1_FLTSRC0_R

#define PWM1_1_FLTSRC0_R   (*((volatile u32 *)0x400290B4))

◆ PWM1_1_FLTSRC1_R

#define PWM1_1_FLTSRC1_R   (*((volatile u32 *)0x400290B8))

◆ PWM1_1_FLTSTAT0_R

#define PWM1_1_FLTSTAT0_R   (*((volatile u32 *)0x40029884))

◆ PWM1_1_FLTSTAT1_R

#define PWM1_1_FLTSTAT1_R   (*((volatile u32 *)0x40029888))

◆ PWM1_1_GENA_R

#define PWM1_1_GENA_R   (*((volatile u32 *)0x400290A0))

◆ PWM1_1_GENB_R

#define PWM1_1_GENB_R   (*((volatile u32 *)0x400290A4))

◆ PWM1_1_INTEN_R

#define PWM1_1_INTEN_R   (*((volatile u32 *)0x40029084))

◆ PWM1_1_ISC_R

#define PWM1_1_ISC_R   (*((volatile u32 *)0x4002908C))

◆ PWM1_1_LOAD_R

#define PWM1_1_LOAD_R   (*((volatile u32 *)0x40029090))

◆ PWM1_1_MINFLTPER_R

#define PWM1_1_MINFLTPER_R   (*((volatile u32 *)0x400290BC))

◆ PWM1_1_RIS_R

#define PWM1_1_RIS_R   (*((volatile u32 *)0x40029088))

◆ PWM1_2_CMPA_R

#define PWM1_2_CMPA_R   (*((volatile u32 *)0x400290D8))

◆ PWM1_2_CMPB_R

#define PWM1_2_CMPB_R   (*((volatile u32 *)0x400290DC))

◆ PWM1_2_COUNT_R

#define PWM1_2_COUNT_R   (*((volatile u32 *)0x400290D4))

◆ PWM1_2_CTL_R

#define PWM1_2_CTL_R   (*((volatile u32 *)0x400290C0))

◆ PWM1_2_DBCTL_R

#define PWM1_2_DBCTL_R   (*((volatile u32 *)0x400290E8))

◆ PWM1_2_DBFALL_R

#define PWM1_2_DBFALL_R   (*((volatile u32 *)0x400290F0))

◆ PWM1_2_DBRISE_R

#define PWM1_2_DBRISE_R   (*((volatile u32 *)0x400290EC))

◆ PWM1_2_FLTSRC0_R

#define PWM1_2_FLTSRC0_R   (*((volatile u32 *)0x400290F4))

◆ PWM1_2_FLTSRC1_R

#define PWM1_2_FLTSRC1_R   (*((volatile u32 *)0x400290F8))

◆ PWM1_2_FLTSTAT0_R

#define PWM1_2_FLTSTAT0_R   (*((volatile u32 *)0x40029904))

◆ PWM1_2_FLTSTAT1_R

#define PWM1_2_FLTSTAT1_R   (*((volatile u32 *)0x40029908))

◆ PWM1_2_GENA_R

#define PWM1_2_GENA_R   (*((volatile u32 *)0x400290E0))

◆ PWM1_2_GENB_R

#define PWM1_2_GENB_R   (*((volatile u32 *)0x400290E4))

◆ PWM1_2_INTEN_R

#define PWM1_2_INTEN_R   (*((volatile u32 *)0x400290C4))

◆ PWM1_2_ISC_R

#define PWM1_2_ISC_R   (*((volatile u32 *)0x400290CC))

◆ PWM1_2_LOAD_R

#define PWM1_2_LOAD_R   (*((volatile u32 *)0x400290D0))

◆ PWM1_2_MINFLTPER_R

#define PWM1_2_MINFLTPER_R   (*((volatile u32 *)0x400290FC))

◆ PWM1_2_RIS_R

#define PWM1_2_RIS_R   (*((volatile u32 *)0x400290C8))

◆ PWM1_3_CMPA_R

#define PWM1_3_CMPA_R   (*((volatile u32 *)0x40029118))

◆ PWM1_3_CMPB_R

#define PWM1_3_CMPB_R   (*((volatile u32 *)0x4002911C))

◆ PWM1_3_COUNT_R

#define PWM1_3_COUNT_R   (*((volatile u32 *)0x40029114))

◆ PWM1_3_CTL_R

#define PWM1_3_CTL_R   (*((volatile u32 *)0x40029100))

◆ PWM1_3_DBCTL_R

#define PWM1_3_DBCTL_R   (*((volatile u32 *)0x40029128))

◆ PWM1_3_DBFALL_R

#define PWM1_3_DBFALL_R   (*((volatile u32 *)0x40029130))

◆ PWM1_3_DBRISE_R

#define PWM1_3_DBRISE_R   (*((volatile u32 *)0x4002912C))

◆ PWM1_3_FLTSRC0_R

#define PWM1_3_FLTSRC0_R   (*((volatile u32 *)0x40029134))

◆ PWM1_3_FLTSRC1_R

#define PWM1_3_FLTSRC1_R   (*((volatile u32 *)0x40029138))

◆ PWM1_3_FLTSTAT0_R

#define PWM1_3_FLTSTAT0_R   (*((volatile u32 *)0x40029984))

◆ PWM1_3_FLTSTAT1_R

#define PWM1_3_FLTSTAT1_R   (*((volatile u32 *)0x40029988))

◆ PWM1_3_GENA_R

#define PWM1_3_GENA_R   (*((volatile u32 *)0x40029120))

◆ PWM1_3_GENB_R

#define PWM1_3_GENB_R   (*((volatile u32 *)0x40029124))

◆ PWM1_3_INTEN_R

#define PWM1_3_INTEN_R   (*((volatile u32 *)0x40029104))

◆ PWM1_3_ISC_R

#define PWM1_3_ISC_R   (*((volatile u32 *)0x4002910C))

◆ PWM1_3_LOAD_R

#define PWM1_3_LOAD_R   (*((volatile u32 *)0x40029110))

◆ PWM1_3_MINFLTPER_R

#define PWM1_3_MINFLTPER_R   (*((volatile u32 *)0x4002913C))

◆ PWM1_3_RIS_R

#define PWM1_3_RIS_R   (*((volatile u32 *)0x40029108))

◆ PWM1_CTL_R

#define PWM1_CTL_R   (*((volatile u32 *)0x40029000))

◆ PWM1_ENABLE_R

#define PWM1_ENABLE_R   (*((volatile u32 *)0x40029008))

◆ PWM1_ENUPD_R

#define PWM1_ENUPD_R   (*((volatile u32 *)0x40029028))

◆ PWM1_FAULT_R

#define PWM1_FAULT_R   (*((volatile u32 *)0x40029010))

◆ PWM1_FAULTVAL_R

#define PWM1_FAULTVAL_R   (*((volatile u32 *)0x40029024))

◆ PWM1_INTEN_R

#define PWM1_INTEN_R   (*((volatile u32 *)0x40029014))

◆ PWM1_INVERT_R

#define PWM1_INVERT_R   (*((volatile u32 *)0x4002900C))

◆ PWM1_ISC_R

#define PWM1_ISC_R   (*((volatile u32 *)0x4002901C))

◆ PWM1_PP_R

#define PWM1_PP_R   (*((volatile u32 *)0x40029FC0))

◆ PWM1_RIS_R

#define PWM1_RIS_R   (*((volatile u32 *)0x40029018))

◆ PWM1_STATUS_R

#define PWM1_STATUS_R   (*((volatile u32 *)0x40029020))

◆ PWM1_SYNC_R

#define PWM1_SYNC_R   (*((volatile u32 *)0x40029004))

◆ PWM_0_CMPA_M

#define PWM_0_CMPA_M   0x0000FFFF

◆ PWM_0_CMPA_S

#define PWM_0_CMPA_S   0

◆ PWM_0_CMPB_M

#define PWM_0_CMPB_M   0x0000FFFF

◆ PWM_0_CMPB_S

#define PWM_0_CMPB_S   0

◆ PWM_0_COUNT_M

#define PWM_0_COUNT_M   0x0000FFFF

◆ PWM_0_COUNT_S

#define PWM_0_COUNT_S   0

◆ PWM_0_CTL_CMPAUPD

#define PWM_0_CTL_CMPAUPD   0x00000010

◆ PWM_0_CTL_CMPBUPD

#define PWM_0_CTL_CMPBUPD   0x00000020

◆ PWM_0_CTL_DBCTLUPD_GS

#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00

◆ PWM_0_CTL_DBCTLUPD_I

#define PWM_0_CTL_DBCTLUPD_I   0x00000000

◆ PWM_0_CTL_DBCTLUPD_LS

#define PWM_0_CTL_DBCTLUPD_LS   0x00000800

◆ PWM_0_CTL_DBCTLUPD_M

#define PWM_0_CTL_DBCTLUPD_M   0x00000C00

◆ PWM_0_CTL_DBFALLUPD_GS

#define PWM_0_CTL_DBFALLUPD_GS   0x0000C000

◆ PWM_0_CTL_DBFALLUPD_I

#define PWM_0_CTL_DBFALLUPD_I   0x00000000

◆ PWM_0_CTL_DBFALLUPD_LS

#define PWM_0_CTL_DBFALLUPD_LS   0x00008000

◆ PWM_0_CTL_DBFALLUPD_M

#define PWM_0_CTL_DBFALLUPD_M   0x0000C000

◆ PWM_0_CTL_DBRISEUPD_GS

#define PWM_0_CTL_DBRISEUPD_GS   0x00003000

◆ PWM_0_CTL_DBRISEUPD_I

#define PWM_0_CTL_DBRISEUPD_I   0x00000000

◆ PWM_0_CTL_DBRISEUPD_LS

#define PWM_0_CTL_DBRISEUPD_LS   0x00002000

◆ PWM_0_CTL_DBRISEUPD_M

#define PWM_0_CTL_DBRISEUPD_M   0x00003000

◆ PWM_0_CTL_DEBUG

#define PWM_0_CTL_DEBUG   0x00000004

◆ PWM_0_CTL_ENABLE

#define PWM_0_CTL_ENABLE   0x00000001

◆ PWM_0_CTL_FLTSRC

#define PWM_0_CTL_FLTSRC   0x00010000

◆ PWM_0_CTL_GENAUPD_GS

#define PWM_0_CTL_GENAUPD_GS   0x000000C0

◆ PWM_0_CTL_GENAUPD_I

#define PWM_0_CTL_GENAUPD_I   0x00000000

◆ PWM_0_CTL_GENAUPD_LS

#define PWM_0_CTL_GENAUPD_LS   0x00000080

◆ PWM_0_CTL_GENAUPD_M

#define PWM_0_CTL_GENAUPD_M   0x000000C0

◆ PWM_0_CTL_GENBUPD_GS

#define PWM_0_CTL_GENBUPD_GS   0x00000300

◆ PWM_0_CTL_GENBUPD_I

#define PWM_0_CTL_GENBUPD_I   0x00000000

◆ PWM_0_CTL_GENBUPD_LS

#define PWM_0_CTL_GENBUPD_LS   0x00000200

◆ PWM_0_CTL_GENBUPD_M

#define PWM_0_CTL_GENBUPD_M   0x00000300

◆ PWM_0_CTL_LATCH

#define PWM_0_CTL_LATCH   0x00040000

◆ PWM_0_CTL_LOADUPD

#define PWM_0_CTL_LOADUPD   0x00000008

◆ PWM_0_CTL_MINFLTPER

#define PWM_0_CTL_MINFLTPER   0x00020000

◆ PWM_0_CTL_MODE

#define PWM_0_CTL_MODE   0x00000002

◆ PWM_0_DBCTL_ENABLE

#define PWM_0_DBCTL_ENABLE   0x00000001

◆ PWM_0_DBFALL_DELAY_M

#define PWM_0_DBFALL_DELAY_M   0x00000FFF

◆ PWM_0_DBFALL_DELAY_S

#define PWM_0_DBFALL_DELAY_S   0

◆ PWM_0_DBRISE_DELAY_M

#define PWM_0_DBRISE_DELAY_M   0x00000FFF

◆ PWM_0_DBRISE_DELAY_S

#define PWM_0_DBRISE_DELAY_S   0

◆ PWM_0_FLTSEN_FAULT0

#define PWM_0_FLTSEN_FAULT0   0x00000001

◆ PWM_0_FLTSEN_FAULT1

#define PWM_0_FLTSEN_FAULT1   0x00000002

◆ PWM_0_FLTSRC0_FAULT0

#define PWM_0_FLTSRC0_FAULT0   0x00000001

◆ PWM_0_FLTSRC0_FAULT1

#define PWM_0_FLTSRC0_FAULT1   0x00000002

◆ PWM_0_FLTSRC1_DCMP0

#define PWM_0_FLTSRC1_DCMP0   0x00000001

◆ PWM_0_FLTSRC1_DCMP1

#define PWM_0_FLTSRC1_DCMP1   0x00000002

◆ PWM_0_FLTSRC1_DCMP2

#define PWM_0_FLTSRC1_DCMP2   0x00000004

◆ PWM_0_FLTSRC1_DCMP3

#define PWM_0_FLTSRC1_DCMP3   0x00000008

◆ PWM_0_FLTSRC1_DCMP4

#define PWM_0_FLTSRC1_DCMP4   0x00000010

◆ PWM_0_FLTSRC1_DCMP5

#define PWM_0_FLTSRC1_DCMP5   0x00000020

◆ PWM_0_FLTSRC1_DCMP6

#define PWM_0_FLTSRC1_DCMP6   0x00000040

◆ PWM_0_FLTSRC1_DCMP7

#define PWM_0_FLTSRC1_DCMP7   0x00000080

◆ PWM_0_FLTSTAT0_FAULT0

#define PWM_0_FLTSTAT0_FAULT0   0x00000001

◆ PWM_0_FLTSTAT0_FAULT1

#define PWM_0_FLTSTAT0_FAULT1   0x00000002

◆ PWM_0_FLTSTAT1_DCMP0

#define PWM_0_FLTSTAT1_DCMP0   0x00000001

◆ PWM_0_FLTSTAT1_DCMP1

#define PWM_0_FLTSTAT1_DCMP1   0x00000002

◆ PWM_0_FLTSTAT1_DCMP2

#define PWM_0_FLTSTAT1_DCMP2   0x00000004

◆ PWM_0_FLTSTAT1_DCMP3

#define PWM_0_FLTSTAT1_DCMP3   0x00000008

◆ PWM_0_FLTSTAT1_DCMP4

#define PWM_0_FLTSTAT1_DCMP4   0x00000010

◆ PWM_0_FLTSTAT1_DCMP5

#define PWM_0_FLTSTAT1_DCMP5   0x00000020

◆ PWM_0_FLTSTAT1_DCMP6

#define PWM_0_FLTSTAT1_DCMP6   0x00000040

◆ PWM_0_FLTSTAT1_DCMP7

#define PWM_0_FLTSTAT1_DCMP7   0x00000080

◆ PWM_0_GENA_ACTCMPAD_INV

#define PWM_0_GENA_ACTCMPAD_INV   0x00000040

◆ PWM_0_GENA_ACTCMPAD_M

#define PWM_0_GENA_ACTCMPAD_M   0x000000C0

◆ PWM_0_GENA_ACTCMPAD_NONE

#define PWM_0_GENA_ACTCMPAD_NONE    0x00000000

◆ PWM_0_GENA_ACTCMPAD_ONE

#define PWM_0_GENA_ACTCMPAD_ONE   0x000000C0

◆ PWM_0_GENA_ACTCMPAD_ZERO

#define PWM_0_GENA_ACTCMPAD_ZERO    0x00000080

◆ PWM_0_GENA_ACTCMPAU_INV

#define PWM_0_GENA_ACTCMPAU_INV   0x00000010

◆ PWM_0_GENA_ACTCMPAU_M

#define PWM_0_GENA_ACTCMPAU_M   0x00000030

◆ PWM_0_GENA_ACTCMPAU_NONE

#define PWM_0_GENA_ACTCMPAU_NONE    0x00000000

◆ PWM_0_GENA_ACTCMPAU_ONE

#define PWM_0_GENA_ACTCMPAU_ONE   0x00000030

◆ PWM_0_GENA_ACTCMPAU_ZERO

#define PWM_0_GENA_ACTCMPAU_ZERO    0x00000020

◆ PWM_0_GENA_ACTCMPBD_INV

#define PWM_0_GENA_ACTCMPBD_INV   0x00000400

◆ PWM_0_GENA_ACTCMPBD_M

#define PWM_0_GENA_ACTCMPBD_M   0x00000C00

◆ PWM_0_GENA_ACTCMPBD_NONE

#define PWM_0_GENA_ACTCMPBD_NONE    0x00000000

◆ PWM_0_GENA_ACTCMPBD_ONE

#define PWM_0_GENA_ACTCMPBD_ONE   0x00000C00

◆ PWM_0_GENA_ACTCMPBD_ZERO

#define PWM_0_GENA_ACTCMPBD_ZERO    0x00000800

◆ PWM_0_GENA_ACTCMPBU_INV

#define PWM_0_GENA_ACTCMPBU_INV   0x00000100

◆ PWM_0_GENA_ACTCMPBU_M

#define PWM_0_GENA_ACTCMPBU_M   0x00000300

◆ PWM_0_GENA_ACTCMPBU_NONE

#define PWM_0_GENA_ACTCMPBU_NONE    0x00000000

◆ PWM_0_GENA_ACTCMPBU_ONE

#define PWM_0_GENA_ACTCMPBU_ONE   0x00000300

◆ PWM_0_GENA_ACTCMPBU_ZERO

#define PWM_0_GENA_ACTCMPBU_ZERO    0x00000200

◆ PWM_0_GENA_ACTLOAD_INV

#define PWM_0_GENA_ACTLOAD_INV   0x00000004

◆ PWM_0_GENA_ACTLOAD_M

#define PWM_0_GENA_ACTLOAD_M   0x0000000C

◆ PWM_0_GENA_ACTLOAD_NONE

#define PWM_0_GENA_ACTLOAD_NONE   0x00000000

◆ PWM_0_GENA_ACTLOAD_ONE

#define PWM_0_GENA_ACTLOAD_ONE   0x0000000C

◆ PWM_0_GENA_ACTLOAD_ZERO

#define PWM_0_GENA_ACTLOAD_ZERO   0x00000008

◆ PWM_0_GENA_ACTZERO_INV

#define PWM_0_GENA_ACTZERO_INV   0x00000001

◆ PWM_0_GENA_ACTZERO_M

#define PWM_0_GENA_ACTZERO_M   0x00000003

◆ PWM_0_GENA_ACTZERO_NONE

#define PWM_0_GENA_ACTZERO_NONE   0x00000000

◆ PWM_0_GENA_ACTZERO_ONE

#define PWM_0_GENA_ACTZERO_ONE   0x00000003

◆ PWM_0_GENA_ACTZERO_ZERO

#define PWM_0_GENA_ACTZERO_ZERO   0x00000002

◆ PWM_0_GENB_ACTCMPAD_INV

#define PWM_0_GENB_ACTCMPAD_INV   0x00000040

◆ PWM_0_GENB_ACTCMPAD_M

#define PWM_0_GENB_ACTCMPAD_M   0x000000C0

◆ PWM_0_GENB_ACTCMPAD_NONE

#define PWM_0_GENB_ACTCMPAD_NONE    0x00000000

◆ PWM_0_GENB_ACTCMPAD_ONE

#define PWM_0_GENB_ACTCMPAD_ONE   0x000000C0

◆ PWM_0_GENB_ACTCMPAD_ZERO

#define PWM_0_GENB_ACTCMPAD_ZERO    0x00000080

◆ PWM_0_GENB_ACTCMPAU_INV

#define PWM_0_GENB_ACTCMPAU_INV   0x00000010

◆ PWM_0_GENB_ACTCMPAU_M

#define PWM_0_GENB_ACTCMPAU_M   0x00000030

◆ PWM_0_GENB_ACTCMPAU_NONE

#define PWM_0_GENB_ACTCMPAU_NONE    0x00000000

◆ PWM_0_GENB_ACTCMPAU_ONE

#define PWM_0_GENB_ACTCMPAU_ONE   0x00000030

◆ PWM_0_GENB_ACTCMPAU_ZERO

#define PWM_0_GENB_ACTCMPAU_ZERO    0x00000020

◆ PWM_0_GENB_ACTCMPBD_INV

#define PWM_0_GENB_ACTCMPBD_INV   0x00000400

◆ PWM_0_GENB_ACTCMPBD_M

#define PWM_0_GENB_ACTCMPBD_M   0x00000C00

◆ PWM_0_GENB_ACTCMPBD_NONE

#define PWM_0_GENB_ACTCMPBD_NONE    0x00000000

◆ PWM_0_GENB_ACTCMPBD_ONE

#define PWM_0_GENB_ACTCMPBD_ONE   0x00000C00

◆ PWM_0_GENB_ACTCMPBD_ZERO

#define PWM_0_GENB_ACTCMPBD_ZERO    0x00000800

◆ PWM_0_GENB_ACTCMPBU_INV

#define PWM_0_GENB_ACTCMPBU_INV   0x00000100

◆ PWM_0_GENB_ACTCMPBU_M

#define PWM_0_GENB_ACTCMPBU_M   0x00000300

◆ PWM_0_GENB_ACTCMPBU_NONE

#define PWM_0_GENB_ACTCMPBU_NONE    0x00000000

◆ PWM_0_GENB_ACTCMPBU_ONE

#define PWM_0_GENB_ACTCMPBU_ONE   0x00000300

◆ PWM_0_GENB_ACTCMPBU_ZERO

#define PWM_0_GENB_ACTCMPBU_ZERO    0x00000200

◆ PWM_0_GENB_ACTLOAD_INV

#define PWM_0_GENB_ACTLOAD_INV   0x00000004

◆ PWM_0_GENB_ACTLOAD_M

#define PWM_0_GENB_ACTLOAD_M   0x0000000C

◆ PWM_0_GENB_ACTLOAD_NONE

#define PWM_0_GENB_ACTLOAD_NONE   0x00000000

◆ PWM_0_GENB_ACTLOAD_ONE

#define PWM_0_GENB_ACTLOAD_ONE   0x0000000C

◆ PWM_0_GENB_ACTLOAD_ZERO

#define PWM_0_GENB_ACTLOAD_ZERO   0x00000008

◆ PWM_0_GENB_ACTZERO_INV

#define PWM_0_GENB_ACTZERO_INV   0x00000001

◆ PWM_0_GENB_ACTZERO_M

#define PWM_0_GENB_ACTZERO_M   0x00000003

◆ PWM_0_GENB_ACTZERO_NONE

#define PWM_0_GENB_ACTZERO_NONE   0x00000000

◆ PWM_0_GENB_ACTZERO_ONE

#define PWM_0_GENB_ACTZERO_ONE   0x00000003

◆ PWM_0_GENB_ACTZERO_ZERO

#define PWM_0_GENB_ACTZERO_ZERO   0x00000002

◆ PWM_0_INTEN_INTCMPAD

#define PWM_0_INTEN_INTCMPAD   0x00000008

◆ PWM_0_INTEN_INTCMPAU

#define PWM_0_INTEN_INTCMPAU   0x00000004

◆ PWM_0_INTEN_INTCMPBD

#define PWM_0_INTEN_INTCMPBD   0x00000020

◆ PWM_0_INTEN_INTCMPBU

#define PWM_0_INTEN_INTCMPBU   0x00000010

◆ PWM_0_INTEN_INTCNTLOAD

#define PWM_0_INTEN_INTCNTLOAD   0x00000002

◆ PWM_0_INTEN_INTCNTZERO

#define PWM_0_INTEN_INTCNTZERO   0x00000001

◆ PWM_0_INTEN_TRCMPAD

#define PWM_0_INTEN_TRCMPAD   0x00000800

◆ PWM_0_INTEN_TRCMPAU

#define PWM_0_INTEN_TRCMPAU   0x00000400

◆ PWM_0_INTEN_TRCMPBD

#define PWM_0_INTEN_TRCMPBD   0x00002000

◆ PWM_0_INTEN_TRCMPBU

#define PWM_0_INTEN_TRCMPBU   0x00001000

◆ PWM_0_INTEN_TRCNTLOAD

#define PWM_0_INTEN_TRCNTLOAD   0x00000200

◆ PWM_0_INTEN_TRCNTZERO

#define PWM_0_INTEN_TRCNTZERO   0x00000100

◆ PWM_0_ISC_INTCMPAD

#define PWM_0_ISC_INTCMPAD   0x00000008

◆ PWM_0_ISC_INTCMPAU

#define PWM_0_ISC_INTCMPAU   0x00000004

◆ PWM_0_ISC_INTCMPBD

#define PWM_0_ISC_INTCMPBD   0x00000020

◆ PWM_0_ISC_INTCMPBU

#define PWM_0_ISC_INTCMPBU   0x00000010

◆ PWM_0_ISC_INTCNTLOAD

#define PWM_0_ISC_INTCNTLOAD   0x00000002

◆ PWM_0_ISC_INTCNTZERO

#define PWM_0_ISC_INTCNTZERO   0x00000001

◆ PWM_0_LOAD_M

#define PWM_0_LOAD_M   0x0000FFFF

◆ PWM_0_LOAD_S

#define PWM_0_LOAD_S   0

◆ PWM_0_MINFLTPER_M

#define PWM_0_MINFLTPER_M   0x0000FFFF

◆ PWM_0_MINFLTPER_S

#define PWM_0_MINFLTPER_S   0

◆ PWM_0_RIS_INTCMPAD

#define PWM_0_RIS_INTCMPAD   0x00000008

◆ PWM_0_RIS_INTCMPAU

#define PWM_0_RIS_INTCMPAU   0x00000004

◆ PWM_0_RIS_INTCMPBD

#define PWM_0_RIS_INTCMPBD   0x00000020

◆ PWM_0_RIS_INTCMPBU

#define PWM_0_RIS_INTCMPBU   0x00000010

◆ PWM_0_RIS_INTCNTLOAD

#define PWM_0_RIS_INTCNTLOAD   0x00000002

◆ PWM_0_RIS_INTCNTZERO

#define PWM_0_RIS_INTCNTZERO   0x00000001

◆ PWM_1_CMPA_COMPA_M

#define PWM_1_CMPA_COMPA_M   0x0000FFFF

◆ PWM_1_CMPA_COMPA_S

#define PWM_1_CMPA_COMPA_S   0

◆ PWM_1_CMPB_COMPB_M

#define PWM_1_CMPB_COMPB_M   0x0000FFFF

◆ PWM_1_CMPB_COMPB_S

#define PWM_1_CMPB_COMPB_S   0

◆ PWM_1_COUNT_COUNT_M

#define PWM_1_COUNT_COUNT_M   0x0000FFFF

◆ PWM_1_COUNT_COUNT_S

#define PWM_1_COUNT_COUNT_S   0

◆ PWM_1_CTL_CMPAUPD

#define PWM_1_CTL_CMPAUPD   0x00000010

◆ PWM_1_CTL_CMPBUPD

#define PWM_1_CTL_CMPBUPD   0x00000020

◆ PWM_1_CTL_DBCTLUPD_GS

#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00

◆ PWM_1_CTL_DBCTLUPD_I

#define PWM_1_CTL_DBCTLUPD_I   0x00000000

◆ PWM_1_CTL_DBCTLUPD_LS

#define PWM_1_CTL_DBCTLUPD_LS   0x00000800

◆ PWM_1_CTL_DBCTLUPD_M

#define PWM_1_CTL_DBCTLUPD_M   0x00000C00

◆ PWM_1_CTL_DBFALLUPD_GS

#define PWM_1_CTL_DBFALLUPD_GS   0x0000C000

◆ PWM_1_CTL_DBFALLUPD_I

#define PWM_1_CTL_DBFALLUPD_I   0x00000000

◆ PWM_1_CTL_DBFALLUPD_LS

#define PWM_1_CTL_DBFALLUPD_LS   0x00008000

◆ PWM_1_CTL_DBFALLUPD_M

#define PWM_1_CTL_DBFALLUPD_M   0x0000C000

◆ PWM_1_CTL_DBRISEUPD_GS

#define PWM_1_CTL_DBRISEUPD_GS   0x00003000

◆ PWM_1_CTL_DBRISEUPD_I

#define PWM_1_CTL_DBRISEUPD_I   0x00000000

◆ PWM_1_CTL_DBRISEUPD_LS

#define PWM_1_CTL_DBRISEUPD_LS   0x00002000

◆ PWM_1_CTL_DBRISEUPD_M

#define PWM_1_CTL_DBRISEUPD_M   0x00003000

◆ PWM_1_CTL_DEBUG

#define PWM_1_CTL_DEBUG   0x00000004

◆ PWM_1_CTL_ENABLE

#define PWM_1_CTL_ENABLE   0x00000001

◆ PWM_1_CTL_FLTSRC

#define PWM_1_CTL_FLTSRC   0x00010000

◆ PWM_1_CTL_GENAUPD_GS

#define PWM_1_CTL_GENAUPD_GS   0x000000C0

◆ PWM_1_CTL_GENAUPD_I

#define PWM_1_CTL_GENAUPD_I   0x00000000

◆ PWM_1_CTL_GENAUPD_LS

#define PWM_1_CTL_GENAUPD_LS   0x00000080

◆ PWM_1_CTL_GENAUPD_M

#define PWM_1_CTL_GENAUPD_M   0x000000C0

◆ PWM_1_CTL_GENBUPD_GS

#define PWM_1_CTL_GENBUPD_GS   0x00000300

◆ PWM_1_CTL_GENBUPD_I

#define PWM_1_CTL_GENBUPD_I   0x00000000

◆ PWM_1_CTL_GENBUPD_LS

#define PWM_1_CTL_GENBUPD_LS   0x00000200

◆ PWM_1_CTL_GENBUPD_M

#define PWM_1_CTL_GENBUPD_M   0x00000300

◆ PWM_1_CTL_LATCH

#define PWM_1_CTL_LATCH   0x00040000

◆ PWM_1_CTL_LOADUPD

#define PWM_1_CTL_LOADUPD   0x00000008

◆ PWM_1_CTL_MINFLTPER

#define PWM_1_CTL_MINFLTPER   0x00020000

◆ PWM_1_CTL_MODE

#define PWM_1_CTL_MODE   0x00000002

◆ PWM_1_DBCTL_ENABLE

#define PWM_1_DBCTL_ENABLE   0x00000001

◆ PWM_1_DBFALL_FALLDELAY_M

#define PWM_1_DBFALL_FALLDELAY_M    0x00000FFF

◆ PWM_1_DBFALL_FALLDELAY_S

#define PWM_1_DBFALL_FALLDELAY_S    0

◆ PWM_1_DBRISE_RISEDELAY_M

#define PWM_1_DBRISE_RISEDELAY_M    0x00000FFF

◆ PWM_1_DBRISE_RISEDELAY_S

#define PWM_1_DBRISE_RISEDELAY_S    0

◆ PWM_1_FLTSEN_FAULT0

#define PWM_1_FLTSEN_FAULT0   0x00000001

◆ PWM_1_FLTSEN_FAULT1

#define PWM_1_FLTSEN_FAULT1   0x00000002

◆ PWM_1_FLTSRC0_FAULT0

#define PWM_1_FLTSRC0_FAULT0   0x00000001

◆ PWM_1_FLTSRC0_FAULT1

#define PWM_1_FLTSRC0_FAULT1   0x00000002

◆ PWM_1_FLTSRC1_DCMP0

#define PWM_1_FLTSRC1_DCMP0   0x00000001

◆ PWM_1_FLTSRC1_DCMP1

#define PWM_1_FLTSRC1_DCMP1   0x00000002

◆ PWM_1_FLTSRC1_DCMP2

#define PWM_1_FLTSRC1_DCMP2   0x00000004

◆ PWM_1_FLTSRC1_DCMP3

#define PWM_1_FLTSRC1_DCMP3   0x00000008

◆ PWM_1_FLTSRC1_DCMP4

#define PWM_1_FLTSRC1_DCMP4   0x00000010

◆ PWM_1_FLTSRC1_DCMP5

#define PWM_1_FLTSRC1_DCMP5   0x00000020

◆ PWM_1_FLTSRC1_DCMP6

#define PWM_1_FLTSRC1_DCMP6   0x00000040

◆ PWM_1_FLTSRC1_DCMP7

#define PWM_1_FLTSRC1_DCMP7   0x00000080

◆ PWM_1_FLTSTAT0_FAULT0

#define PWM_1_FLTSTAT0_FAULT0   0x00000001

◆ PWM_1_FLTSTAT0_FAULT1

#define PWM_1_FLTSTAT0_FAULT1   0x00000002

◆ PWM_1_FLTSTAT1_DCMP0

#define PWM_1_FLTSTAT1_DCMP0   0x00000001

◆ PWM_1_FLTSTAT1_DCMP1

#define PWM_1_FLTSTAT1_DCMP1   0x00000002

◆ PWM_1_FLTSTAT1_DCMP2

#define PWM_1_FLTSTAT1_DCMP2   0x00000004

◆ PWM_1_FLTSTAT1_DCMP3

#define PWM_1_FLTSTAT1_DCMP3   0x00000008

◆ PWM_1_FLTSTAT1_DCMP4

#define PWM_1_FLTSTAT1_DCMP4   0x00000010

◆ PWM_1_FLTSTAT1_DCMP5

#define PWM_1_FLTSTAT1_DCMP5   0x00000020

◆ PWM_1_FLTSTAT1_DCMP6

#define PWM_1_FLTSTAT1_DCMP6   0x00000040

◆ PWM_1_FLTSTAT1_DCMP7

#define PWM_1_FLTSTAT1_DCMP7   0x00000080

◆ PWM_1_GENA_ACTCMPAD_INV

#define PWM_1_GENA_ACTCMPAD_INV   0x00000040

◆ PWM_1_GENA_ACTCMPAD_M

#define PWM_1_GENA_ACTCMPAD_M   0x000000C0

◆ PWM_1_GENA_ACTCMPAD_NONE

#define PWM_1_GENA_ACTCMPAD_NONE    0x00000000

◆ PWM_1_GENA_ACTCMPAD_ONE

#define PWM_1_GENA_ACTCMPAD_ONE   0x000000C0

◆ PWM_1_GENA_ACTCMPAD_ZERO

#define PWM_1_GENA_ACTCMPAD_ZERO    0x00000080

◆ PWM_1_GENA_ACTCMPAU_INV

#define PWM_1_GENA_ACTCMPAU_INV   0x00000010

◆ PWM_1_GENA_ACTCMPAU_M

#define PWM_1_GENA_ACTCMPAU_M   0x00000030

◆ PWM_1_GENA_ACTCMPAU_NONE

#define PWM_1_GENA_ACTCMPAU_NONE    0x00000000

◆ PWM_1_GENA_ACTCMPAU_ONE

#define PWM_1_GENA_ACTCMPAU_ONE   0x00000030

◆ PWM_1_GENA_ACTCMPAU_ZERO

#define PWM_1_GENA_ACTCMPAU_ZERO    0x00000020

◆ PWM_1_GENA_ACTCMPBD_INV

#define PWM_1_GENA_ACTCMPBD_INV   0x00000400

◆ PWM_1_GENA_ACTCMPBD_M

#define PWM_1_GENA_ACTCMPBD_M   0x00000C00

◆ PWM_1_GENA_ACTCMPBD_NONE

#define PWM_1_GENA_ACTCMPBD_NONE    0x00000000

◆ PWM_1_GENA_ACTCMPBD_ONE

#define PWM_1_GENA_ACTCMPBD_ONE   0x00000C00

◆ PWM_1_GENA_ACTCMPBD_ZERO

#define PWM_1_GENA_ACTCMPBD_ZERO    0x00000800

◆ PWM_1_GENA_ACTCMPBU_INV

#define PWM_1_GENA_ACTCMPBU_INV   0x00000100

◆ PWM_1_GENA_ACTCMPBU_M

#define PWM_1_GENA_ACTCMPBU_M   0x00000300

◆ PWM_1_GENA_ACTCMPBU_NONE

#define PWM_1_GENA_ACTCMPBU_NONE    0x00000000

◆ PWM_1_GENA_ACTCMPBU_ONE

#define PWM_1_GENA_ACTCMPBU_ONE   0x00000300

◆ PWM_1_GENA_ACTCMPBU_ZERO

#define PWM_1_GENA_ACTCMPBU_ZERO    0x00000200

◆ PWM_1_GENA_ACTLOAD_INV

#define PWM_1_GENA_ACTLOAD_INV   0x00000004

◆ PWM_1_GENA_ACTLOAD_M

#define PWM_1_GENA_ACTLOAD_M   0x0000000C

◆ PWM_1_GENA_ACTLOAD_NONE

#define PWM_1_GENA_ACTLOAD_NONE   0x00000000

◆ PWM_1_GENA_ACTLOAD_ONE

#define PWM_1_GENA_ACTLOAD_ONE   0x0000000C

◆ PWM_1_GENA_ACTLOAD_ZERO

#define PWM_1_GENA_ACTLOAD_ZERO   0x00000008

◆ PWM_1_GENA_ACTZERO_INV

#define PWM_1_GENA_ACTZERO_INV   0x00000001

◆ PWM_1_GENA_ACTZERO_M

#define PWM_1_GENA_ACTZERO_M   0x00000003

◆ PWM_1_GENA_ACTZERO_NONE

#define PWM_1_GENA_ACTZERO_NONE   0x00000000

◆ PWM_1_GENA_ACTZERO_ONE

#define PWM_1_GENA_ACTZERO_ONE   0x00000003

◆ PWM_1_GENA_ACTZERO_ZERO

#define PWM_1_GENA_ACTZERO_ZERO   0x00000002

◆ PWM_1_GENB_ACTCMPAD_INV

#define PWM_1_GENB_ACTCMPAD_INV   0x00000040

◆ PWM_1_GENB_ACTCMPAD_M

#define PWM_1_GENB_ACTCMPAD_M   0x000000C0

◆ PWM_1_GENB_ACTCMPAD_NONE

#define PWM_1_GENB_ACTCMPAD_NONE    0x00000000

◆ PWM_1_GENB_ACTCMPAD_ONE

#define PWM_1_GENB_ACTCMPAD_ONE   0x000000C0

◆ PWM_1_GENB_ACTCMPAD_ZERO

#define PWM_1_GENB_ACTCMPAD_ZERO    0x00000080

◆ PWM_1_GENB_ACTCMPAU_INV

#define PWM_1_GENB_ACTCMPAU_INV   0x00000010

◆ PWM_1_GENB_ACTCMPAU_M

#define PWM_1_GENB_ACTCMPAU_M   0x00000030

◆ PWM_1_GENB_ACTCMPAU_NONE

#define PWM_1_GENB_ACTCMPAU_NONE    0x00000000

◆ PWM_1_GENB_ACTCMPAU_ONE

#define PWM_1_GENB_ACTCMPAU_ONE   0x00000030

◆ PWM_1_GENB_ACTCMPAU_ZERO

#define PWM_1_GENB_ACTCMPAU_ZERO    0x00000020

◆ PWM_1_GENB_ACTCMPBD_INV

#define PWM_1_GENB_ACTCMPBD_INV   0x00000400

◆ PWM_1_GENB_ACTCMPBD_M

#define PWM_1_GENB_ACTCMPBD_M   0x00000C00

◆ PWM_1_GENB_ACTCMPBD_NONE

#define PWM_1_GENB_ACTCMPBD_NONE    0x00000000

◆ PWM_1_GENB_ACTCMPBD_ONE

#define PWM_1_GENB_ACTCMPBD_ONE   0x00000C00

◆ PWM_1_GENB_ACTCMPBD_ZERO

#define PWM_1_GENB_ACTCMPBD_ZERO    0x00000800

◆ PWM_1_GENB_ACTCMPBU_INV

#define PWM_1_GENB_ACTCMPBU_INV   0x00000100

◆ PWM_1_GENB_ACTCMPBU_M

#define PWM_1_GENB_ACTCMPBU_M   0x00000300

◆ PWM_1_GENB_ACTCMPBU_NONE

#define PWM_1_GENB_ACTCMPBU_NONE    0x00000000

◆ PWM_1_GENB_ACTCMPBU_ONE

#define PWM_1_GENB_ACTCMPBU_ONE   0x00000300

◆ PWM_1_GENB_ACTCMPBU_ZERO

#define PWM_1_GENB_ACTCMPBU_ZERO    0x00000200

◆ PWM_1_GENB_ACTLOAD_INV

#define PWM_1_GENB_ACTLOAD_INV   0x00000004

◆ PWM_1_GENB_ACTLOAD_M

#define PWM_1_GENB_ACTLOAD_M   0x0000000C

◆ PWM_1_GENB_ACTLOAD_NONE

#define PWM_1_GENB_ACTLOAD_NONE   0x00000000

◆ PWM_1_GENB_ACTLOAD_ONE

#define PWM_1_GENB_ACTLOAD_ONE   0x0000000C

◆ PWM_1_GENB_ACTLOAD_ZERO

#define PWM_1_GENB_ACTLOAD_ZERO   0x00000008

◆ PWM_1_GENB_ACTZERO_INV

#define PWM_1_GENB_ACTZERO_INV   0x00000001

◆ PWM_1_GENB_ACTZERO_M

#define PWM_1_GENB_ACTZERO_M   0x00000003

◆ PWM_1_GENB_ACTZERO_NONE

#define PWM_1_GENB_ACTZERO_NONE   0x00000000

◆ PWM_1_GENB_ACTZERO_ONE

#define PWM_1_GENB_ACTZERO_ONE   0x00000003

◆ PWM_1_GENB_ACTZERO_ZERO

#define PWM_1_GENB_ACTZERO_ZERO   0x00000002

◆ PWM_1_INTEN_INTCMPAD

#define PWM_1_INTEN_INTCMPAD   0x00000008

◆ PWM_1_INTEN_INTCMPAU

#define PWM_1_INTEN_INTCMPAU   0x00000004

◆ PWM_1_INTEN_INTCMPBD

#define PWM_1_INTEN_INTCMPBD   0x00000020

◆ PWM_1_INTEN_INTCMPBU

#define PWM_1_INTEN_INTCMPBU   0x00000010

◆ PWM_1_INTEN_INTCNTLOAD

#define PWM_1_INTEN_INTCNTLOAD   0x00000002

◆ PWM_1_INTEN_INTCNTZERO

#define PWM_1_INTEN_INTCNTZERO   0x00000001

◆ PWM_1_INTEN_TRCMPAD

#define PWM_1_INTEN_TRCMPAD   0x00000800

◆ PWM_1_INTEN_TRCMPAU

#define PWM_1_INTEN_TRCMPAU   0x00000400

◆ PWM_1_INTEN_TRCMPBD

#define PWM_1_INTEN_TRCMPBD   0x00002000

◆ PWM_1_INTEN_TRCMPBU

#define PWM_1_INTEN_TRCMPBU   0x00001000

◆ PWM_1_INTEN_TRCNTLOAD

#define PWM_1_INTEN_TRCNTLOAD   0x00000200

◆ PWM_1_INTEN_TRCNTZERO

#define PWM_1_INTEN_TRCNTZERO   0x00000100

◆ PWM_1_ISC_INTCMPAD

#define PWM_1_ISC_INTCMPAD   0x00000008

◆ PWM_1_ISC_INTCMPAU

#define PWM_1_ISC_INTCMPAU   0x00000004

◆ PWM_1_ISC_INTCMPBD

#define PWM_1_ISC_INTCMPBD   0x00000020

◆ PWM_1_ISC_INTCMPBU

#define PWM_1_ISC_INTCMPBU   0x00000010

◆ PWM_1_ISC_INTCNTLOAD

#define PWM_1_ISC_INTCNTLOAD   0x00000002

◆ PWM_1_ISC_INTCNTZERO

#define PWM_1_ISC_INTCNTZERO   0x00000001

◆ PWM_1_LOAD_LOAD_M

#define PWM_1_LOAD_LOAD_M   0x0000FFFF

◆ PWM_1_LOAD_LOAD_S

#define PWM_1_LOAD_LOAD_S   0

◆ PWM_1_MINFLTPER_MFP_M

#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF

◆ PWM_1_MINFLTPER_MFP_S

#define PWM_1_MINFLTPER_MFP_S   0

◆ PWM_1_RIS_INTCMPAD

#define PWM_1_RIS_INTCMPAD   0x00000008

◆ PWM_1_RIS_INTCMPAU

#define PWM_1_RIS_INTCMPAU   0x00000004

◆ PWM_1_RIS_INTCMPBD

#define PWM_1_RIS_INTCMPBD   0x00000020

◆ PWM_1_RIS_INTCMPBU

#define PWM_1_RIS_INTCMPBU   0x00000010

◆ PWM_1_RIS_INTCNTLOAD

#define PWM_1_RIS_INTCNTLOAD   0x00000002

◆ PWM_1_RIS_INTCNTZERO

#define PWM_1_RIS_INTCNTZERO   0x00000001

◆ PWM_2_CMPA_COMPA_M

#define PWM_2_CMPA_COMPA_M   0x0000FFFF

◆ PWM_2_CMPA_COMPA_S

#define PWM_2_CMPA_COMPA_S   0

◆ PWM_2_CMPB_COMPB_M

#define PWM_2_CMPB_COMPB_M   0x0000FFFF

◆ PWM_2_CMPB_COMPB_S

#define PWM_2_CMPB_COMPB_S   0

◆ PWM_2_COUNT_COUNT_M

#define PWM_2_COUNT_COUNT_M   0x0000FFFF

◆ PWM_2_COUNT_COUNT_S

#define PWM_2_COUNT_COUNT_S   0

◆ PWM_2_CTL_CMPAUPD

#define PWM_2_CTL_CMPAUPD   0x00000010

◆ PWM_2_CTL_CMPBUPD

#define PWM_2_CTL_CMPBUPD   0x00000020

◆ PWM_2_CTL_DBCTLUPD_GS

#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00

◆ PWM_2_CTL_DBCTLUPD_I

#define PWM_2_CTL_DBCTLUPD_I   0x00000000

◆ PWM_2_CTL_DBCTLUPD_LS

#define PWM_2_CTL_DBCTLUPD_LS   0x00000800

◆ PWM_2_CTL_DBCTLUPD_M

#define PWM_2_CTL_DBCTLUPD_M   0x00000C00

◆ PWM_2_CTL_DBFALLUPD_GS

#define PWM_2_CTL_DBFALLUPD_GS   0x0000C000

◆ PWM_2_CTL_DBFALLUPD_I

#define PWM_2_CTL_DBFALLUPD_I   0x00000000

◆ PWM_2_CTL_DBFALLUPD_LS

#define PWM_2_CTL_DBFALLUPD_LS   0x00008000

◆ PWM_2_CTL_DBFALLUPD_M

#define PWM_2_CTL_DBFALLUPD_M   0x0000C000

◆ PWM_2_CTL_DBRISEUPD_GS

#define PWM_2_CTL_DBRISEUPD_GS   0x00003000

◆ PWM_2_CTL_DBRISEUPD_I

#define PWM_2_CTL_DBRISEUPD_I   0x00000000

◆ PWM_2_CTL_DBRISEUPD_LS

#define PWM_2_CTL_DBRISEUPD_LS   0x00002000

◆ PWM_2_CTL_DBRISEUPD_M

#define PWM_2_CTL_DBRISEUPD_M   0x00003000

◆ PWM_2_CTL_DEBUG

#define PWM_2_CTL_DEBUG   0x00000004

◆ PWM_2_CTL_ENABLE

#define PWM_2_CTL_ENABLE   0x00000001

◆ PWM_2_CTL_FLTSRC

#define PWM_2_CTL_FLTSRC   0x00010000

◆ PWM_2_CTL_GENAUPD_GS

#define PWM_2_CTL_GENAUPD_GS   0x000000C0

◆ PWM_2_CTL_GENAUPD_I

#define PWM_2_CTL_GENAUPD_I   0x00000000

◆ PWM_2_CTL_GENAUPD_LS

#define PWM_2_CTL_GENAUPD_LS   0x00000080

◆ PWM_2_CTL_GENAUPD_M

#define PWM_2_CTL_GENAUPD_M   0x000000C0

◆ PWM_2_CTL_GENBUPD_GS

#define PWM_2_CTL_GENBUPD_GS   0x00000300

◆ PWM_2_CTL_GENBUPD_I

#define PWM_2_CTL_GENBUPD_I   0x00000000

◆ PWM_2_CTL_GENBUPD_LS

#define PWM_2_CTL_GENBUPD_LS   0x00000200

◆ PWM_2_CTL_GENBUPD_M

#define PWM_2_CTL_GENBUPD_M   0x00000300

◆ PWM_2_CTL_LATCH

#define PWM_2_CTL_LATCH   0x00040000

◆ PWM_2_CTL_LOADUPD

#define PWM_2_CTL_LOADUPD   0x00000008

◆ PWM_2_CTL_MINFLTPER

#define PWM_2_CTL_MINFLTPER   0x00020000

◆ PWM_2_CTL_MODE

#define PWM_2_CTL_MODE   0x00000002

◆ PWM_2_DBCTL_ENABLE

#define PWM_2_DBCTL_ENABLE   0x00000001

◆ PWM_2_DBFALL_FALLDELAY_M

#define PWM_2_DBFALL_FALLDELAY_M    0x00000FFF

◆ PWM_2_DBFALL_FALLDELAY_S

#define PWM_2_DBFALL_FALLDELAY_S    0

◆ PWM_2_DBRISE_RISEDELAY_M

#define PWM_2_DBRISE_RISEDELAY_M    0x00000FFF

◆ PWM_2_DBRISE_RISEDELAY_S

#define PWM_2_DBRISE_RISEDELAY_S    0

◆ PWM_2_FLTSRC0_FAULT0

#define PWM_2_FLTSRC0_FAULT0   0x00000001

◆ PWM_2_FLTSRC0_FAULT1

#define PWM_2_FLTSRC0_FAULT1   0x00000002

◆ PWM_2_FLTSRC1_DCMP0

#define PWM_2_FLTSRC1_DCMP0   0x00000001

◆ PWM_2_FLTSRC1_DCMP1

#define PWM_2_FLTSRC1_DCMP1   0x00000002

◆ PWM_2_FLTSRC1_DCMP2

#define PWM_2_FLTSRC1_DCMP2   0x00000004

◆ PWM_2_FLTSRC1_DCMP3

#define PWM_2_FLTSRC1_DCMP3   0x00000008

◆ PWM_2_FLTSRC1_DCMP4

#define PWM_2_FLTSRC1_DCMP4   0x00000010

◆ PWM_2_FLTSRC1_DCMP5

#define PWM_2_FLTSRC1_DCMP5   0x00000020

◆ PWM_2_FLTSRC1_DCMP6

#define PWM_2_FLTSRC1_DCMP6   0x00000040

◆ PWM_2_FLTSRC1_DCMP7

#define PWM_2_FLTSRC1_DCMP7   0x00000080

◆ PWM_2_FLTSTAT0_FAULT0

#define PWM_2_FLTSTAT0_FAULT0   0x00000001

◆ PWM_2_FLTSTAT0_FAULT1

#define PWM_2_FLTSTAT0_FAULT1   0x00000002

◆ PWM_2_FLTSTAT1_DCMP0

#define PWM_2_FLTSTAT1_DCMP0   0x00000001

◆ PWM_2_FLTSTAT1_DCMP1

#define PWM_2_FLTSTAT1_DCMP1   0x00000002

◆ PWM_2_FLTSTAT1_DCMP2

#define PWM_2_FLTSTAT1_DCMP2   0x00000004

◆ PWM_2_FLTSTAT1_DCMP3

#define PWM_2_FLTSTAT1_DCMP3   0x00000008

◆ PWM_2_FLTSTAT1_DCMP4

#define PWM_2_FLTSTAT1_DCMP4   0x00000010

◆ PWM_2_FLTSTAT1_DCMP5

#define PWM_2_FLTSTAT1_DCMP5   0x00000020

◆ PWM_2_FLTSTAT1_DCMP6

#define PWM_2_FLTSTAT1_DCMP6   0x00000040

◆ PWM_2_FLTSTAT1_DCMP7

#define PWM_2_FLTSTAT1_DCMP7   0x00000080

◆ PWM_2_GENA_ACTCMPAD_INV

#define PWM_2_GENA_ACTCMPAD_INV   0x00000040

◆ PWM_2_GENA_ACTCMPAD_M

#define PWM_2_GENA_ACTCMPAD_M   0x000000C0

◆ PWM_2_GENA_ACTCMPAD_NONE

#define PWM_2_GENA_ACTCMPAD_NONE    0x00000000

◆ PWM_2_GENA_ACTCMPAD_ONE

#define PWM_2_GENA_ACTCMPAD_ONE   0x000000C0

◆ PWM_2_GENA_ACTCMPAD_ZERO

#define PWM_2_GENA_ACTCMPAD_ZERO    0x00000080

◆ PWM_2_GENA_ACTCMPAU_INV

#define PWM_2_GENA_ACTCMPAU_INV   0x00000010

◆ PWM_2_GENA_ACTCMPAU_M

#define PWM_2_GENA_ACTCMPAU_M   0x00000030

◆ PWM_2_GENA_ACTCMPAU_NONE

#define PWM_2_GENA_ACTCMPAU_NONE    0x00000000

◆ PWM_2_GENA_ACTCMPAU_ONE

#define PWM_2_GENA_ACTCMPAU_ONE   0x00000030

◆ PWM_2_GENA_ACTCMPAU_ZERO

#define PWM_2_GENA_ACTCMPAU_ZERO    0x00000020

◆ PWM_2_GENA_ACTCMPBD_INV

#define PWM_2_GENA_ACTCMPBD_INV   0x00000400

◆ PWM_2_GENA_ACTCMPBD_M

#define PWM_2_GENA_ACTCMPBD_M   0x00000C00

◆ PWM_2_GENA_ACTCMPBD_NONE

#define PWM_2_GENA_ACTCMPBD_NONE    0x00000000

◆ PWM_2_GENA_ACTCMPBD_ONE

#define PWM_2_GENA_ACTCMPBD_ONE   0x00000C00

◆ PWM_2_GENA_ACTCMPBD_ZERO

#define PWM_2_GENA_ACTCMPBD_ZERO    0x00000800

◆ PWM_2_GENA_ACTCMPBU_INV

#define PWM_2_GENA_ACTCMPBU_INV   0x00000100

◆ PWM_2_GENA_ACTCMPBU_M

#define PWM_2_GENA_ACTCMPBU_M   0x00000300

◆ PWM_2_GENA_ACTCMPBU_NONE

#define PWM_2_GENA_ACTCMPBU_NONE    0x00000000

◆ PWM_2_GENA_ACTCMPBU_ONE

#define PWM_2_GENA_ACTCMPBU_ONE   0x00000300

◆ PWM_2_GENA_ACTCMPBU_ZERO

#define PWM_2_GENA_ACTCMPBU_ZERO    0x00000200

◆ PWM_2_GENA_ACTLOAD_INV

#define PWM_2_GENA_ACTLOAD_INV   0x00000004

◆ PWM_2_GENA_ACTLOAD_M

#define PWM_2_GENA_ACTLOAD_M   0x0000000C

◆ PWM_2_GENA_ACTLOAD_NONE

#define PWM_2_GENA_ACTLOAD_NONE   0x00000000

◆ PWM_2_GENA_ACTLOAD_ONE

#define PWM_2_GENA_ACTLOAD_ONE   0x0000000C

◆ PWM_2_GENA_ACTLOAD_ZERO

#define PWM_2_GENA_ACTLOAD_ZERO   0x00000008

◆ PWM_2_GENA_ACTZERO_INV

#define PWM_2_GENA_ACTZERO_INV   0x00000001

◆ PWM_2_GENA_ACTZERO_M

#define PWM_2_GENA_ACTZERO_M   0x00000003

◆ PWM_2_GENA_ACTZERO_NONE

#define PWM_2_GENA_ACTZERO_NONE   0x00000000

◆ PWM_2_GENA_ACTZERO_ONE

#define PWM_2_GENA_ACTZERO_ONE   0x00000003

◆ PWM_2_GENA_ACTZERO_ZERO

#define PWM_2_GENA_ACTZERO_ZERO   0x00000002

◆ PWM_2_GENB_ACTCMPAD_INV

#define PWM_2_GENB_ACTCMPAD_INV   0x00000040

◆ PWM_2_GENB_ACTCMPAD_M

#define PWM_2_GENB_ACTCMPAD_M   0x000000C0

◆ PWM_2_GENB_ACTCMPAD_NONE

#define PWM_2_GENB_ACTCMPAD_NONE    0x00000000

◆ PWM_2_GENB_ACTCMPAD_ONE

#define PWM_2_GENB_ACTCMPAD_ONE   0x000000C0

◆ PWM_2_GENB_ACTCMPAD_ZERO

#define PWM_2_GENB_ACTCMPAD_ZERO    0x00000080

◆ PWM_2_GENB_ACTCMPAU_INV

#define PWM_2_GENB_ACTCMPAU_INV   0x00000010

◆ PWM_2_GENB_ACTCMPAU_M

#define PWM_2_GENB_ACTCMPAU_M   0x00000030

◆ PWM_2_GENB_ACTCMPAU_NONE

#define PWM_2_GENB_ACTCMPAU_NONE    0x00000000

◆ PWM_2_GENB_ACTCMPAU_ONE

#define PWM_2_GENB_ACTCMPAU_ONE   0x00000030

◆ PWM_2_GENB_ACTCMPAU_ZERO

#define PWM_2_GENB_ACTCMPAU_ZERO    0x00000020

◆ PWM_2_GENB_ACTCMPBD_INV

#define PWM_2_GENB_ACTCMPBD_INV   0x00000400

◆ PWM_2_GENB_ACTCMPBD_M

#define PWM_2_GENB_ACTCMPBD_M   0x00000C00

◆ PWM_2_GENB_ACTCMPBD_NONE

#define PWM_2_GENB_ACTCMPBD_NONE    0x00000000

◆ PWM_2_GENB_ACTCMPBD_ONE

#define PWM_2_GENB_ACTCMPBD_ONE   0x00000C00

◆ PWM_2_GENB_ACTCMPBD_ZERO

#define PWM_2_GENB_ACTCMPBD_ZERO    0x00000800

◆ PWM_2_GENB_ACTCMPBU_INV

#define PWM_2_GENB_ACTCMPBU_INV   0x00000100

◆ PWM_2_GENB_ACTCMPBU_M

#define PWM_2_GENB_ACTCMPBU_M   0x00000300

◆ PWM_2_GENB_ACTCMPBU_NONE

#define PWM_2_GENB_ACTCMPBU_NONE    0x00000000

◆ PWM_2_GENB_ACTCMPBU_ONE

#define PWM_2_GENB_ACTCMPBU_ONE   0x00000300

◆ PWM_2_GENB_ACTCMPBU_ZERO

#define PWM_2_GENB_ACTCMPBU_ZERO    0x00000200

◆ PWM_2_GENB_ACTLOAD_INV

#define PWM_2_GENB_ACTLOAD_INV   0x00000004

◆ PWM_2_GENB_ACTLOAD_M

#define PWM_2_GENB_ACTLOAD_M   0x0000000C

◆ PWM_2_GENB_ACTLOAD_NONE

#define PWM_2_GENB_ACTLOAD_NONE   0x00000000

◆ PWM_2_GENB_ACTLOAD_ONE

#define PWM_2_GENB_ACTLOAD_ONE   0x0000000C

◆ PWM_2_GENB_ACTLOAD_ZERO

#define PWM_2_GENB_ACTLOAD_ZERO   0x00000008

◆ PWM_2_GENB_ACTZERO_INV

#define PWM_2_GENB_ACTZERO_INV   0x00000001

◆ PWM_2_GENB_ACTZERO_M

#define PWM_2_GENB_ACTZERO_M   0x00000003

◆ PWM_2_GENB_ACTZERO_NONE

#define PWM_2_GENB_ACTZERO_NONE   0x00000000

◆ PWM_2_GENB_ACTZERO_ONE

#define PWM_2_GENB_ACTZERO_ONE   0x00000003

◆ PWM_2_GENB_ACTZERO_ZERO

#define PWM_2_GENB_ACTZERO_ZERO   0x00000002

◆ PWM_2_INTEN_INTCMPAD

#define PWM_2_INTEN_INTCMPAD   0x00000008

◆ PWM_2_INTEN_INTCMPAU

#define PWM_2_INTEN_INTCMPAU   0x00000004

◆ PWM_2_INTEN_INTCMPBD

#define PWM_2_INTEN_INTCMPBD   0x00000020

◆ PWM_2_INTEN_INTCMPBU

#define PWM_2_INTEN_INTCMPBU   0x00000010

◆ PWM_2_INTEN_INTCNTLOAD

#define PWM_2_INTEN_INTCNTLOAD   0x00000002

◆ PWM_2_INTEN_INTCNTZERO

#define PWM_2_INTEN_INTCNTZERO   0x00000001

◆ PWM_2_INTEN_TRCMPAD

#define PWM_2_INTEN_TRCMPAD   0x00000800

◆ PWM_2_INTEN_TRCMPAU

#define PWM_2_INTEN_TRCMPAU   0x00000400

◆ PWM_2_INTEN_TRCMPBD

#define PWM_2_INTEN_TRCMPBD   0x00002000

◆ PWM_2_INTEN_TRCMPBU

#define PWM_2_INTEN_TRCMPBU   0x00001000

◆ PWM_2_INTEN_TRCNTLOAD

#define PWM_2_INTEN_TRCNTLOAD   0x00000200

◆ PWM_2_INTEN_TRCNTZERO

#define PWM_2_INTEN_TRCNTZERO   0x00000100

◆ PWM_2_ISC_INTCMPAD

#define PWM_2_ISC_INTCMPAD   0x00000008

◆ PWM_2_ISC_INTCMPAU

#define PWM_2_ISC_INTCMPAU   0x00000004

◆ PWM_2_ISC_INTCMPBD

#define PWM_2_ISC_INTCMPBD   0x00000020

◆ PWM_2_ISC_INTCMPBU

#define PWM_2_ISC_INTCMPBU   0x00000010

◆ PWM_2_ISC_INTCNTLOAD

#define PWM_2_ISC_INTCNTLOAD   0x00000002

◆ PWM_2_ISC_INTCNTZERO

#define PWM_2_ISC_INTCNTZERO   0x00000001

◆ PWM_2_LOAD_LOAD_M

#define PWM_2_LOAD_LOAD_M   0x0000FFFF

◆ PWM_2_LOAD_LOAD_S

#define PWM_2_LOAD_LOAD_S   0

◆ PWM_2_MINFLTPER_MFP_M

#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF

◆ PWM_2_MINFLTPER_MFP_S

#define PWM_2_MINFLTPER_MFP_S   0

◆ PWM_2_RIS_INTCMPAD

#define PWM_2_RIS_INTCMPAD   0x00000008

◆ PWM_2_RIS_INTCMPAU

#define PWM_2_RIS_INTCMPAU   0x00000004

◆ PWM_2_RIS_INTCMPBD

#define PWM_2_RIS_INTCMPBD   0x00000020

◆ PWM_2_RIS_INTCMPBU

#define PWM_2_RIS_INTCMPBU   0x00000010

◆ PWM_2_RIS_INTCNTLOAD

#define PWM_2_RIS_INTCNTLOAD   0x00000002

◆ PWM_2_RIS_INTCNTZERO

#define PWM_2_RIS_INTCNTZERO   0x00000001

◆ PWM_3_CMPA_COMPA_M

#define PWM_3_CMPA_COMPA_M   0x0000FFFF

◆ PWM_3_CMPA_COMPA_S

#define PWM_3_CMPA_COMPA_S   0

◆ PWM_3_CMPB_COMPB_M

#define PWM_3_CMPB_COMPB_M   0x0000FFFF

◆ PWM_3_CMPB_COMPB_S

#define PWM_3_CMPB_COMPB_S   0

◆ PWM_3_COUNT_COUNT_M

#define PWM_3_COUNT_COUNT_M   0x0000FFFF

◆ PWM_3_COUNT_COUNT_S

#define PWM_3_COUNT_COUNT_S   0

◆ PWM_3_CTL_CMPAUPD

#define PWM_3_CTL_CMPAUPD   0x00000010

◆ PWM_3_CTL_CMPBUPD

#define PWM_3_CTL_CMPBUPD   0x00000020

◆ PWM_3_CTL_DBCTLUPD_GS

#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00

◆ PWM_3_CTL_DBCTLUPD_I

#define PWM_3_CTL_DBCTLUPD_I   0x00000000

◆ PWM_3_CTL_DBCTLUPD_LS

#define PWM_3_CTL_DBCTLUPD_LS   0x00000800

◆ PWM_3_CTL_DBCTLUPD_M

#define PWM_3_CTL_DBCTLUPD_M   0x00000C00

◆ PWM_3_CTL_DBFALLUPD_GS

#define PWM_3_CTL_DBFALLUPD_GS   0x0000C000

◆ PWM_3_CTL_DBFALLUPD_I

#define PWM_3_CTL_DBFALLUPD_I   0x00000000

◆ PWM_3_CTL_DBFALLUPD_LS

#define PWM_3_CTL_DBFALLUPD_LS   0x00008000

◆ PWM_3_CTL_DBFALLUPD_M

#define PWM_3_CTL_DBFALLUPD_M   0x0000C000

◆ PWM_3_CTL_DBRISEUPD_GS

#define PWM_3_CTL_DBRISEUPD_GS   0x00003000

◆ PWM_3_CTL_DBRISEUPD_I

#define PWM_3_CTL_DBRISEUPD_I   0x00000000

◆ PWM_3_CTL_DBRISEUPD_LS

#define PWM_3_CTL_DBRISEUPD_LS   0x00002000

◆ PWM_3_CTL_DBRISEUPD_M

#define PWM_3_CTL_DBRISEUPD_M   0x00003000

◆ PWM_3_CTL_DEBUG

#define PWM_3_CTL_DEBUG   0x00000004

◆ PWM_3_CTL_ENABLE

#define PWM_3_CTL_ENABLE   0x00000001

◆ PWM_3_CTL_FLTSRC

#define PWM_3_CTL_FLTSRC   0x00010000

◆ PWM_3_CTL_GENAUPD_GS

#define PWM_3_CTL_GENAUPD_GS   0x000000C0

◆ PWM_3_CTL_GENAUPD_I

#define PWM_3_CTL_GENAUPD_I   0x00000000

◆ PWM_3_CTL_GENAUPD_LS

#define PWM_3_CTL_GENAUPD_LS   0x00000080

◆ PWM_3_CTL_GENAUPD_M

#define PWM_3_CTL_GENAUPD_M   0x000000C0

◆ PWM_3_CTL_GENBUPD_GS

#define PWM_3_CTL_GENBUPD_GS   0x00000300

◆ PWM_3_CTL_GENBUPD_I

#define PWM_3_CTL_GENBUPD_I   0x00000000

◆ PWM_3_CTL_GENBUPD_LS

#define PWM_3_CTL_GENBUPD_LS   0x00000200

◆ PWM_3_CTL_GENBUPD_M

#define PWM_3_CTL_GENBUPD_M   0x00000300

◆ PWM_3_CTL_LATCH

#define PWM_3_CTL_LATCH   0x00040000

◆ PWM_3_CTL_LOADUPD

#define PWM_3_CTL_LOADUPD   0x00000008

◆ PWM_3_CTL_MINFLTPER

#define PWM_3_CTL_MINFLTPER   0x00020000

◆ PWM_3_CTL_MODE

#define PWM_3_CTL_MODE   0x00000002

◆ PWM_3_DBCTL_ENABLE

#define PWM_3_DBCTL_ENABLE   0x00000001

◆ PWM_3_DBFALL_FALLDELAY_M

#define PWM_3_DBFALL_FALLDELAY_M    0x00000FFF

◆ PWM_3_DBFALL_FALLDELAY_S

#define PWM_3_DBFALL_FALLDELAY_S    0

◆ PWM_3_DBRISE_RISEDELAY_M

#define PWM_3_DBRISE_RISEDELAY_M    0x00000FFF

◆ PWM_3_DBRISE_RISEDELAY_S

#define PWM_3_DBRISE_RISEDELAY_S    0

◆ PWM_3_FLTSRC0_FAULT0

#define PWM_3_FLTSRC0_FAULT0   0x00000001

◆ PWM_3_FLTSRC0_FAULT1

#define PWM_3_FLTSRC0_FAULT1   0x00000002

◆ PWM_3_FLTSRC1_DCMP0

#define PWM_3_FLTSRC1_DCMP0   0x00000001

◆ PWM_3_FLTSRC1_DCMP1

#define PWM_3_FLTSRC1_DCMP1   0x00000002

◆ PWM_3_FLTSRC1_DCMP2

#define PWM_3_FLTSRC1_DCMP2   0x00000004

◆ PWM_3_FLTSRC1_DCMP3

#define PWM_3_FLTSRC1_DCMP3   0x00000008

◆ PWM_3_FLTSRC1_DCMP4

#define PWM_3_FLTSRC1_DCMP4   0x00000010

◆ PWM_3_FLTSRC1_DCMP5

#define PWM_3_FLTSRC1_DCMP5   0x00000020

◆ PWM_3_FLTSRC1_DCMP6

#define PWM_3_FLTSRC1_DCMP6   0x00000040

◆ PWM_3_FLTSRC1_DCMP7

#define PWM_3_FLTSRC1_DCMP7   0x00000080

◆ PWM_3_FLTSTAT0_FAULT0

#define PWM_3_FLTSTAT0_FAULT0   0x00000001

◆ PWM_3_FLTSTAT0_FAULT1

#define PWM_3_FLTSTAT0_FAULT1   0x00000002

◆ PWM_3_FLTSTAT1_DCMP0

#define PWM_3_FLTSTAT1_DCMP0   0x00000001

◆ PWM_3_FLTSTAT1_DCMP1

#define PWM_3_FLTSTAT1_DCMP1   0x00000002

◆ PWM_3_FLTSTAT1_DCMP2

#define PWM_3_FLTSTAT1_DCMP2   0x00000004

◆ PWM_3_FLTSTAT1_DCMP3

#define PWM_3_FLTSTAT1_DCMP3   0x00000008

◆ PWM_3_FLTSTAT1_DCMP4

#define PWM_3_FLTSTAT1_DCMP4   0x00000010

◆ PWM_3_FLTSTAT1_DCMP5

#define PWM_3_FLTSTAT1_DCMP5   0x00000020

◆ PWM_3_FLTSTAT1_DCMP6

#define PWM_3_FLTSTAT1_DCMP6   0x00000040

◆ PWM_3_FLTSTAT1_DCMP7

#define PWM_3_FLTSTAT1_DCMP7   0x00000080

◆ PWM_3_GENA_ACTCMPAD_INV

#define PWM_3_GENA_ACTCMPAD_INV   0x00000040

◆ PWM_3_GENA_ACTCMPAD_M

#define PWM_3_GENA_ACTCMPAD_M   0x000000C0

◆ PWM_3_GENA_ACTCMPAD_NONE

#define PWM_3_GENA_ACTCMPAD_NONE    0x00000000

◆ PWM_3_GENA_ACTCMPAD_ONE

#define PWM_3_GENA_ACTCMPAD_ONE   0x000000C0

◆ PWM_3_GENA_ACTCMPAD_ZERO

#define PWM_3_GENA_ACTCMPAD_ZERO    0x00000080

◆ PWM_3_GENA_ACTCMPAU_INV

#define PWM_3_GENA_ACTCMPAU_INV   0x00000010

◆ PWM_3_GENA_ACTCMPAU_M

#define PWM_3_GENA_ACTCMPAU_M   0x00000030

◆ PWM_3_GENA_ACTCMPAU_NONE

#define PWM_3_GENA_ACTCMPAU_NONE    0x00000000

◆ PWM_3_GENA_ACTCMPAU_ONE

#define PWM_3_GENA_ACTCMPAU_ONE   0x00000030

◆ PWM_3_GENA_ACTCMPAU_ZERO

#define PWM_3_GENA_ACTCMPAU_ZERO    0x00000020

◆ PWM_3_GENA_ACTCMPBD_INV

#define PWM_3_GENA_ACTCMPBD_INV   0x00000400

◆ PWM_3_GENA_ACTCMPBD_M

#define PWM_3_GENA_ACTCMPBD_M   0x00000C00

◆ PWM_3_GENA_ACTCMPBD_NONE

#define PWM_3_GENA_ACTCMPBD_NONE    0x00000000

◆ PWM_3_GENA_ACTCMPBD_ONE

#define PWM_3_GENA_ACTCMPBD_ONE   0x00000C00

◆ PWM_3_GENA_ACTCMPBD_ZERO

#define PWM_3_GENA_ACTCMPBD_ZERO    0x00000800

◆ PWM_3_GENA_ACTCMPBU_INV

#define PWM_3_GENA_ACTCMPBU_INV   0x00000100

◆ PWM_3_GENA_ACTCMPBU_M

#define PWM_3_GENA_ACTCMPBU_M   0x00000300

◆ PWM_3_GENA_ACTCMPBU_NONE

#define PWM_3_GENA_ACTCMPBU_NONE    0x00000000

◆ PWM_3_GENA_ACTCMPBU_ONE

#define PWM_3_GENA_ACTCMPBU_ONE   0x00000300

◆ PWM_3_GENA_ACTCMPBU_ZERO

#define PWM_3_GENA_ACTCMPBU_ZERO    0x00000200

◆ PWM_3_GENA_ACTLOAD_INV

#define PWM_3_GENA_ACTLOAD_INV   0x00000004

◆ PWM_3_GENA_ACTLOAD_M

#define PWM_3_GENA_ACTLOAD_M   0x0000000C

◆ PWM_3_GENA_ACTLOAD_NONE

#define PWM_3_GENA_ACTLOAD_NONE   0x00000000

◆ PWM_3_GENA_ACTLOAD_ONE

#define PWM_3_GENA_ACTLOAD_ONE   0x0000000C

◆ PWM_3_GENA_ACTLOAD_ZERO

#define PWM_3_GENA_ACTLOAD_ZERO   0x00000008

◆ PWM_3_GENA_ACTZERO_INV

#define PWM_3_GENA_ACTZERO_INV   0x00000001

◆ PWM_3_GENA_ACTZERO_M

#define PWM_3_GENA_ACTZERO_M   0x00000003

◆ PWM_3_GENA_ACTZERO_NONE

#define PWM_3_GENA_ACTZERO_NONE   0x00000000

◆ PWM_3_GENA_ACTZERO_ONE

#define PWM_3_GENA_ACTZERO_ONE   0x00000003

◆ PWM_3_GENA_ACTZERO_ZERO

#define PWM_3_GENA_ACTZERO_ZERO   0x00000002

◆ PWM_3_GENB_ACTCMPAD_INV

#define PWM_3_GENB_ACTCMPAD_INV   0x00000040

◆ PWM_3_GENB_ACTCMPAD_M

#define PWM_3_GENB_ACTCMPAD_M   0x000000C0

◆ PWM_3_GENB_ACTCMPAD_NONE

#define PWM_3_GENB_ACTCMPAD_NONE    0x00000000

◆ PWM_3_GENB_ACTCMPAD_ONE

#define PWM_3_GENB_ACTCMPAD_ONE   0x000000C0

◆ PWM_3_GENB_ACTCMPAD_ZERO

#define PWM_3_GENB_ACTCMPAD_ZERO    0x00000080

◆ PWM_3_GENB_ACTCMPAU_INV

#define PWM_3_GENB_ACTCMPAU_INV   0x00000010

◆ PWM_3_GENB_ACTCMPAU_M

#define PWM_3_GENB_ACTCMPAU_M   0x00000030

◆ PWM_3_GENB_ACTCMPAU_NONE

#define PWM_3_GENB_ACTCMPAU_NONE    0x00000000

◆ PWM_3_GENB_ACTCMPAU_ONE

#define PWM_3_GENB_ACTCMPAU_ONE   0x00000030

◆ PWM_3_GENB_ACTCMPAU_ZERO

#define PWM_3_GENB_ACTCMPAU_ZERO    0x00000020

◆ PWM_3_GENB_ACTCMPBD_INV

#define PWM_3_GENB_ACTCMPBD_INV   0x00000400

◆ PWM_3_GENB_ACTCMPBD_M

#define PWM_3_GENB_ACTCMPBD_M   0x00000C00

◆ PWM_3_GENB_ACTCMPBD_NONE

#define PWM_3_GENB_ACTCMPBD_NONE    0x00000000

◆ PWM_3_GENB_ACTCMPBD_ONE

#define PWM_3_GENB_ACTCMPBD_ONE   0x00000C00

◆ PWM_3_GENB_ACTCMPBD_ZERO

#define PWM_3_GENB_ACTCMPBD_ZERO    0x00000800

◆ PWM_3_GENB_ACTCMPBU_INV

#define PWM_3_GENB_ACTCMPBU_INV   0x00000100

◆ PWM_3_GENB_ACTCMPBU_M

#define PWM_3_GENB_ACTCMPBU_M   0x00000300

◆ PWM_3_GENB_ACTCMPBU_NONE

#define PWM_3_GENB_ACTCMPBU_NONE    0x00000000

◆ PWM_3_GENB_ACTCMPBU_ONE

#define PWM_3_GENB_ACTCMPBU_ONE   0x00000300

◆ PWM_3_GENB_ACTCMPBU_ZERO

#define PWM_3_GENB_ACTCMPBU_ZERO    0x00000200

◆ PWM_3_GENB_ACTLOAD_INV

#define PWM_3_GENB_ACTLOAD_INV   0x00000004

◆ PWM_3_GENB_ACTLOAD_M

#define PWM_3_GENB_ACTLOAD_M   0x0000000C

◆ PWM_3_GENB_ACTLOAD_NONE

#define PWM_3_GENB_ACTLOAD_NONE   0x00000000

◆ PWM_3_GENB_ACTLOAD_ONE

#define PWM_3_GENB_ACTLOAD_ONE   0x0000000C

◆ PWM_3_GENB_ACTLOAD_ZERO

#define PWM_3_GENB_ACTLOAD_ZERO   0x00000008

◆ PWM_3_GENB_ACTZERO_INV

#define PWM_3_GENB_ACTZERO_INV   0x00000001

◆ PWM_3_GENB_ACTZERO_M

#define PWM_3_GENB_ACTZERO_M   0x00000003

◆ PWM_3_GENB_ACTZERO_NONE

#define PWM_3_GENB_ACTZERO_NONE   0x00000000

◆ PWM_3_GENB_ACTZERO_ONE

#define PWM_3_GENB_ACTZERO_ONE   0x00000003

◆ PWM_3_GENB_ACTZERO_ZERO

#define PWM_3_GENB_ACTZERO_ZERO   0x00000002

◆ PWM_3_INTEN_INTCMPAD

#define PWM_3_INTEN_INTCMPAD   0x00000008

◆ PWM_3_INTEN_INTCMPAU

#define PWM_3_INTEN_INTCMPAU   0x00000004

◆ PWM_3_INTEN_INTCMPBD

#define PWM_3_INTEN_INTCMPBD   0x00000020

◆ PWM_3_INTEN_INTCMPBU

#define PWM_3_INTEN_INTCMPBU   0x00000010

◆ PWM_3_INTEN_INTCNTLOAD

#define PWM_3_INTEN_INTCNTLOAD   0x00000002

◆ PWM_3_INTEN_INTCNTZERO

#define PWM_3_INTEN_INTCNTZERO   0x00000001

◆ PWM_3_INTEN_TRCMPAD

#define PWM_3_INTEN_TRCMPAD   0x00000800

◆ PWM_3_INTEN_TRCMPAU

#define PWM_3_INTEN_TRCMPAU   0x00000400

◆ PWM_3_INTEN_TRCMPBD

#define PWM_3_INTEN_TRCMPBD   0x00002000

◆ PWM_3_INTEN_TRCMPBU

#define PWM_3_INTEN_TRCMPBU   0x00001000

◆ PWM_3_INTEN_TRCNTLOAD

#define PWM_3_INTEN_TRCNTLOAD   0x00000200

◆ PWM_3_INTEN_TRCNTZERO

#define PWM_3_INTEN_TRCNTZERO   0x00000100

◆ PWM_3_ISC_INTCMPAD

#define PWM_3_ISC_INTCMPAD   0x00000008

◆ PWM_3_ISC_INTCMPAU

#define PWM_3_ISC_INTCMPAU   0x00000004

◆ PWM_3_ISC_INTCMPBD

#define PWM_3_ISC_INTCMPBD   0x00000020

◆ PWM_3_ISC_INTCMPBU

#define PWM_3_ISC_INTCMPBU   0x00000010

◆ PWM_3_ISC_INTCNTLOAD

#define PWM_3_ISC_INTCNTLOAD   0x00000002

◆ PWM_3_ISC_INTCNTZERO

#define PWM_3_ISC_INTCNTZERO   0x00000001

◆ PWM_3_LOAD_LOAD_M

#define PWM_3_LOAD_LOAD_M   0x0000FFFF

◆ PWM_3_LOAD_LOAD_S

#define PWM_3_LOAD_LOAD_S   0

◆ PWM_3_MINFLTPER_MFP_M

#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF

◆ PWM_3_MINFLTPER_MFP_S

#define PWM_3_MINFLTPER_MFP_S   0

◆ PWM_3_RIS_INTCMPAD

#define PWM_3_RIS_INTCMPAD   0x00000008

◆ PWM_3_RIS_INTCMPAU

#define PWM_3_RIS_INTCMPAU   0x00000004

◆ PWM_3_RIS_INTCMPBD

#define PWM_3_RIS_INTCMPBD   0x00000020

◆ PWM_3_RIS_INTCMPBU

#define PWM_3_RIS_INTCMPBU   0x00000010

◆ PWM_3_RIS_INTCNTLOAD

#define PWM_3_RIS_INTCNTLOAD   0x00000002

◆ PWM_3_RIS_INTCNTZERO

#define PWM_3_RIS_INTCNTZERO   0x00000001

◆ PWM_CTL_GLOBALSYNC0

#define PWM_CTL_GLOBALSYNC0   0x00000001

◆ PWM_CTL_GLOBALSYNC1

#define PWM_CTL_GLOBALSYNC1   0x00000002

◆ PWM_CTL_GLOBALSYNC2

#define PWM_CTL_GLOBALSYNC2   0x00000004

◆ PWM_CTL_GLOBALSYNC3

#define PWM_CTL_GLOBALSYNC3   0x00000008

◆ PWM_ENABLE_PWM0EN

#define PWM_ENABLE_PWM0EN   0x00000001

◆ PWM_ENABLE_PWM1EN

#define PWM_ENABLE_PWM1EN   0x00000002

◆ PWM_ENABLE_PWM2EN

#define PWM_ENABLE_PWM2EN   0x00000004

◆ PWM_ENABLE_PWM3EN

#define PWM_ENABLE_PWM3EN   0x00000008

◆ PWM_ENABLE_PWM4EN

#define PWM_ENABLE_PWM4EN   0x00000010

◆ PWM_ENABLE_PWM5EN

#define PWM_ENABLE_PWM5EN   0x00000020

◆ PWM_ENABLE_PWM6EN

#define PWM_ENABLE_PWM6EN   0x00000040

◆ PWM_ENABLE_PWM7EN

#define PWM_ENABLE_PWM7EN   0x00000080

◆ PWM_ENUPD_ENUPD0_GSYNC

#define PWM_ENUPD_ENUPD0_GSYNC   0x00000003

◆ PWM_ENUPD_ENUPD0_IMM

#define PWM_ENUPD_ENUPD0_IMM   0x00000000

◆ PWM_ENUPD_ENUPD0_LSYNC

#define PWM_ENUPD_ENUPD0_LSYNC   0x00000002

◆ PWM_ENUPD_ENUPD0_M

#define PWM_ENUPD_ENUPD0_M   0x00000003

◆ PWM_ENUPD_ENUPD1_GSYNC

#define PWM_ENUPD_ENUPD1_GSYNC   0x0000000C

◆ PWM_ENUPD_ENUPD1_IMM

#define PWM_ENUPD_ENUPD1_IMM   0x00000000

◆ PWM_ENUPD_ENUPD1_LSYNC

#define PWM_ENUPD_ENUPD1_LSYNC   0x00000008

◆ PWM_ENUPD_ENUPD1_M

#define PWM_ENUPD_ENUPD1_M   0x0000000C

◆ PWM_ENUPD_ENUPD2_GSYNC

#define PWM_ENUPD_ENUPD2_GSYNC   0x00000030

◆ PWM_ENUPD_ENUPD2_IMM

#define PWM_ENUPD_ENUPD2_IMM   0x00000000

◆ PWM_ENUPD_ENUPD2_LSYNC

#define PWM_ENUPD_ENUPD2_LSYNC   0x00000020

◆ PWM_ENUPD_ENUPD2_M

#define PWM_ENUPD_ENUPD2_M   0x00000030

◆ PWM_ENUPD_ENUPD3_GSYNC

#define PWM_ENUPD_ENUPD3_GSYNC   0x000000C0

◆ PWM_ENUPD_ENUPD3_IMM

#define PWM_ENUPD_ENUPD3_IMM   0x00000000

◆ PWM_ENUPD_ENUPD3_LSYNC

#define PWM_ENUPD_ENUPD3_LSYNC   0x00000080

◆ PWM_ENUPD_ENUPD3_M

#define PWM_ENUPD_ENUPD3_M   0x000000C0

◆ PWM_ENUPD_ENUPD4_GSYNC

#define PWM_ENUPD_ENUPD4_GSYNC   0x00000300

◆ PWM_ENUPD_ENUPD4_IMM

#define PWM_ENUPD_ENUPD4_IMM   0x00000000

◆ PWM_ENUPD_ENUPD4_LSYNC

#define PWM_ENUPD_ENUPD4_LSYNC   0x00000200

◆ PWM_ENUPD_ENUPD4_M

#define PWM_ENUPD_ENUPD4_M   0x00000300

◆ PWM_ENUPD_ENUPD5_GSYNC

#define PWM_ENUPD_ENUPD5_GSYNC   0x00000C00

◆ PWM_ENUPD_ENUPD5_IMM

#define PWM_ENUPD_ENUPD5_IMM   0x00000000

◆ PWM_ENUPD_ENUPD5_LSYNC

#define PWM_ENUPD_ENUPD5_LSYNC   0x00000800

◆ PWM_ENUPD_ENUPD5_M

#define PWM_ENUPD_ENUPD5_M   0x00000C00

◆ PWM_ENUPD_ENUPD6_GSYNC

#define PWM_ENUPD_ENUPD6_GSYNC   0x00003000

◆ PWM_ENUPD_ENUPD6_IMM

#define PWM_ENUPD_ENUPD6_IMM   0x00000000

◆ PWM_ENUPD_ENUPD6_LSYNC

#define PWM_ENUPD_ENUPD6_LSYNC   0x00002000

◆ PWM_ENUPD_ENUPD6_M

#define PWM_ENUPD_ENUPD6_M   0x00003000

◆ PWM_ENUPD_ENUPD7_GSYNC

#define PWM_ENUPD_ENUPD7_GSYNC   0x0000C000

◆ PWM_ENUPD_ENUPD7_IMM

#define PWM_ENUPD_ENUPD7_IMM   0x00000000

◆ PWM_ENUPD_ENUPD7_LSYNC

#define PWM_ENUPD_ENUPD7_LSYNC   0x00008000

◆ PWM_ENUPD_ENUPD7_M

#define PWM_ENUPD_ENUPD7_M   0x0000C000

◆ PWM_FAULT_FAULT0

#define PWM_FAULT_FAULT0   0x00000001

◆ PWM_FAULT_FAULT1

#define PWM_FAULT_FAULT1   0x00000002

◆ PWM_FAULT_FAULT2

#define PWM_FAULT_FAULT2   0x00000004

◆ PWM_FAULT_FAULT3

#define PWM_FAULT_FAULT3   0x00000008

◆ PWM_FAULT_FAULT4

#define PWM_FAULT_FAULT4   0x00000010

◆ PWM_FAULT_FAULT5

#define PWM_FAULT_FAULT5   0x00000020

◆ PWM_FAULT_FAULT6

#define PWM_FAULT_FAULT6   0x00000040

◆ PWM_FAULT_FAULT7

#define PWM_FAULT_FAULT7   0x00000080

◆ PWM_FAULTVAL_PWM0

#define PWM_FAULTVAL_PWM0   0x00000001

◆ PWM_FAULTVAL_PWM1

#define PWM_FAULTVAL_PWM1   0x00000002

◆ PWM_FAULTVAL_PWM2

#define PWM_FAULTVAL_PWM2   0x00000004

◆ PWM_FAULTVAL_PWM3

#define PWM_FAULTVAL_PWM3   0x00000008

◆ PWM_FAULTVAL_PWM4

#define PWM_FAULTVAL_PWM4   0x00000010

◆ PWM_FAULTVAL_PWM5

#define PWM_FAULTVAL_PWM5   0x00000020

◆ PWM_FAULTVAL_PWM6

#define PWM_FAULTVAL_PWM6   0x00000040

◆ PWM_FAULTVAL_PWM7

#define PWM_FAULTVAL_PWM7   0x00000080

◆ PWM_INTEN_INTFAULT0

#define PWM_INTEN_INTFAULT0   0x00010000

◆ PWM_INTEN_INTFAULT1

#define PWM_INTEN_INTFAULT1   0x00020000

◆ PWM_INTEN_INTPWM0

#define PWM_INTEN_INTPWM0   0x00000001

◆ PWM_INTEN_INTPWM1

#define PWM_INTEN_INTPWM1   0x00000002

◆ PWM_INTEN_INTPWM2

#define PWM_INTEN_INTPWM2   0x00000004

◆ PWM_INTEN_INTPWM3

#define PWM_INTEN_INTPWM3   0x00000008

◆ PWM_INVERT_PWM0INV

#define PWM_INVERT_PWM0INV   0x00000001

◆ PWM_INVERT_PWM1INV

#define PWM_INVERT_PWM1INV   0x00000002

◆ PWM_INVERT_PWM2INV

#define PWM_INVERT_PWM2INV   0x00000004

◆ PWM_INVERT_PWM3INV

#define PWM_INVERT_PWM3INV   0x00000008

◆ PWM_INVERT_PWM4INV

#define PWM_INVERT_PWM4INV   0x00000010

◆ PWM_INVERT_PWM5INV

#define PWM_INVERT_PWM5INV   0x00000020

◆ PWM_INVERT_PWM6INV

#define PWM_INVERT_PWM6INV   0x00000040

◆ PWM_INVERT_PWM7INV

#define PWM_INVERT_PWM7INV   0x00000080

◆ PWM_ISC_INTFAULT0

#define PWM_ISC_INTFAULT0   0x00010000

◆ PWM_ISC_INTFAULT1

#define PWM_ISC_INTFAULT1   0x00020000

◆ PWM_ISC_INTPWM0

#define PWM_ISC_INTPWM0   0x00000001

◆ PWM_ISC_INTPWM1

#define PWM_ISC_INTPWM1   0x00000002

◆ PWM_ISC_INTPWM2

#define PWM_ISC_INTPWM2   0x00000004

◆ PWM_ISC_INTPWM3

#define PWM_ISC_INTPWM3   0x00000008

◆ PWM_PP_EFAULT

#define PWM_PP_EFAULT   0x00000200

◆ PWM_PP_ESYNC

#define PWM_PP_ESYNC   0x00000100

◆ PWM_PP_FCNT_M

#define PWM_PP_FCNT_M   0x000000F0

◆ PWM_PP_FCNT_S

#define PWM_PP_FCNT_S   4

◆ PWM_PP_GCNT_M

#define PWM_PP_GCNT_M   0x0000000F

◆ PWM_PP_GCNT_S

#define PWM_PP_GCNT_S   0

◆ PWM_PP_ONE

#define PWM_PP_ONE   0x00000400

◆ PWM_RIS_INTFAULT0

#define PWM_RIS_INTFAULT0   0x00010000

◆ PWM_RIS_INTFAULT1

#define PWM_RIS_INTFAULT1   0x00020000

◆ PWM_RIS_INTPWM0

#define PWM_RIS_INTPWM0   0x00000001

◆ PWM_RIS_INTPWM1

#define PWM_RIS_INTPWM1   0x00000002

◆ PWM_RIS_INTPWM2

#define PWM_RIS_INTPWM2   0x00000004

◆ PWM_RIS_INTPWM3

#define PWM_RIS_INTPWM3   0x00000008

◆ PWM_STATUS_FAULT0

#define PWM_STATUS_FAULT0   0x00000001

◆ PWM_STATUS_FAULT1

#define PWM_STATUS_FAULT1   0x00000002

◆ PWM_SYNC_SYNC0

#define PWM_SYNC_SYNC0   0x00000001

◆ PWM_SYNC_SYNC1

#define PWM_SYNC_SYNC1   0x00000002

◆ PWM_SYNC_SYNC2

#define PWM_SYNC_SYNC2   0x00000004

◆ PWM_SYNC_SYNC3

#define PWM_SYNC_SYNC3   0x00000008

◆ QEI0_COUNT_R

#define QEI0_COUNT_R   (*((volatile u32 *)0x4002C018))

◆ QEI0_CTL_R

#define QEI0_CTL_R   (*((volatile u32 *)0x4002C000))

◆ QEI0_INTEN_R

#define QEI0_INTEN_R   (*((volatile u32 *)0x4002C020))

◆ QEI0_ISC_R

#define QEI0_ISC_R   (*((volatile u32 *)0x4002C028))

◆ QEI0_LOAD_R

#define QEI0_LOAD_R   (*((volatile u32 *)0x4002C010))

◆ QEI0_MAXPOS_R

#define QEI0_MAXPOS_R   (*((volatile u32 *)0x4002C00C))

◆ QEI0_POS_R

#define QEI0_POS_R   (*((volatile u32 *)0x4002C008))

◆ QEI0_RIS_R

#define QEI0_RIS_R   (*((volatile u32 *)0x4002C024))

◆ QEI0_SPEED_R

#define QEI0_SPEED_R   (*((volatile u32 *)0x4002C01C))

◆ QEI0_STAT_R

#define QEI0_STAT_R   (*((volatile u32 *)0x4002C004))

◆ QEI0_TIME_R

#define QEI0_TIME_R   (*((volatile u32 *)0x4002C014))

◆ QEI1_COUNT_R

#define QEI1_COUNT_R   (*((volatile u32 *)0x4002D018))

◆ QEI1_CTL_R

#define QEI1_CTL_R   (*((volatile u32 *)0x4002D000))

◆ QEI1_INTEN_R

#define QEI1_INTEN_R   (*((volatile u32 *)0x4002D020))

◆ QEI1_ISC_R

#define QEI1_ISC_R   (*((volatile u32 *)0x4002D028))

◆ QEI1_LOAD_R

#define QEI1_LOAD_R   (*((volatile u32 *)0x4002D010))

◆ QEI1_MAXPOS_R

#define QEI1_MAXPOS_R   (*((volatile u32 *)0x4002D00C))

◆ QEI1_POS_R

#define QEI1_POS_R   (*((volatile u32 *)0x4002D008))

◆ QEI1_RIS_R

#define QEI1_RIS_R   (*((volatile u32 *)0x4002D024))

◆ QEI1_SPEED_R

#define QEI1_SPEED_R   (*((volatile u32 *)0x4002D01C))

◆ QEI1_STAT_R

#define QEI1_STAT_R   (*((volatile u32 *)0x4002D004))

◆ QEI1_TIME_R

#define QEI1_TIME_R   (*((volatile u32 *)0x4002D014))

◆ QEI_COUNT_M

#define QEI_COUNT_M   0xFFFFFFFF

◆ QEI_COUNT_S

#define QEI_COUNT_S   0

◆ QEI_CTL_CAPMODE

#define QEI_CTL_CAPMODE   0x00000008

◆ QEI_CTL_ENABLE

#define QEI_CTL_ENABLE   0x00000001

◆ QEI_CTL_FILTCNT_M

#define QEI_CTL_FILTCNT_M   0x000F0000

◆ QEI_CTL_FILTCNT_S

#define QEI_CTL_FILTCNT_S   16

◆ QEI_CTL_FILTEN

#define QEI_CTL_FILTEN   0x00002000

◆ QEI_CTL_INVA

#define QEI_CTL_INVA   0x00000200

◆ QEI_CTL_INVB

#define QEI_CTL_INVB   0x00000400

◆ QEI_CTL_INVI

#define QEI_CTL_INVI   0x00000800

◆ QEI_CTL_RESMODE

#define QEI_CTL_RESMODE   0x00000010

◆ QEI_CTL_SIGMODE

#define QEI_CTL_SIGMODE   0x00000004

◆ QEI_CTL_STALLEN

#define QEI_CTL_STALLEN   0x00001000

◆ QEI_CTL_SWAP

#define QEI_CTL_SWAP   0x00000002

◆ QEI_CTL_VELDIV_1

#define QEI_CTL_VELDIV_1   0x00000000

◆ QEI_CTL_VELDIV_128

#define QEI_CTL_VELDIV_128   0x000001C0

◆ QEI_CTL_VELDIV_16

#define QEI_CTL_VELDIV_16   0x00000100

◆ QEI_CTL_VELDIV_2

#define QEI_CTL_VELDIV_2   0x00000040

◆ QEI_CTL_VELDIV_32

#define QEI_CTL_VELDIV_32   0x00000140

◆ QEI_CTL_VELDIV_4

#define QEI_CTL_VELDIV_4   0x00000080

◆ QEI_CTL_VELDIV_64

#define QEI_CTL_VELDIV_64   0x00000180

◆ QEI_CTL_VELDIV_8

#define QEI_CTL_VELDIV_8   0x000000C0

◆ QEI_CTL_VELDIV_M

#define QEI_CTL_VELDIV_M   0x000001C0

◆ QEI_CTL_VELEN

#define QEI_CTL_VELEN   0x00000020

◆ QEI_INTEN_DIR

#define QEI_INTEN_DIR   0x00000004

◆ QEI_INTEN_ERROR

#define QEI_INTEN_ERROR   0x00000008

◆ QEI_INTEN_INDEX

#define QEI_INTEN_INDEX   0x00000001

◆ QEI_INTEN_TIMER

#define QEI_INTEN_TIMER   0x00000002

◆ QEI_ISC_DIR

#define QEI_ISC_DIR   0x00000004

◆ QEI_ISC_ERROR

#define QEI_ISC_ERROR   0x00000008

◆ QEI_ISC_INDEX

#define QEI_ISC_INDEX   0x00000001

◆ QEI_ISC_TIMER

#define QEI_ISC_TIMER   0x00000002

◆ QEI_LOAD_M

#define QEI_LOAD_M   0xFFFFFFFF

◆ QEI_LOAD_S

#define QEI_LOAD_S   0

◆ QEI_MAXPOS_M

#define QEI_MAXPOS_M   0xFFFFFFFF

◆ QEI_MAXPOS_S

#define QEI_MAXPOS_S   0

◆ QEI_POS_M

#define QEI_POS_M   0xFFFFFFFF

◆ QEI_POS_S

#define QEI_POS_S   0

◆ QEI_RIS_DIR

#define QEI_RIS_DIR   0x00000004

◆ QEI_RIS_ERROR

#define QEI_RIS_ERROR   0x00000008

◆ QEI_RIS_INDEX

#define QEI_RIS_INDEX   0x00000001

◆ QEI_RIS_TIMER

#define QEI_RIS_TIMER   0x00000002

◆ QEI_SPEED_M

#define QEI_SPEED_M   0xFFFFFFFF

◆ QEI_SPEED_S

#define QEI_SPEED_S   0

◆ QEI_STAT_DIRECTION

#define QEI_STAT_DIRECTION   0x00000002

◆ QEI_STAT_ERROR

#define QEI_STAT_ERROR   0x00000001

◆ QEI_TIME_M

#define QEI_TIME_M   0xFFFFFFFF

◆ QEI_TIME_S

#define QEI_TIME_S   0

◆ SSI0_CC_R

#define SSI0_CC_R   (*((volatile u32 *)0x40008FC8))

◆ SSI0_CPSR_R

#define SSI0_CPSR_R   (*((volatile u32 *)0x40008010))

◆ SSI0_CR0_R

#define SSI0_CR0_R   (*((volatile u32 *)0x40008000))

◆ SSI0_CR1_R

#define SSI0_CR1_R   (*((volatile u32 *)0x40008004))

◆ SSI0_DMACTL_R

#define SSI0_DMACTL_R   (*((volatile u32 *)0x40008024))

◆ SSI0_DR_R

#define SSI0_DR_R   (*((volatile u32 *)0x40008008))

◆ SSI0_ICR_R

#define SSI0_ICR_R   (*((volatile u32 *)0x40008020))

◆ SSI0_IM_R

#define SSI0_IM_R   (*((volatile u32 *)0x40008014))

◆ SSI0_MIS_R

#define SSI0_MIS_R   (*((volatile u32 *)0x4000801C))

◆ SSI0_RIS_R

#define SSI0_RIS_R   (*((volatile u32 *)0x40008018))

◆ SSI0_SR_R

#define SSI0_SR_R   (*((volatile u32 *)0x4000800C))

◆ SSI1_CC_R

#define SSI1_CC_R   (*((volatile u32 *)0x40009FC8))

◆ SSI1_CPSR_R

#define SSI1_CPSR_R   (*((volatile u32 *)0x40009010))

◆ SSI1_CR0_R

#define SSI1_CR0_R   (*((volatile u32 *)0x40009000))

◆ SSI1_CR1_R

#define SSI1_CR1_R   (*((volatile u32 *)0x40009004))

◆ SSI1_DMACTL_R

#define SSI1_DMACTL_R   (*((volatile u32 *)0x40009024))

◆ SSI1_DR_R

#define SSI1_DR_R   (*((volatile u32 *)0x40009008))

◆ SSI1_ICR_R

#define SSI1_ICR_R   (*((volatile u32 *)0x40009020))

◆ SSI1_IM_R

#define SSI1_IM_R   (*((volatile u32 *)0x40009014))

◆ SSI1_MIS_R

#define SSI1_MIS_R   (*((volatile u32 *)0x4000901C))

◆ SSI1_RIS_R

#define SSI1_RIS_R   (*((volatile u32 *)0x40009018))

◆ SSI1_SR_R

#define SSI1_SR_R   (*((volatile u32 *)0x4000900C))

◆ SSI2_CC_R

#define SSI2_CC_R   (*((volatile u32 *)0x4000AFC8))

◆ SSI2_CPSR_R

#define SSI2_CPSR_R   (*((volatile u32 *)0x4000A010))

◆ SSI2_CR0_R

#define SSI2_CR0_R   (*((volatile u32 *)0x4000A000))

◆ SSI2_CR1_R

#define SSI2_CR1_R   (*((volatile u32 *)0x4000A004))

◆ SSI2_DMACTL_R

#define SSI2_DMACTL_R   (*((volatile u32 *)0x4000A024))

◆ SSI2_DR_R

#define SSI2_DR_R   (*((volatile u32 *)0x4000A008))

◆ SSI2_ICR_R

#define SSI2_ICR_R   (*((volatile u32 *)0x4000A020))

◆ SSI2_IM_R

#define SSI2_IM_R   (*((volatile u32 *)0x4000A014))

◆ SSI2_MIS_R

#define SSI2_MIS_R   (*((volatile u32 *)0x4000A01C))

◆ SSI2_RIS_R

#define SSI2_RIS_R   (*((volatile u32 *)0x4000A018))

◆ SSI2_SR_R

#define SSI2_SR_R   (*((volatile u32 *)0x4000A00C))

◆ SSI3_CC_R

#define SSI3_CC_R   (*((volatile u32 *)0x4000BFC8))

◆ SSI3_CPSR_R

#define SSI3_CPSR_R   (*((volatile u32 *)0x4000B010))

◆ SSI3_CR0_R

#define SSI3_CR0_R   (*((volatile u32 *)0x4000B000))

◆ SSI3_CR1_R

#define SSI3_CR1_R   (*((volatile u32 *)0x4000B004))

◆ SSI3_DMACTL_R

#define SSI3_DMACTL_R   (*((volatile u32 *)0x4000B024))

◆ SSI3_DR_R

#define SSI3_DR_R   (*((volatile u32 *)0x4000B008))

◆ SSI3_ICR_R

#define SSI3_ICR_R   (*((volatile u32 *)0x4000B020))

◆ SSI3_IM_R

#define SSI3_IM_R   (*((volatile u32 *)0x4000B014))

◆ SSI3_MIS_R

#define SSI3_MIS_R   (*((volatile u32 *)0x4000B01C))

◆ SSI3_RIS_R

#define SSI3_RIS_R   (*((volatile u32 *)0x4000B018))

◆ SSI3_SR_R

#define SSI3_SR_R   (*((volatile u32 *)0x4000B00C))

◆ SSI_CC_CS_M

#define SSI_CC_CS_M   0x0000000F

◆ SSI_CC_CS_PIOSC

#define SSI_CC_CS_PIOSC   0x00000005

◆ SSI_CC_CS_SYSPLL

#define SSI_CC_CS_SYSPLL   0x00000000

◆ SSI_CPSR_CPSDVSR_M

#define SSI_CPSR_CPSDVSR_M   0x000000FF

◆ SSI_CPSR_CPSDVSR_S

#define SSI_CPSR_CPSDVSR_S   0

◆ SSI_CR0_DSS_10

#define SSI_CR0_DSS_10   0x00000009

◆ SSI_CR0_DSS_11

#define SSI_CR0_DSS_11   0x0000000A

◆ SSI_CR0_DSS_12

#define SSI_CR0_DSS_12   0x0000000B

◆ SSI_CR0_DSS_13

#define SSI_CR0_DSS_13   0x0000000C

◆ SSI_CR0_DSS_14

#define SSI_CR0_DSS_14   0x0000000D

◆ SSI_CR0_DSS_15

#define SSI_CR0_DSS_15   0x0000000E

◆ SSI_CR0_DSS_16

#define SSI_CR0_DSS_16   0x0000000F

◆ SSI_CR0_DSS_4

#define SSI_CR0_DSS_4   0x00000003

◆ SSI_CR0_DSS_5

#define SSI_CR0_DSS_5   0x00000004

◆ SSI_CR0_DSS_6

#define SSI_CR0_DSS_6   0x00000005

◆ SSI_CR0_DSS_7

#define SSI_CR0_DSS_7   0x00000006

◆ SSI_CR0_DSS_8

#define SSI_CR0_DSS_8   0x00000007

◆ SSI_CR0_DSS_9

#define SSI_CR0_DSS_9   0x00000008

◆ SSI_CR0_DSS_M

#define SSI_CR0_DSS_M   0x0000000F

◆ SSI_CR0_FRF_M

#define SSI_CR0_FRF_M   0x00000030

◆ SSI_CR0_FRF_MOTO

#define SSI_CR0_FRF_MOTO   0x00000000

◆ SSI_CR0_FRF_NMW

#define SSI_CR0_FRF_NMW   0x00000020

◆ SSI_CR0_FRF_TI

#define SSI_CR0_FRF_TI   0x00000010

◆ SSI_CR0_SCR_M

#define SSI_CR0_SCR_M   0x0000FF00

◆ SSI_CR0_SCR_S

#define SSI_CR0_SCR_S   8

◆ SSI_CR0_SPH

#define SSI_CR0_SPH   0x00000080

◆ SSI_CR0_SPO

#define SSI_CR0_SPO   0x00000040

◆ SSI_CR1_EOT

#define SSI_CR1_EOT   0x00000010

◆ SSI_CR1_LBM

#define SSI_CR1_LBM   0x00000001

◆ SSI_CR1_MS

#define SSI_CR1_MS   0x00000004

◆ SSI_CR1_SSE

#define SSI_CR1_SSE   0x00000002

◆ SSI_DMACTL_RXDMAE

#define SSI_DMACTL_RXDMAE   0x00000001

◆ SSI_DMACTL_TXDMAE

#define SSI_DMACTL_TXDMAE   0x00000002

◆ SSI_DR_DATA_M

#define SSI_DR_DATA_M   0x0000FFFF

◆ SSI_DR_DATA_S

#define SSI_DR_DATA_S   0

◆ SSI_ICR_RORIC

#define SSI_ICR_RORIC   0x00000001

◆ SSI_ICR_RTIC

#define SSI_ICR_RTIC   0x00000002

◆ SSI_IM_RORIM

#define SSI_IM_RORIM   0x00000001

◆ SSI_IM_RTIM

#define SSI_IM_RTIM   0x00000002

◆ SSI_IM_RXIM

#define SSI_IM_RXIM   0x00000004

◆ SSI_IM_TXIM

#define SSI_IM_TXIM   0x00000008

◆ SSI_MIS_RORMIS

#define SSI_MIS_RORMIS   0x00000001

◆ SSI_MIS_RTMIS

#define SSI_MIS_RTMIS   0x00000002

◆ SSI_MIS_RXMIS

#define SSI_MIS_RXMIS   0x00000004

◆ SSI_MIS_TXMIS

#define SSI_MIS_TXMIS   0x00000008

◆ SSI_RIS_RORRIS

#define SSI_RIS_RORRIS   0x00000001

◆ SSI_RIS_RTRIS

#define SSI_RIS_RTRIS   0x00000002

◆ SSI_RIS_RXRIS

#define SSI_RIS_RXRIS   0x00000004

◆ SSI_RIS_TXRIS

#define SSI_RIS_TXRIS   0x00000008

◆ SSI_SR_BSY

#define SSI_SR_BSY   0x00000010

◆ SSI_SR_RFF

#define SSI_SR_RFF   0x00000008

◆ SSI_SR_RNE

#define SSI_SR_RNE   0x00000004

◆ SSI_SR_TFE

#define SSI_SR_TFE   0x00000001

◆ SSI_SR_TNF

#define SSI_SR_TNF   0x00000002

◆ SYSCTL_DC0_FLASHSZ_128K

#define SYSCTL_DC0_FLASHSZ_128K   0x0000003F

◆ SYSCTL_DC0_FLASHSZ_16KB

#define SYSCTL_DC0_FLASHSZ_16KB   0x00000007

◆ SYSCTL_DC0_FLASHSZ_192K

#define SYSCTL_DC0_FLASHSZ_192K   0x0000005F

◆ SYSCTL_DC0_FLASHSZ_256K

#define SYSCTL_DC0_FLASHSZ_256K   0x0000007F

◆ SYSCTL_DC0_FLASHSZ_32KB

#define SYSCTL_DC0_FLASHSZ_32KB   0x0000000F

◆ SYSCTL_DC0_FLASHSZ_64KB

#define SYSCTL_DC0_FLASHSZ_64KB   0x0000001F

◆ SYSCTL_DC0_FLASHSZ_8KB

#define SYSCTL_DC0_FLASHSZ_8KB   0x00000003

◆ SYSCTL_DC0_FLASHSZ_96KB

#define SYSCTL_DC0_FLASHSZ_96KB   0x0000002F

◆ SYSCTL_DC0_FLASHSZ_M

#define SYSCTL_DC0_FLASHSZ_M   0x0000FFFF

◆ SYSCTL_DC0_R

#define SYSCTL_DC0_R   (*((volatile u32 *)0x400FE008))

◆ SYSCTL_DC0_SRAMSZ_12KB

#define SYSCTL_DC0_SRAMSZ_12KB   0x002F0000

◆ SYSCTL_DC0_SRAMSZ_16KB

#define SYSCTL_DC0_SRAMSZ_16KB   0x003F0000

◆ SYSCTL_DC0_SRAMSZ_20KB

#define SYSCTL_DC0_SRAMSZ_20KB   0x004F0000

◆ SYSCTL_DC0_SRAMSZ_24KB

#define SYSCTL_DC0_SRAMSZ_24KB   0x005F0000

◆ SYSCTL_DC0_SRAMSZ_2KB

#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000

◆ SYSCTL_DC0_SRAMSZ_32KB

#define SYSCTL_DC0_SRAMSZ_32KB   0x007F0000

◆ SYSCTL_DC0_SRAMSZ_4KB

#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000

◆ SYSCTL_DC0_SRAMSZ_6KB

#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000

◆ SYSCTL_DC0_SRAMSZ_8KB

#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000

◆ SYSCTL_DC0_SRAMSZ_M

#define SYSCTL_DC0_SRAMSZ_M   0xFFFF0000

◆ SYSCTL_DC1_ADC0

#define SYSCTL_DC1_ADC0   0x00010000

◆ SYSCTL_DC1_ADC0SPD_125K

#define SYSCTL_DC1_ADC0SPD_125K   0x00000000

◆ SYSCTL_DC1_ADC0SPD_1M

#define SYSCTL_DC1_ADC0SPD_1M   0x00000300

◆ SYSCTL_DC1_ADC0SPD_250K

#define SYSCTL_DC1_ADC0SPD_250K   0x00000100

◆ SYSCTL_DC1_ADC0SPD_500K

#define SYSCTL_DC1_ADC0SPD_500K   0x00000200

◆ SYSCTL_DC1_ADC0SPD_M

#define SYSCTL_DC1_ADC0SPD_M   0x00000300

◆ SYSCTL_DC1_ADC1

#define SYSCTL_DC1_ADC1   0x00020000

◆ SYSCTL_DC1_ADC1SPD_125K

#define SYSCTL_DC1_ADC1SPD_125K   0x00000000

◆ SYSCTL_DC1_ADC1SPD_1M

#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00

◆ SYSCTL_DC1_ADC1SPD_250K

#define SYSCTL_DC1_ADC1SPD_250K   0x00000400

◆ SYSCTL_DC1_ADC1SPD_500K

#define SYSCTL_DC1_ADC1SPD_500K   0x00000800

◆ SYSCTL_DC1_ADC1SPD_M

#define SYSCTL_DC1_ADC1SPD_M   0x00000C00

◆ SYSCTL_DC1_CAN0

#define SYSCTL_DC1_CAN0   0x01000000

◆ SYSCTL_DC1_CAN1

#define SYSCTL_DC1_CAN1   0x02000000

◆ SYSCTL_DC1_HIB

#define SYSCTL_DC1_HIB   0x00000040

◆ SYSCTL_DC1_JTAG

#define SYSCTL_DC1_JTAG   0x00000001

◆ SYSCTL_DC1_MINSYSDIV_20

#define SYSCTL_DC1_MINSYSDIV_20   0x00009000

◆ SYSCTL_DC1_MINSYSDIV_25

#define SYSCTL_DC1_MINSYSDIV_25   0x00007000

◆ SYSCTL_DC1_MINSYSDIV_40

#define SYSCTL_DC1_MINSYSDIV_40   0x00004000

◆ SYSCTL_DC1_MINSYSDIV_50

#define SYSCTL_DC1_MINSYSDIV_50   0x00003000

◆ SYSCTL_DC1_MINSYSDIV_66

#define SYSCTL_DC1_MINSYSDIV_66   0x00002000

◆ SYSCTL_DC1_MINSYSDIV_80

#define SYSCTL_DC1_MINSYSDIV_80   0x00001000

◆ SYSCTL_DC1_MINSYSDIV_M

#define SYSCTL_DC1_MINSYSDIV_M   0x0000F000

◆ SYSCTL_DC1_MPU

#define SYSCTL_DC1_MPU   0x00000080

◆ SYSCTL_DC1_PLL

#define SYSCTL_DC1_PLL   0x00000010

◆ SYSCTL_DC1_PWM0

#define SYSCTL_DC1_PWM0   0x00100000

◆ SYSCTL_DC1_PWM1

#define SYSCTL_DC1_PWM1   0x00200000

◆ SYSCTL_DC1_R

#define SYSCTL_DC1_R   (*((volatile u32 *)0x400FE010))

◆ SYSCTL_DC1_SWD

#define SYSCTL_DC1_SWD   0x00000002

◆ SYSCTL_DC1_SWO

#define SYSCTL_DC1_SWO   0x00000004

◆ SYSCTL_DC1_TEMP

#define SYSCTL_DC1_TEMP   0x00000020

◆ SYSCTL_DC1_WDT0

#define SYSCTL_DC1_WDT0   0x00000008

◆ SYSCTL_DC1_WDT1

#define SYSCTL_DC1_WDT1   0x10000000

◆ SYSCTL_DC2_COMP0

#define SYSCTL_DC2_COMP0   0x01000000

◆ SYSCTL_DC2_COMP1

#define SYSCTL_DC2_COMP1   0x02000000

◆ SYSCTL_DC2_COMP2

#define SYSCTL_DC2_COMP2   0x04000000

◆ SYSCTL_DC2_EPI0

#define SYSCTL_DC2_EPI0   0x40000000

◆ SYSCTL_DC2_I2C0

#define SYSCTL_DC2_I2C0   0x00001000

◆ SYSCTL_DC2_I2C0HS

#define SYSCTL_DC2_I2C0HS   0x00002000

◆ SYSCTL_DC2_I2C1

#define SYSCTL_DC2_I2C1   0x00004000

◆ SYSCTL_DC2_I2C1HS

#define SYSCTL_DC2_I2C1HS   0x00008000

◆ SYSCTL_DC2_I2S0

#define SYSCTL_DC2_I2S0   0x10000000

◆ SYSCTL_DC2_QEI0

#define SYSCTL_DC2_QEI0   0x00000100

◆ SYSCTL_DC2_QEI1

#define SYSCTL_DC2_QEI1   0x00000200

◆ SYSCTL_DC2_R

#define SYSCTL_DC2_R   (*((volatile u32 *)0x400FE014))

◆ SYSCTL_DC2_SSI0

#define SYSCTL_DC2_SSI0   0x00000010

◆ SYSCTL_DC2_SSI1

#define SYSCTL_DC2_SSI1   0x00000020

◆ SYSCTL_DC2_TIMER0

#define SYSCTL_DC2_TIMER0   0x00010000

◆ SYSCTL_DC2_TIMER1

#define SYSCTL_DC2_TIMER1   0x00020000

◆ SYSCTL_DC2_TIMER2

#define SYSCTL_DC2_TIMER2   0x00040000

◆ SYSCTL_DC2_TIMER3

#define SYSCTL_DC2_TIMER3   0x00080000

◆ SYSCTL_DC2_UART0

#define SYSCTL_DC2_UART0   0x00000001

◆ SYSCTL_DC2_UART1

#define SYSCTL_DC2_UART1   0x00000002

◆ SYSCTL_DC2_UART2

#define SYSCTL_DC2_UART2   0x00000004

◆ SYSCTL_DC3_32KHZ

#define SYSCTL_DC3_32KHZ   0x80000000

◆ SYSCTL_DC3_ADC0AIN0

#define SYSCTL_DC3_ADC0AIN0   0x00010000

◆ SYSCTL_DC3_ADC0AIN1

#define SYSCTL_DC3_ADC0AIN1   0x00020000

◆ SYSCTL_DC3_ADC0AIN2

#define SYSCTL_DC3_ADC0AIN2   0x00040000

◆ SYSCTL_DC3_ADC0AIN3

#define SYSCTL_DC3_ADC0AIN3   0x00080000

◆ SYSCTL_DC3_ADC0AIN4

#define SYSCTL_DC3_ADC0AIN4   0x00100000

◆ SYSCTL_DC3_ADC0AIN5

#define SYSCTL_DC3_ADC0AIN5   0x00200000

◆ SYSCTL_DC3_ADC0AIN6

#define SYSCTL_DC3_ADC0AIN6   0x00400000

◆ SYSCTL_DC3_ADC0AIN7

#define SYSCTL_DC3_ADC0AIN7   0x00800000

◆ SYSCTL_DC3_C0MINUS

#define SYSCTL_DC3_C0MINUS   0x00000040

◆ SYSCTL_DC3_C0O

#define SYSCTL_DC3_C0O   0x00000100

◆ SYSCTL_DC3_C0PLUS

#define SYSCTL_DC3_C0PLUS   0x00000080

◆ SYSCTL_DC3_C1MINUS

#define SYSCTL_DC3_C1MINUS   0x00000200

◆ SYSCTL_DC3_C1O

#define SYSCTL_DC3_C1O   0x00000800

◆ SYSCTL_DC3_C1PLUS

#define SYSCTL_DC3_C1PLUS   0x00000400

◆ SYSCTL_DC3_C2MINUS

#define SYSCTL_DC3_C2MINUS   0x00001000

◆ SYSCTL_DC3_C2O

#define SYSCTL_DC3_C2O   0x00004000

◆ SYSCTL_DC3_C2PLUS

#define SYSCTL_DC3_C2PLUS   0x00002000

◆ SYSCTL_DC3_CCP0

#define SYSCTL_DC3_CCP0   0x01000000

◆ SYSCTL_DC3_CCP1

#define SYSCTL_DC3_CCP1   0x02000000

◆ SYSCTL_DC3_CCP2

#define SYSCTL_DC3_CCP2   0x04000000

◆ SYSCTL_DC3_CCP3

#define SYSCTL_DC3_CCP3   0x08000000

◆ SYSCTL_DC3_CCP4

#define SYSCTL_DC3_CCP4   0x10000000

◆ SYSCTL_DC3_CCP5

#define SYSCTL_DC3_CCP5   0x20000000

◆ SYSCTL_DC3_PWM0

#define SYSCTL_DC3_PWM0   0x00000001

◆ SYSCTL_DC3_PWM1

#define SYSCTL_DC3_PWM1   0x00000002

◆ SYSCTL_DC3_PWM2

#define SYSCTL_DC3_PWM2   0x00000004

◆ SYSCTL_DC3_PWM3

#define SYSCTL_DC3_PWM3   0x00000008

◆ SYSCTL_DC3_PWM4

#define SYSCTL_DC3_PWM4   0x00000010

◆ SYSCTL_DC3_PWM5

#define SYSCTL_DC3_PWM5   0x00000020

◆ SYSCTL_DC3_PWMFAULT

#define SYSCTL_DC3_PWMFAULT   0x00008000

◆ SYSCTL_DC3_R

#define SYSCTL_DC3_R   (*((volatile u32 *)0x400FE018))

◆ SYSCTL_DC4_CCP6

#define SYSCTL_DC4_CCP6   0x00004000

◆ SYSCTL_DC4_CCP7

#define SYSCTL_DC4_CCP7   0x00008000

◆ SYSCTL_DC4_E1588

#define SYSCTL_DC4_E1588   0x01000000

◆ SYSCTL_DC4_EMAC0

#define SYSCTL_DC4_EMAC0   0x10000000

◆ SYSCTL_DC4_EPHY0

#define SYSCTL_DC4_EPHY0   0x40000000

◆ SYSCTL_DC4_GPIOA

#define SYSCTL_DC4_GPIOA   0x00000001

◆ SYSCTL_DC4_GPIOB

#define SYSCTL_DC4_GPIOB   0x00000002

◆ SYSCTL_DC4_GPIOC

#define SYSCTL_DC4_GPIOC   0x00000004

◆ SYSCTL_DC4_GPIOD

#define SYSCTL_DC4_GPIOD   0x00000008

◆ SYSCTL_DC4_GPIOE

#define SYSCTL_DC4_GPIOE   0x00000010

◆ SYSCTL_DC4_GPIOF

#define SYSCTL_DC4_GPIOF   0x00000020

◆ SYSCTL_DC4_GPIOG

#define SYSCTL_DC4_GPIOG   0x00000040

◆ SYSCTL_DC4_GPIOH

#define SYSCTL_DC4_GPIOH   0x00000080

◆ SYSCTL_DC4_GPIOJ

#define SYSCTL_DC4_GPIOJ   0x00000100

◆ SYSCTL_DC4_PICAL

#define SYSCTL_DC4_PICAL   0x00040000

◆ SYSCTL_DC4_R

#define SYSCTL_DC4_R   (*((volatile u32 *)0x400FE01C))

◆ SYSCTL_DC4_ROM

#define SYSCTL_DC4_ROM   0x00001000

◆ SYSCTL_DC4_UDMA

#define SYSCTL_DC4_UDMA   0x00002000

◆ SYSCTL_DC5_PWM0

#define SYSCTL_DC5_PWM0   0x00000001

◆ SYSCTL_DC5_PWM1

#define SYSCTL_DC5_PWM1   0x00000002

◆ SYSCTL_DC5_PWM2

#define SYSCTL_DC5_PWM2   0x00000004

◆ SYSCTL_DC5_PWM3

#define SYSCTL_DC5_PWM3   0x00000008

◆ SYSCTL_DC5_PWM4

#define SYSCTL_DC5_PWM4   0x00000010

◆ SYSCTL_DC5_PWM5

#define SYSCTL_DC5_PWM5   0x00000020

◆ SYSCTL_DC5_PWM6

#define SYSCTL_DC5_PWM6   0x00000040

◆ SYSCTL_DC5_PWM7

#define SYSCTL_DC5_PWM7   0x00000080

◆ SYSCTL_DC5_PWMEFLT

#define SYSCTL_DC5_PWMEFLT   0x00200000

◆ SYSCTL_DC5_PWMESYNC

#define SYSCTL_DC5_PWMESYNC   0x00100000

◆ SYSCTL_DC5_PWMFAULT0

#define SYSCTL_DC5_PWMFAULT0   0x01000000

◆ SYSCTL_DC5_PWMFAULT1

#define SYSCTL_DC5_PWMFAULT1   0x02000000

◆ SYSCTL_DC5_PWMFAULT2

#define SYSCTL_DC5_PWMFAULT2   0x04000000

◆ SYSCTL_DC5_PWMFAULT3

#define SYSCTL_DC5_PWMFAULT3   0x08000000

◆ SYSCTL_DC5_R

#define SYSCTL_DC5_R   (*((volatile u32 *)0x400FE020))

◆ SYSCTL_DC6_R

#define SYSCTL_DC6_R   (*((volatile u32 *)0x400FE024))

◆ SYSCTL_DC6_USB0_DEV

#define SYSCTL_DC6_USB0_DEV   0x00000001

◆ SYSCTL_DC6_USB0_HOSTDEV

#define SYSCTL_DC6_USB0_HOSTDEV   0x00000002

◆ SYSCTL_DC6_USB0_M

#define SYSCTL_DC6_USB0_M   0x00000003

◆ SYSCTL_DC6_USB0_OTG

#define SYSCTL_DC6_USB0_OTG   0x00000003

◆ SYSCTL_DC6_USB0PHY

#define SYSCTL_DC6_USB0PHY   0x00000010

◆ SYSCTL_DC7_DMACH0

#define SYSCTL_DC7_DMACH0   0x00000001

◆ SYSCTL_DC7_DMACH1

#define SYSCTL_DC7_DMACH1   0x00000002

◆ SYSCTL_DC7_DMACH10

#define SYSCTL_DC7_DMACH10   0x00000400

◆ SYSCTL_DC7_DMACH11

#define SYSCTL_DC7_DMACH11   0x00000800

◆ SYSCTL_DC7_DMACH12

#define SYSCTL_DC7_DMACH12   0x00001000

◆ SYSCTL_DC7_DMACH13

#define SYSCTL_DC7_DMACH13   0x00002000

◆ SYSCTL_DC7_DMACH14

#define SYSCTL_DC7_DMACH14   0x00004000

◆ SYSCTL_DC7_DMACH15

#define SYSCTL_DC7_DMACH15   0x00008000

◆ SYSCTL_DC7_DMACH16

#define SYSCTL_DC7_DMACH16   0x00010000

◆ SYSCTL_DC7_DMACH17

#define SYSCTL_DC7_DMACH17   0x00020000

◆ SYSCTL_DC7_DMACH18

#define SYSCTL_DC7_DMACH18   0x00040000

◆ SYSCTL_DC7_DMACH19

#define SYSCTL_DC7_DMACH19   0x00080000

◆ SYSCTL_DC7_DMACH2

#define SYSCTL_DC7_DMACH2   0x00000004

◆ SYSCTL_DC7_DMACH20

#define SYSCTL_DC7_DMACH20   0x00100000

◆ SYSCTL_DC7_DMACH21

#define SYSCTL_DC7_DMACH21   0x00200000

◆ SYSCTL_DC7_DMACH22

#define SYSCTL_DC7_DMACH22   0x00400000

◆ SYSCTL_DC7_DMACH23

#define SYSCTL_DC7_DMACH23   0x00800000

◆ SYSCTL_DC7_DMACH24

#define SYSCTL_DC7_DMACH24   0x01000000

◆ SYSCTL_DC7_DMACH25

#define SYSCTL_DC7_DMACH25   0x02000000

◆ SYSCTL_DC7_DMACH26

#define SYSCTL_DC7_DMACH26   0x04000000

◆ SYSCTL_DC7_DMACH27

#define SYSCTL_DC7_DMACH27   0x08000000

◆ SYSCTL_DC7_DMACH28

#define SYSCTL_DC7_DMACH28   0x10000000

◆ SYSCTL_DC7_DMACH29

#define SYSCTL_DC7_DMACH29   0x20000000

◆ SYSCTL_DC7_DMACH3

#define SYSCTL_DC7_DMACH3   0x00000008

◆ SYSCTL_DC7_DMACH30

#define SYSCTL_DC7_DMACH30   0x40000000

◆ SYSCTL_DC7_DMACH4

#define SYSCTL_DC7_DMACH4   0x00000010

◆ SYSCTL_DC7_DMACH5

#define SYSCTL_DC7_DMACH5   0x00000020

◆ SYSCTL_DC7_DMACH6

#define SYSCTL_DC7_DMACH6   0x00000040

◆ SYSCTL_DC7_DMACH7

#define SYSCTL_DC7_DMACH7   0x00000080

◆ SYSCTL_DC7_DMACH8

#define SYSCTL_DC7_DMACH8   0x00000100

◆ SYSCTL_DC7_DMACH9

#define SYSCTL_DC7_DMACH9   0x00000200

◆ SYSCTL_DC7_R

#define SYSCTL_DC7_R   (*((volatile u32 *)0x400FE028))

◆ SYSCTL_DC8_ADC0AIN0

#define SYSCTL_DC8_ADC0AIN0   0x00000001

◆ SYSCTL_DC8_ADC0AIN1

#define SYSCTL_DC8_ADC0AIN1   0x00000002

◆ SYSCTL_DC8_ADC0AIN10

#define SYSCTL_DC8_ADC0AIN10   0x00000400

◆ SYSCTL_DC8_ADC0AIN11

#define SYSCTL_DC8_ADC0AIN11   0x00000800

◆ SYSCTL_DC8_ADC0AIN12

#define SYSCTL_DC8_ADC0AIN12   0x00001000

◆ SYSCTL_DC8_ADC0AIN13

#define SYSCTL_DC8_ADC0AIN13   0x00002000

◆ SYSCTL_DC8_ADC0AIN14

#define SYSCTL_DC8_ADC0AIN14   0x00004000

◆ SYSCTL_DC8_ADC0AIN15

#define SYSCTL_DC8_ADC0AIN15   0x00008000

◆ SYSCTL_DC8_ADC0AIN2

#define SYSCTL_DC8_ADC0AIN2   0x00000004

◆ SYSCTL_DC8_ADC0AIN3

#define SYSCTL_DC8_ADC0AIN3   0x00000008

◆ SYSCTL_DC8_ADC0AIN4

#define SYSCTL_DC8_ADC0AIN4   0x00000010

◆ SYSCTL_DC8_ADC0AIN5

#define SYSCTL_DC8_ADC0AIN5   0x00000020

◆ SYSCTL_DC8_ADC0AIN6

#define SYSCTL_DC8_ADC0AIN6   0x00000040

◆ SYSCTL_DC8_ADC0AIN7

#define SYSCTL_DC8_ADC0AIN7   0x00000080

◆ SYSCTL_DC8_ADC0AIN8

#define SYSCTL_DC8_ADC0AIN8   0x00000100

◆ SYSCTL_DC8_ADC0AIN9

#define SYSCTL_DC8_ADC0AIN9   0x00000200

◆ SYSCTL_DC8_ADC1AIN0

#define SYSCTL_DC8_ADC1AIN0   0x00010000

◆ SYSCTL_DC8_ADC1AIN1

#define SYSCTL_DC8_ADC1AIN1   0x00020000

◆ SYSCTL_DC8_ADC1AIN10

#define SYSCTL_DC8_ADC1AIN10   0x04000000

◆ SYSCTL_DC8_ADC1AIN11

#define SYSCTL_DC8_ADC1AIN11   0x08000000

◆ SYSCTL_DC8_ADC1AIN12

#define SYSCTL_DC8_ADC1AIN12   0x10000000

◆ SYSCTL_DC8_ADC1AIN13

#define SYSCTL_DC8_ADC1AIN13   0x20000000

◆ SYSCTL_DC8_ADC1AIN14

#define SYSCTL_DC8_ADC1AIN14   0x40000000

◆ SYSCTL_DC8_ADC1AIN15

#define SYSCTL_DC8_ADC1AIN15   0x80000000

◆ SYSCTL_DC8_ADC1AIN2

#define SYSCTL_DC8_ADC1AIN2   0x00040000

◆ SYSCTL_DC8_ADC1AIN3

#define SYSCTL_DC8_ADC1AIN3   0x00080000

◆ SYSCTL_DC8_ADC1AIN4

#define SYSCTL_DC8_ADC1AIN4   0x00100000

◆ SYSCTL_DC8_ADC1AIN5

#define SYSCTL_DC8_ADC1AIN5   0x00200000

◆ SYSCTL_DC8_ADC1AIN6

#define SYSCTL_DC8_ADC1AIN6   0x00400000

◆ SYSCTL_DC8_ADC1AIN7

#define SYSCTL_DC8_ADC1AIN7   0x00800000

◆ SYSCTL_DC8_ADC1AIN8

#define SYSCTL_DC8_ADC1AIN8   0x01000000

◆ SYSCTL_DC8_ADC1AIN9

#define SYSCTL_DC8_ADC1AIN9   0x02000000

◆ SYSCTL_DC8_R

#define SYSCTL_DC8_R   (*((volatile u32 *)0x400FE02C))

◆ SYSCTL_DC9_ADC0DC0

#define SYSCTL_DC9_ADC0DC0   0x00000001

◆ SYSCTL_DC9_ADC0DC1

#define SYSCTL_DC9_ADC0DC1   0x00000002

◆ SYSCTL_DC9_ADC0DC2

#define SYSCTL_DC9_ADC0DC2   0x00000004

◆ SYSCTL_DC9_ADC0DC3

#define SYSCTL_DC9_ADC0DC3   0x00000008

◆ SYSCTL_DC9_ADC0DC4

#define SYSCTL_DC9_ADC0DC4   0x00000010

◆ SYSCTL_DC9_ADC0DC5

#define SYSCTL_DC9_ADC0DC5   0x00000020

◆ SYSCTL_DC9_ADC0DC6

#define SYSCTL_DC9_ADC0DC6   0x00000040

◆ SYSCTL_DC9_ADC0DC7

#define SYSCTL_DC9_ADC0DC7   0x00000080

◆ SYSCTL_DC9_ADC1DC0

#define SYSCTL_DC9_ADC1DC0   0x00010000

◆ SYSCTL_DC9_ADC1DC1

#define SYSCTL_DC9_ADC1DC1   0x00020000

◆ SYSCTL_DC9_ADC1DC2

#define SYSCTL_DC9_ADC1DC2   0x00040000

◆ SYSCTL_DC9_ADC1DC3

#define SYSCTL_DC9_ADC1DC3   0x00080000

◆ SYSCTL_DC9_ADC1DC4

#define SYSCTL_DC9_ADC1DC4   0x00100000

◆ SYSCTL_DC9_ADC1DC5

#define SYSCTL_DC9_ADC1DC5   0x00200000

◆ SYSCTL_DC9_ADC1DC6

#define SYSCTL_DC9_ADC1DC6   0x00400000

◆ SYSCTL_DC9_ADC1DC7

#define SYSCTL_DC9_ADC1DC7   0x00800000

◆ SYSCTL_DC9_R

#define SYSCTL_DC9_R   (*((volatile u32 *)0x400FE190))

◆ SYSCTL_DCGC0_ADC0

#define SYSCTL_DCGC0_ADC0   0x00010000

◆ SYSCTL_DCGC0_ADC1

#define SYSCTL_DCGC0_ADC1   0x00020000

◆ SYSCTL_DCGC0_CAN0

#define SYSCTL_DCGC0_CAN0   0x01000000

◆ SYSCTL_DCGC0_CAN1

#define SYSCTL_DCGC0_CAN1   0x02000000

◆ SYSCTL_DCGC0_HIB

#define SYSCTL_DCGC0_HIB   0x00000040

◆ SYSCTL_DCGC0_PWM0

#define SYSCTL_DCGC0_PWM0   0x00100000

◆ SYSCTL_DCGC0_R

#define SYSCTL_DCGC0_R   (*((volatile u32 *)0x400FE120))

◆ SYSCTL_DCGC0_WDT0

#define SYSCTL_DCGC0_WDT0   0x00000008

◆ SYSCTL_DCGC0_WDT1

#define SYSCTL_DCGC0_WDT1   0x10000000

◆ SYSCTL_DCGC1_COMP0

#define SYSCTL_DCGC1_COMP0   0x01000000

◆ SYSCTL_DCGC1_COMP1

#define SYSCTL_DCGC1_COMP1   0x02000000

◆ SYSCTL_DCGC1_I2C0

#define SYSCTL_DCGC1_I2C0   0x00001000

◆ SYSCTL_DCGC1_I2C1

#define SYSCTL_DCGC1_I2C1   0x00004000

◆ SYSCTL_DCGC1_QEI0

#define SYSCTL_DCGC1_QEI0   0x00000100

◆ SYSCTL_DCGC1_QEI1

#define SYSCTL_DCGC1_QEI1   0x00000200

◆ SYSCTL_DCGC1_R

#define SYSCTL_DCGC1_R   (*((volatile u32 *)0x400FE124))

◆ SYSCTL_DCGC1_SSI0

#define SYSCTL_DCGC1_SSI0   0x00000010

◆ SYSCTL_DCGC1_SSI1

#define SYSCTL_DCGC1_SSI1   0x00000020

◆ SYSCTL_DCGC1_TIMER0

#define SYSCTL_DCGC1_TIMER0   0x00010000

◆ SYSCTL_DCGC1_TIMER1

#define SYSCTL_DCGC1_TIMER1   0x00020000

◆ SYSCTL_DCGC1_TIMER2

#define SYSCTL_DCGC1_TIMER2   0x00040000

◆ SYSCTL_DCGC1_TIMER3

#define SYSCTL_DCGC1_TIMER3   0x00080000

◆ SYSCTL_DCGC1_UART0

#define SYSCTL_DCGC1_UART0   0x00000001

◆ SYSCTL_DCGC1_UART1

#define SYSCTL_DCGC1_UART1   0x00000002

◆ SYSCTL_DCGC1_UART2

#define SYSCTL_DCGC1_UART2   0x00000004

◆ SYSCTL_DCGC2_GPIOA

#define SYSCTL_DCGC2_GPIOA   0x00000001

◆ SYSCTL_DCGC2_GPIOB

#define SYSCTL_DCGC2_GPIOB   0x00000002

◆ SYSCTL_DCGC2_GPIOC

#define SYSCTL_DCGC2_GPIOC   0x00000004

◆ SYSCTL_DCGC2_GPIOD

#define SYSCTL_DCGC2_GPIOD   0x00000008

◆ SYSCTL_DCGC2_GPIOE

#define SYSCTL_DCGC2_GPIOE   0x00000010

◆ SYSCTL_DCGC2_GPIOF

#define SYSCTL_DCGC2_GPIOF   0x00000020

◆ SYSCTL_DCGC2_R

#define SYSCTL_DCGC2_R   (*((volatile u32 *)0x400FE128))

◆ SYSCTL_DCGC2_UDMA

#define SYSCTL_DCGC2_UDMA   0x00002000

◆ SYSCTL_DCGC2_USB0

#define SYSCTL_DCGC2_USB0   0x00010000

◆ SYSCTL_DCGCACMP_D0

#define SYSCTL_DCGCACMP_D0   0x00000001

◆ SYSCTL_DCGCACMP_R

#define SYSCTL_DCGCACMP_R   (*((volatile u32 *)0x400FE83C))

◆ SYSCTL_DCGCADC_D0

#define SYSCTL_DCGCADC_D0   0x00000001

◆ SYSCTL_DCGCADC_D1

#define SYSCTL_DCGCADC_D1   0x00000002

◆ SYSCTL_DCGCADC_R

#define SYSCTL_DCGCADC_R   (*((volatile u32 *)0x400FE838))

◆ SYSCTL_DCGCCAN_D0

#define SYSCTL_DCGCCAN_D0   0x00000001

◆ SYSCTL_DCGCCAN_D1

#define SYSCTL_DCGCCAN_D1   0x00000002

◆ SYSCTL_DCGCCAN_R

#define SYSCTL_DCGCCAN_R   (*((volatile u32 *)0x400FE834))

◆ SYSCTL_DCGCDMA_D0

#define SYSCTL_DCGCDMA_D0   0x00000001

◆ SYSCTL_DCGCDMA_R

#define SYSCTL_DCGCDMA_R   (*((volatile u32 *)0x400FE80C))

◆ SYSCTL_DCGCEEPROM_D0

#define SYSCTL_DCGCEEPROM_D0   0x00000001

◆ SYSCTL_DCGCEEPROM_R

#define SYSCTL_DCGCEEPROM_R   (*((volatile u32 *)0x400FE858))

◆ SYSCTL_DCGCGPIO_D0

#define SYSCTL_DCGCGPIO_D0   0x00000001

◆ SYSCTL_DCGCGPIO_D1

#define SYSCTL_DCGCGPIO_D1   0x00000002

◆ SYSCTL_DCGCGPIO_D2

#define SYSCTL_DCGCGPIO_D2   0x00000004

◆ SYSCTL_DCGCGPIO_D3

#define SYSCTL_DCGCGPIO_D3   0x00000008

◆ SYSCTL_DCGCGPIO_D4

#define SYSCTL_DCGCGPIO_D4   0x00000010

◆ SYSCTL_DCGCGPIO_D5

#define SYSCTL_DCGCGPIO_D5   0x00000020

◆ SYSCTL_DCGCGPIO_R

#define SYSCTL_DCGCGPIO_R   (*((volatile u32 *)0x400FE808))

◆ SYSCTL_DCGCHIB_D0

#define SYSCTL_DCGCHIB_D0   0x00000001

◆ SYSCTL_DCGCHIB_R

#define SYSCTL_DCGCHIB_R   (*((volatile u32 *)0x400FE814))

◆ SYSCTL_DCGCI2C_D0

#define SYSCTL_DCGCI2C_D0   0x00000001

◆ SYSCTL_DCGCI2C_D1

#define SYSCTL_DCGCI2C_D1   0x00000002

◆ SYSCTL_DCGCI2C_D2

#define SYSCTL_DCGCI2C_D2   0x00000004

◆ SYSCTL_DCGCI2C_D3

#define SYSCTL_DCGCI2C_D3   0x00000008

◆ SYSCTL_DCGCI2C_R

#define SYSCTL_DCGCI2C_R   (*((volatile u32 *)0x400FE820))

◆ SYSCTL_DCGCPWM_D0

#define SYSCTL_DCGCPWM_D0   0x00000001

◆ SYSCTL_DCGCPWM_D1

#define SYSCTL_DCGCPWM_D1   0x00000002

◆ SYSCTL_DCGCPWM_R

#define SYSCTL_DCGCPWM_R   (*((volatile u32 *)0x400FE840))

◆ SYSCTL_DCGCQEI_D0

#define SYSCTL_DCGCQEI_D0   0x00000001

◆ SYSCTL_DCGCQEI_D1

#define SYSCTL_DCGCQEI_D1   0x00000002

◆ SYSCTL_DCGCQEI_R

#define SYSCTL_DCGCQEI_R   (*((volatile u32 *)0x400FE844))

◆ SYSCTL_DCGCSSI_D0

#define SYSCTL_DCGCSSI_D0   0x00000001

◆ SYSCTL_DCGCSSI_D1

#define SYSCTL_DCGCSSI_D1   0x00000002

◆ SYSCTL_DCGCSSI_D2

#define SYSCTL_DCGCSSI_D2   0x00000004

◆ SYSCTL_DCGCSSI_D3

#define SYSCTL_DCGCSSI_D3   0x00000008

◆ SYSCTL_DCGCSSI_R

#define SYSCTL_DCGCSSI_R   (*((volatile u32 *)0x400FE81C))

◆ SYSCTL_DCGCTIMER_D0

#define SYSCTL_DCGCTIMER_D0   0x00000001

◆ SYSCTL_DCGCTIMER_D1

#define SYSCTL_DCGCTIMER_D1   0x00000002

◆ SYSCTL_DCGCTIMER_D2

#define SYSCTL_DCGCTIMER_D2   0x00000004

◆ SYSCTL_DCGCTIMER_D3

#define SYSCTL_DCGCTIMER_D3   0x00000008

◆ SYSCTL_DCGCTIMER_D4

#define SYSCTL_DCGCTIMER_D4   0x00000010

◆ SYSCTL_DCGCTIMER_D5

#define SYSCTL_DCGCTIMER_D5   0x00000020

◆ SYSCTL_DCGCTIMER_R

#define SYSCTL_DCGCTIMER_R   (*((volatile u32 *)0x400FE804))

◆ SYSCTL_DCGCUART_D0

#define SYSCTL_DCGCUART_D0   0x00000001

◆ SYSCTL_DCGCUART_D1

#define SYSCTL_DCGCUART_D1   0x00000002

◆ SYSCTL_DCGCUART_D2

#define SYSCTL_DCGCUART_D2   0x00000004

◆ SYSCTL_DCGCUART_D3

#define SYSCTL_DCGCUART_D3   0x00000008

◆ SYSCTL_DCGCUART_D4

#define SYSCTL_DCGCUART_D4   0x00000010

◆ SYSCTL_DCGCUART_D5

#define SYSCTL_DCGCUART_D5   0x00000020

◆ SYSCTL_DCGCUART_D6

#define SYSCTL_DCGCUART_D6   0x00000040

◆ SYSCTL_DCGCUART_D7

#define SYSCTL_DCGCUART_D7   0x00000080

◆ SYSCTL_DCGCUART_R

#define SYSCTL_DCGCUART_R   (*((volatile u32 *)0x400FE818))

◆ SYSCTL_DCGCUSB_D0

#define SYSCTL_DCGCUSB_D0   0x00000001

◆ SYSCTL_DCGCUSB_R

#define SYSCTL_DCGCUSB_R   (*((volatile u32 *)0x400FE828))

◆ SYSCTL_DCGCWD_D0

#define SYSCTL_DCGCWD_D0   0x00000001

◆ SYSCTL_DCGCWD_D1

#define SYSCTL_DCGCWD_D1   0x00000002

◆ SYSCTL_DCGCWD_R

#define SYSCTL_DCGCWD_R   (*((volatile u32 *)0x400FE800))

◆ SYSCTL_DCGCWTIMER_D0

#define SYSCTL_DCGCWTIMER_D0   0x00000001

◆ SYSCTL_DCGCWTIMER_D1

#define SYSCTL_DCGCWTIMER_D1   0x00000002

◆ SYSCTL_DCGCWTIMER_D2

#define SYSCTL_DCGCWTIMER_D2   0x00000004

◆ SYSCTL_DCGCWTIMER_D3

#define SYSCTL_DCGCWTIMER_D3   0x00000008

◆ SYSCTL_DCGCWTIMER_D4

#define SYSCTL_DCGCWTIMER_D4   0x00000010

◆ SYSCTL_DCGCWTIMER_D5

#define SYSCTL_DCGCWTIMER_D5   0x00000020

◆ SYSCTL_DCGCWTIMER_R

#define SYSCTL_DCGCWTIMER_R   (*((volatile u32 *)0x400FE85C))

◆ SYSCTL_DID0_CLASS_BLIZZARD

#define SYSCTL_DID0_CLASS_BLIZZARD    0x00050000

◆ SYSCTL_DID0_CLASS_M

#define SYSCTL_DID0_CLASS_M   0x00FF0000

◆ SYSCTL_DID0_CLASS_TM4C123

#define SYSCTL_DID0_CLASS_TM4C123    0x00050000

◆ SYSCTL_DID0_MAJ_M

#define SYSCTL_DID0_MAJ_M   0x0000FF00

◆ SYSCTL_DID0_MAJ_REVA

#define SYSCTL_DID0_MAJ_REVA   0x00000000

◆ SYSCTL_DID0_MAJ_REVB

#define SYSCTL_DID0_MAJ_REVB   0x00000100

◆ SYSCTL_DID0_MAJ_REVC

#define SYSCTL_DID0_MAJ_REVC   0x00000200

◆ SYSCTL_DID0_MIN_0

#define SYSCTL_DID0_MIN_0   0x00000000

◆ SYSCTL_DID0_MIN_1

#define SYSCTL_DID0_MIN_1   0x00000001

◆ SYSCTL_DID0_MIN_2

#define SYSCTL_DID0_MIN_2   0x00000002

◆ SYSCTL_DID0_MIN_M

#define SYSCTL_DID0_MIN_M   0x000000FF

◆ SYSCTL_DID0_R

#define SYSCTL_DID0_R   (*((volatile u32 *)0x400FE000))

◆ SYSCTL_DID0_VER_1

#define SYSCTL_DID0_VER_1   0x10000000

◆ SYSCTL_DID0_VER_M

#define SYSCTL_DID0_VER_M   0x70000000

◆ SYSCTL_DID1_FAM_M

#define SYSCTL_DID1_FAM_M   0x0F000000

◆ SYSCTL_DID1_FAM_TIVA

#define SYSCTL_DID1_FAM_TIVA   0x00000000

◆ SYSCTL_DID1_PINCNT_100

#define SYSCTL_DID1_PINCNT_100   0x00004000

◆ SYSCTL_DID1_PINCNT_128

#define SYSCTL_DID1_PINCNT_128   0x0000C000

◆ SYSCTL_DID1_PINCNT_144

#define SYSCTL_DID1_PINCNT_144   0x00008000

◆ SYSCTL_DID1_PINCNT_157

#define SYSCTL_DID1_PINCNT_157   0x0000A000

◆ SYSCTL_DID1_PINCNT_64

#define SYSCTL_DID1_PINCNT_64   0x00006000

◆ SYSCTL_DID1_PINCNT_M

#define SYSCTL_DID1_PINCNT_M   0x0000E000

◆ SYSCTL_DID1_PKG_BGA

#define SYSCTL_DID1_PKG_BGA   0x00000010

◆ SYSCTL_DID1_PKG_M

#define SYSCTL_DID1_PKG_M   0x00000018

◆ SYSCTL_DID1_PKG_QFP

#define SYSCTL_DID1_PKG_QFP   0x00000008

◆ SYSCTL_DID1_PRTNO_M

#define SYSCTL_DID1_PRTNO_M   0x00FF0000

◆ SYSCTL_DID1_PRTNO_TM4C123GH6PM

#define SYSCTL_DID1_PRTNO_TM4C123GH6PM    0x00A10000

◆ SYSCTL_DID1_QUAL_ES

#define SYSCTL_DID1_QUAL_ES   0x00000000

◆ SYSCTL_DID1_QUAL_FQ

#define SYSCTL_DID1_QUAL_FQ   0x00000002

◆ SYSCTL_DID1_QUAL_M

#define SYSCTL_DID1_QUAL_M   0x00000003

◆ SYSCTL_DID1_QUAL_PP

#define SYSCTL_DID1_QUAL_PP   0x00000001

◆ SYSCTL_DID1_R

#define SYSCTL_DID1_R   (*((volatile u32 *)0x400FE004))

◆ SYSCTL_DID1_ROHS

#define SYSCTL_DID1_ROHS   0x00000004

◆ SYSCTL_DID1_TEMP_E

#define SYSCTL_DID1_TEMP_E   0x00000040

◆ SYSCTL_DID1_TEMP_I

#define SYSCTL_DID1_TEMP_I   0x00000020

◆ SYSCTL_DID1_TEMP_IE

#define SYSCTL_DID1_TEMP_IE   0x00000060

◆ SYSCTL_DID1_TEMP_M

#define SYSCTL_DID1_TEMP_M   0x000000E0

◆ SYSCTL_DID1_VER_1

#define SYSCTL_DID1_VER_1   0x10000000

◆ SYSCTL_DID1_VER_M

#define SYSCTL_DID1_VER_M   0xF0000000

◆ SYSCTL_DSLPCLKCFG_D_M

#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000

◆ SYSCTL_DSLPCLKCFG_D_S

#define SYSCTL_DSLPCLKCFG_D_S   23

◆ SYSCTL_DSLPCLKCFG_O_30

#define SYSCTL_DSLPCLKCFG_O_30   0x00000030

◆ SYSCTL_DSLPCLKCFG_O_32

#define SYSCTL_DSLPCLKCFG_O_32   0x00000070

◆ SYSCTL_DSLPCLKCFG_O_IGN

#define SYSCTL_DSLPCLKCFG_O_IGN   0x00000000

◆ SYSCTL_DSLPCLKCFG_O_IO

#define SYSCTL_DSLPCLKCFG_O_IO   0x00000010

◆ SYSCTL_DSLPCLKCFG_O_M

#define SYSCTL_DSLPCLKCFG_O_M   0x00000070

◆ SYSCTL_DSLPCLKCFG_PIOSCPD

#define SYSCTL_DSLPCLKCFG_PIOSCPD    0x00000002

◆ SYSCTL_DSLPCLKCFG_R

#define SYSCTL_DSLPCLKCFG_R   (*((volatile u32 *)0x400FE144))

◆ SYSCTL_DSLPPWRCFG_FLASHPM_M

#define SYSCTL_DSLPPWRCFG_FLASHPM_M    0x00000030

◆ SYSCTL_DSLPPWRCFG_FLASHPM_NRM

#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM    0x00000000

◆ SYSCTL_DSLPPWRCFG_FLASHPM_SLP

#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP    0x00000020

◆ SYSCTL_DSLPPWRCFG_R

#define SYSCTL_DSLPPWRCFG_R   (*((volatile u32 *)0x400FE18C))

◆ SYSCTL_DSLPPWRCFG_SRAMPM_LP

#define SYSCTL_DSLPPWRCFG_SRAMPM_LP    0x00000003

◆ SYSCTL_DSLPPWRCFG_SRAMPM_M

#define SYSCTL_DSLPPWRCFG_SRAMPM_M    0x00000003

◆ SYSCTL_DSLPPWRCFG_SRAMPM_NRM

#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM    0x00000000

◆ SYSCTL_DSLPPWRCFG_SRAMPM_SBY

#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY    0x00000001

◆ SYSCTL_GPIOHBCTL_PORTA

#define SYSCTL_GPIOHBCTL_PORTA   0x00000001

◆ SYSCTL_GPIOHBCTL_PORTB

#define SYSCTL_GPIOHBCTL_PORTB   0x00000002

◆ SYSCTL_GPIOHBCTL_PORTC

#define SYSCTL_GPIOHBCTL_PORTC   0x00000004

◆ SYSCTL_GPIOHBCTL_PORTD

#define SYSCTL_GPIOHBCTL_PORTD   0x00000008

◆ SYSCTL_GPIOHBCTL_PORTE

#define SYSCTL_GPIOHBCTL_PORTE   0x00000010

◆ SYSCTL_GPIOHBCTL_PORTF

#define SYSCTL_GPIOHBCTL_PORTF   0x00000020

◆ SYSCTL_GPIOHBCTL_R

#define SYSCTL_GPIOHBCTL_R   (*((volatile u32 *)0x400FE06C))

◆ SYSCTL_IMC_BOR0IM

#define SYSCTL_IMC_BOR0IM   0x00000800

◆ SYSCTL_IMC_BOR1IM

#define SYSCTL_IMC_BOR1IM   0x00000002

◆ SYSCTL_IMC_MOFIM

#define SYSCTL_IMC_MOFIM   0x00000008

◆ SYSCTL_IMC_MOSCPUPIM

#define SYSCTL_IMC_MOSCPUPIM   0x00000100

◆ SYSCTL_IMC_PLLLIM

#define SYSCTL_IMC_PLLLIM   0x00000040

◆ SYSCTL_IMC_R

#define SYSCTL_IMC_R   (*((volatile u32 *)0x400FE054))

◆ SYSCTL_IMC_USBPLLLIM

#define SYSCTL_IMC_USBPLLLIM   0x00000080

◆ SYSCTL_IMC_VDDAIM

#define SYSCTL_IMC_VDDAIM   0x00000400

◆ SYSCTL_LDODPCTL_R

#define SYSCTL_LDODPCTL_R   (*((volatile u32 *)0x400FE1BC))

◆ SYSCTL_LDODPCTL_VADJEN

#define SYSCTL_LDODPCTL_VADJEN   0x80000000

◆ SYSCTL_LDODPCTL_VLDO_0_90V

#define SYSCTL_LDODPCTL_VLDO_0_90V    0x00000012

◆ SYSCTL_LDODPCTL_VLDO_0_95V

#define SYSCTL_LDODPCTL_VLDO_0_95V    0x00000013

◆ SYSCTL_LDODPCTL_VLDO_1_00V

#define SYSCTL_LDODPCTL_VLDO_1_00V    0x00000014

◆ SYSCTL_LDODPCTL_VLDO_1_05V

#define SYSCTL_LDODPCTL_VLDO_1_05V    0x00000015

◆ SYSCTL_LDODPCTL_VLDO_1_10V

#define SYSCTL_LDODPCTL_VLDO_1_10V    0x00000016

◆ SYSCTL_LDODPCTL_VLDO_1_15V

#define SYSCTL_LDODPCTL_VLDO_1_15V    0x00000017

◆ SYSCTL_LDODPCTL_VLDO_1_20V

#define SYSCTL_LDODPCTL_VLDO_1_20V    0x00000018

◆ SYSCTL_LDODPCTL_VLDO_M

#define SYSCTL_LDODPCTL_VLDO_M   0x000000FF

◆ SYSCTL_LDOSPCTL_R

#define SYSCTL_LDOSPCTL_R   (*((volatile u32 *)0x400FE1B4))

◆ SYSCTL_LDOSPCTL_VADJEN

#define SYSCTL_LDOSPCTL_VADJEN   0x80000000

◆ SYSCTL_LDOSPCTL_VLDO_0_90V

#define SYSCTL_LDOSPCTL_VLDO_0_90V    0x00000012

◆ SYSCTL_LDOSPCTL_VLDO_0_95V

#define SYSCTL_LDOSPCTL_VLDO_0_95V    0x00000013

◆ SYSCTL_LDOSPCTL_VLDO_1_00V

#define SYSCTL_LDOSPCTL_VLDO_1_00V    0x00000014

◆ SYSCTL_LDOSPCTL_VLDO_1_05V

#define SYSCTL_LDOSPCTL_VLDO_1_05V    0x00000015

◆ SYSCTL_LDOSPCTL_VLDO_1_10V

#define SYSCTL_LDOSPCTL_VLDO_1_10V    0x00000016

◆ SYSCTL_LDOSPCTL_VLDO_1_15V

#define SYSCTL_LDOSPCTL_VLDO_1_15V    0x00000017

◆ SYSCTL_LDOSPCTL_VLDO_1_20V

#define SYSCTL_LDOSPCTL_VLDO_1_20V    0x00000018

◆ SYSCTL_LDOSPCTL_VLDO_M

#define SYSCTL_LDOSPCTL_VLDO_M   0x000000FF

◆ SYSCTL_MISC_BOR0MIS

#define SYSCTL_MISC_BOR0MIS   0x00000800

◆ SYSCTL_MISC_BOR1MIS

#define SYSCTL_MISC_BOR1MIS   0x00000002

◆ SYSCTL_MISC_MOFMIS

#define SYSCTL_MISC_MOFMIS   0x00000008

◆ SYSCTL_MISC_MOSCPUPMIS

#define SYSCTL_MISC_MOSCPUPMIS   0x00000100

◆ SYSCTL_MISC_PLLLMIS

#define SYSCTL_MISC_PLLLMIS   0x00000040

◆ SYSCTL_MISC_R

#define SYSCTL_MISC_R   (*((volatile u32 *)0x400FE058))

◆ SYSCTL_MISC_USBPLLLMIS

#define SYSCTL_MISC_USBPLLLMIS   0x00000080

◆ SYSCTL_MISC_VDDAMIS

#define SYSCTL_MISC_VDDAMIS   0x00000400

◆ SYSCTL_MOSCCTL_CVAL

#define SYSCTL_MOSCCTL_CVAL   0x00000001

◆ SYSCTL_MOSCCTL_MOSCIM

#define SYSCTL_MOSCCTL_MOSCIM   0x00000002

◆ SYSCTL_MOSCCTL_NOXTAL

#define SYSCTL_MOSCCTL_NOXTAL   0x00000004

◆ SYSCTL_MOSCCTL_R

#define SYSCTL_MOSCCTL_R   (*((volatile u32 *)0x400FE07C))

◆ SYSCTL_NVMSTAT_FWB

#define SYSCTL_NVMSTAT_FWB   0x00000001

◆ SYSCTL_NVMSTAT_R

#define SYSCTL_NVMSTAT_R   (*((volatile u32 *)0x400FE1A0))

◆ SYSCTL_PBORCTL_BOR0

#define SYSCTL_PBORCTL_BOR0   0x00000004

◆ SYSCTL_PBORCTL_BOR1

#define SYSCTL_PBORCTL_BOR1   0x00000002

◆ SYSCTL_PBORCTL_R

#define SYSCTL_PBORCTL_R   (*((volatile u32 *)0x400FE030))

◆ SYSCTL_PIOSCCAL_CAL

#define SYSCTL_PIOSCCAL_CAL   0x00000200

◆ SYSCTL_PIOSCCAL_R

#define SYSCTL_PIOSCCAL_R   (*((volatile u32 *)0x400FE150))

◆ SYSCTL_PIOSCCAL_UPDATE

#define SYSCTL_PIOSCCAL_UPDATE   0x00000100

◆ SYSCTL_PIOSCCAL_UT_M

#define SYSCTL_PIOSCCAL_UT_M   0x0000007F

◆ SYSCTL_PIOSCCAL_UT_S

#define SYSCTL_PIOSCCAL_UT_S   0

◆ SYSCTL_PIOSCCAL_UTEN

#define SYSCTL_PIOSCCAL_UTEN   0x80000000

◆ SYSCTL_PIOSCSTAT_CR_M

#define SYSCTL_PIOSCSTAT_CR_M   0x00000300

◆ SYSCTL_PIOSCSTAT_CRFAIL

#define SYSCTL_PIOSCSTAT_CRFAIL   0x00000200

◆ SYSCTL_PIOSCSTAT_CRNONE

#define SYSCTL_PIOSCSTAT_CRNONE   0x00000000

◆ SYSCTL_PIOSCSTAT_CRPASS

#define SYSCTL_PIOSCSTAT_CRPASS   0x00000100

◆ SYSCTL_PIOSCSTAT_CT_M

#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F

◆ SYSCTL_PIOSCSTAT_CT_S

#define SYSCTL_PIOSCSTAT_CT_S   0

◆ SYSCTL_PIOSCSTAT_DT_M

#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000

◆ SYSCTL_PIOSCSTAT_DT_S

#define SYSCTL_PIOSCSTAT_DT_S   16

◆ SYSCTL_PIOSCSTAT_R

#define SYSCTL_PIOSCSTAT_R   (*((volatile u32 *)0x400FE154))

◆ SYSCTL_PLLFREQ0_MFRAC_M

#define SYSCTL_PLLFREQ0_MFRAC_M   0x000FFC00

◆ SYSCTL_PLLFREQ0_MFRAC_S

#define SYSCTL_PLLFREQ0_MFRAC_S   10

◆ SYSCTL_PLLFREQ0_MINT_M

#define SYSCTL_PLLFREQ0_MINT_M   0x000003FF

◆ SYSCTL_PLLFREQ0_MINT_S

#define SYSCTL_PLLFREQ0_MINT_S   0

◆ SYSCTL_PLLFREQ0_R

#define SYSCTL_PLLFREQ0_R   (*((volatile u32 *)0x400FE160))

◆ SYSCTL_PLLFREQ1_N_M

#define SYSCTL_PLLFREQ1_N_M   0x0000001F

◆ SYSCTL_PLLFREQ1_N_S

#define SYSCTL_PLLFREQ1_N_S   0

◆ SYSCTL_PLLFREQ1_Q_M

#define SYSCTL_PLLFREQ1_Q_M   0x00001F00

◆ SYSCTL_PLLFREQ1_Q_S

#define SYSCTL_PLLFREQ1_Q_S   8

◆ SYSCTL_PLLFREQ1_R

#define SYSCTL_PLLFREQ1_R   (*((volatile u32 *)0x400FE164))

◆ SYSCTL_PLLSTAT_LOCK

#define SYSCTL_PLLSTAT_LOCK   0x00000001

◆ SYSCTL_PLLSTAT_R

#define SYSCTL_PLLSTAT_R   (*((volatile u32 *)0x400FE168))

◆ SYSCTL_PPACMP_P0

#define SYSCTL_PPACMP_P0   0x00000001

◆ SYSCTL_PPACMP_R

#define SYSCTL_PPACMP_R   (*((volatile u32 *)0x400FE33C))

◆ SYSCTL_PPADC_P0

#define SYSCTL_PPADC_P0   0x00000001

◆ SYSCTL_PPADC_P1

#define SYSCTL_PPADC_P1   0x00000002

◆ SYSCTL_PPADC_R

#define SYSCTL_PPADC_R   (*((volatile u32 *)0x400FE338))

◆ SYSCTL_PPCAN_P0

#define SYSCTL_PPCAN_P0   0x00000001

◆ SYSCTL_PPCAN_P1

#define SYSCTL_PPCAN_P1   0x00000002

◆ SYSCTL_PPCAN_R

#define SYSCTL_PPCAN_R   (*((volatile u32 *)0x400FE334))

◆ SYSCTL_PPDMA_P0

#define SYSCTL_PPDMA_P0   0x00000001

◆ SYSCTL_PPDMA_R

#define SYSCTL_PPDMA_R   (*((volatile u32 *)0x400FE30C))

◆ SYSCTL_PPEEPROM_P0

#define SYSCTL_PPEEPROM_P0   0x00000001

◆ SYSCTL_PPEEPROM_R

#define SYSCTL_PPEEPROM_R   (*((volatile u32 *)0x400FE358))

◆ SYSCTL_PPGPIO_P0

#define SYSCTL_PPGPIO_P0   0x00000001

◆ SYSCTL_PPGPIO_P1

#define SYSCTL_PPGPIO_P1   0x00000002

◆ SYSCTL_PPGPIO_P10

#define SYSCTL_PPGPIO_P10   0x00000400

◆ SYSCTL_PPGPIO_P11

#define SYSCTL_PPGPIO_P11   0x00000800

◆ SYSCTL_PPGPIO_P12

#define SYSCTL_PPGPIO_P12   0x00001000

◆ SYSCTL_PPGPIO_P13

#define SYSCTL_PPGPIO_P13   0x00002000

◆ SYSCTL_PPGPIO_P14

#define SYSCTL_PPGPIO_P14   0x00004000

◆ SYSCTL_PPGPIO_P2

#define SYSCTL_PPGPIO_P2   0x00000004

◆ SYSCTL_PPGPIO_P3

#define SYSCTL_PPGPIO_P3   0x00000008

◆ SYSCTL_PPGPIO_P4

#define SYSCTL_PPGPIO_P4   0x00000010

◆ SYSCTL_PPGPIO_P5

#define SYSCTL_PPGPIO_P5   0x00000020

◆ SYSCTL_PPGPIO_P6

#define SYSCTL_PPGPIO_P6   0x00000040

◆ SYSCTL_PPGPIO_P7

#define SYSCTL_PPGPIO_P7   0x00000080

◆ SYSCTL_PPGPIO_P8

#define SYSCTL_PPGPIO_P8   0x00000100

◆ SYSCTL_PPGPIO_P9

#define SYSCTL_PPGPIO_P9   0x00000200

◆ SYSCTL_PPGPIO_R

#define SYSCTL_PPGPIO_R   (*((volatile u32 *)0x400FE308))

◆ SYSCTL_PPHIB_P0

#define SYSCTL_PPHIB_P0   0x00000001

◆ SYSCTL_PPHIB_R

#define SYSCTL_PPHIB_R   (*((volatile u32 *)0x400FE314))

◆ SYSCTL_PPI2C_P0

#define SYSCTL_PPI2C_P0   0x00000001

◆ SYSCTL_PPI2C_P1

#define SYSCTL_PPI2C_P1   0x00000002

◆ SYSCTL_PPI2C_P2

#define SYSCTL_PPI2C_P2   0x00000004

◆ SYSCTL_PPI2C_P3

#define SYSCTL_PPI2C_P3   0x00000008

◆ SYSCTL_PPI2C_P4

#define SYSCTL_PPI2C_P4   0x00000010

◆ SYSCTL_PPI2C_P5

#define SYSCTL_PPI2C_P5   0x00000020

◆ SYSCTL_PPI2C_R

#define SYSCTL_PPI2C_R   (*((volatile u32 *)0x400FE320))

◆ SYSCTL_PPPWM_P0

#define SYSCTL_PPPWM_P0   0x00000001

◆ SYSCTL_PPPWM_P1

#define SYSCTL_PPPWM_P1   0x00000002

◆ SYSCTL_PPPWM_R

#define SYSCTL_PPPWM_R   (*((volatile u32 *)0x400FE340))

◆ SYSCTL_PPQEI_P0

#define SYSCTL_PPQEI_P0   0x00000001

◆ SYSCTL_PPQEI_P1

#define SYSCTL_PPQEI_P1   0x00000002

◆ SYSCTL_PPQEI_R

#define SYSCTL_PPQEI_R   (*((volatile u32 *)0x400FE344))

◆ SYSCTL_PPSSI_P0

#define SYSCTL_PPSSI_P0   0x00000001

◆ SYSCTL_PPSSI_P1

#define SYSCTL_PPSSI_P1   0x00000002

◆ SYSCTL_PPSSI_P2

#define SYSCTL_PPSSI_P2   0x00000004

◆ SYSCTL_PPSSI_P3

#define SYSCTL_PPSSI_P3   0x00000008

◆ SYSCTL_PPSSI_R

#define SYSCTL_PPSSI_R   (*((volatile u32 *)0x400FE31C))

◆ SYSCTL_PPTIMER_P0

#define SYSCTL_PPTIMER_P0   0x00000001

◆ SYSCTL_PPTIMER_P1

#define SYSCTL_PPTIMER_P1   0x00000002

◆ SYSCTL_PPTIMER_P2

#define SYSCTL_PPTIMER_P2   0x00000004

◆ SYSCTL_PPTIMER_P3

#define SYSCTL_PPTIMER_P3   0x00000008

◆ SYSCTL_PPTIMER_P4

#define SYSCTL_PPTIMER_P4   0x00000010

◆ SYSCTL_PPTIMER_P5

#define SYSCTL_PPTIMER_P5   0x00000020

◆ SYSCTL_PPTIMER_R

#define SYSCTL_PPTIMER_R   (*((volatile u32 *)0x400FE304))

◆ SYSCTL_PPUART_P0

#define SYSCTL_PPUART_P0   0x00000001

◆ SYSCTL_PPUART_P1

#define SYSCTL_PPUART_P1   0x00000002

◆ SYSCTL_PPUART_P2

#define SYSCTL_PPUART_P2   0x00000004

◆ SYSCTL_PPUART_P3

#define SYSCTL_PPUART_P3   0x00000008

◆ SYSCTL_PPUART_P4

#define SYSCTL_PPUART_P4   0x00000010

◆ SYSCTL_PPUART_P5

#define SYSCTL_PPUART_P5   0x00000020

◆ SYSCTL_PPUART_P6

#define SYSCTL_PPUART_P6   0x00000040

◆ SYSCTL_PPUART_P7

#define SYSCTL_PPUART_P7   0x00000080

◆ SYSCTL_PPUART_R

#define SYSCTL_PPUART_R   (*((volatile u32 *)0x400FE318))

◆ SYSCTL_PPUSB_P0

#define SYSCTL_PPUSB_P0   0x00000001

◆ SYSCTL_PPUSB_R

#define SYSCTL_PPUSB_R   (*((volatile u32 *)0x400FE328))

◆ SYSCTL_PPWD_P0

#define SYSCTL_PPWD_P0   0x00000001

◆ SYSCTL_PPWD_P1

#define SYSCTL_PPWD_P1   0x00000002

◆ SYSCTL_PPWD_R

#define SYSCTL_PPWD_R   (*((volatile u32 *)0x400FE300))

◆ SYSCTL_PPWTIMER_P0

#define SYSCTL_PPWTIMER_P0   0x00000001

◆ SYSCTL_PPWTIMER_P1

#define SYSCTL_PPWTIMER_P1   0x00000002

◆ SYSCTL_PPWTIMER_P2

#define SYSCTL_PPWTIMER_P2   0x00000004

◆ SYSCTL_PPWTIMER_P3

#define SYSCTL_PPWTIMER_P3   0x00000008

◆ SYSCTL_PPWTIMER_P4

#define SYSCTL_PPWTIMER_P4   0x00000010

◆ SYSCTL_PPWTIMER_P5

#define SYSCTL_PPWTIMER_P5   0x00000020

◆ SYSCTL_PPWTIMER_R

#define SYSCTL_PPWTIMER_R   (*((volatile u32 *)0x400FE35C))

◆ SYSCTL_PRACMP_R

#define SYSCTL_PRACMP_R   (*((volatile u32 *)0x400FEA3C))

◆ SYSCTL_PRACMP_R0

#define SYSCTL_PRACMP_R0   0x00000001

◆ SYSCTL_PRADC_R

#define SYSCTL_PRADC_R   (*((volatile u32 *)0x400FEA38))

◆ SYSCTL_PRADC_R0

#define SYSCTL_PRADC_R0   0x00000001

◆ SYSCTL_PRADC_R1

#define SYSCTL_PRADC_R1   0x00000002

◆ SYSCTL_PRCAN_R

#define SYSCTL_PRCAN_R   (*((volatile u32 *)0x400FEA34))

◆ SYSCTL_PRCAN_R0

#define SYSCTL_PRCAN_R0   0x00000001

◆ SYSCTL_PRCAN_R1

#define SYSCTL_PRCAN_R1   0x00000002

◆ SYSCTL_PRDMA_R

#define SYSCTL_PRDMA_R   (*((volatile u32 *)0x400FEA0C))

◆ SYSCTL_PRDMA_R0

#define SYSCTL_PRDMA_R0   0x00000001

◆ SYSCTL_PREEPROM_R

#define SYSCTL_PREEPROM_R   (*((volatile u32 *)0x400FEA58))

◆ SYSCTL_PREEPROM_R0

#define SYSCTL_PREEPROM_R0   0x00000001

◆ SYSCTL_PRGPIO_R

#define SYSCTL_PRGPIO_R   (*((volatile u32 *)0x400FEA08))

◆ SYSCTL_PRGPIO_R0

#define SYSCTL_PRGPIO_R0   0x00000001

◆ SYSCTL_PRGPIO_R1

#define SYSCTL_PRGPIO_R1   0x00000002

◆ SYSCTL_PRGPIO_R2

#define SYSCTL_PRGPIO_R2   0x00000004

◆ SYSCTL_PRGPIO_R3

#define SYSCTL_PRGPIO_R3   0x00000008

◆ SYSCTL_PRGPIO_R4

#define SYSCTL_PRGPIO_R4   0x00000010

◆ SYSCTL_PRGPIO_R5

#define SYSCTL_PRGPIO_R5   0x00000020

◆ SYSCTL_PRHIB_R

#define SYSCTL_PRHIB_R   (*((volatile u32 *)0x400FEA14))

◆ SYSCTL_PRHIB_R0

#define SYSCTL_PRHIB_R0   0x00000001

◆ SYSCTL_PRI2C_R

#define SYSCTL_PRI2C_R   (*((volatile u32 *)0x400FEA20))

◆ SYSCTL_PRI2C_R0

#define SYSCTL_PRI2C_R0   0x00000001

◆ SYSCTL_PRI2C_R1

#define SYSCTL_PRI2C_R1   0x00000002

◆ SYSCTL_PRI2C_R2

#define SYSCTL_PRI2C_R2   0x00000004

◆ SYSCTL_PRI2C_R3

#define SYSCTL_PRI2C_R3   0x00000008

◆ SYSCTL_PRPWM_R

#define SYSCTL_PRPWM_R   (*((volatile u32 *)0x400FEA40))

◆ SYSCTL_PRPWM_R0

#define SYSCTL_PRPWM_R0   0x00000001

◆ SYSCTL_PRPWM_R1

#define SYSCTL_PRPWM_R1   0x00000002

◆ SYSCTL_PRQEI_R

#define SYSCTL_PRQEI_R   (*((volatile u32 *)0x400FEA44))

◆ SYSCTL_PRQEI_R0

#define SYSCTL_PRQEI_R0   0x00000001

◆ SYSCTL_PRQEI_R1

#define SYSCTL_PRQEI_R1   0x00000002

◆ SYSCTL_PRSSI_R

#define SYSCTL_PRSSI_R   (*((volatile u32 *)0x400FEA1C))

◆ SYSCTL_PRSSI_R0

#define SYSCTL_PRSSI_R0   0x00000001

◆ SYSCTL_PRSSI_R1

#define SYSCTL_PRSSI_R1   0x00000002

◆ SYSCTL_PRSSI_R2

#define SYSCTL_PRSSI_R2   0x00000004

◆ SYSCTL_PRSSI_R3

#define SYSCTL_PRSSI_R3   0x00000008

◆ SYSCTL_PRTIMER_R

#define SYSCTL_PRTIMER_R   (*((volatile u32 *)0x400FEA04))

◆ SYSCTL_PRTIMER_R0

#define SYSCTL_PRTIMER_R0   0x00000001

◆ SYSCTL_PRTIMER_R1

#define SYSCTL_PRTIMER_R1   0x00000002

◆ SYSCTL_PRTIMER_R2

#define SYSCTL_PRTIMER_R2   0x00000004

◆ SYSCTL_PRTIMER_R3

#define SYSCTL_PRTIMER_R3   0x00000008

◆ SYSCTL_PRTIMER_R4

#define SYSCTL_PRTIMER_R4   0x00000010

◆ SYSCTL_PRTIMER_R5

#define SYSCTL_PRTIMER_R5   0x00000020

◆ SYSCTL_PRUART_R

#define SYSCTL_PRUART_R   (*((volatile u32 *)0x400FEA18))

◆ SYSCTL_PRUART_R0

#define SYSCTL_PRUART_R0   0x00000001

◆ SYSCTL_PRUART_R1

#define SYSCTL_PRUART_R1   0x00000002

◆ SYSCTL_PRUART_R2

#define SYSCTL_PRUART_R2   0x00000004

◆ SYSCTL_PRUART_R3

#define SYSCTL_PRUART_R3   0x00000008

◆ SYSCTL_PRUART_R4

#define SYSCTL_PRUART_R4   0x00000010

◆ SYSCTL_PRUART_R5

#define SYSCTL_PRUART_R5   0x00000020

◆ SYSCTL_PRUART_R6

#define SYSCTL_PRUART_R6   0x00000040

◆ SYSCTL_PRUART_R7

#define SYSCTL_PRUART_R7   0x00000080

◆ SYSCTL_PRUSB_R

#define SYSCTL_PRUSB_R   (*((volatile u32 *)0x400FEA28))

◆ SYSCTL_PRUSB_R0

#define SYSCTL_PRUSB_R0   0x00000001

◆ SYSCTL_PRWD_R

#define SYSCTL_PRWD_R   (*((volatile u32 *)0x400FEA00))

◆ SYSCTL_PRWD_R0

#define SYSCTL_PRWD_R0   0x00000001

◆ SYSCTL_PRWD_R1

#define SYSCTL_PRWD_R1   0x00000002

◆ SYSCTL_PRWTIMER_R

#define SYSCTL_PRWTIMER_R   (*((volatile u32 *)0x400FEA5C))

◆ SYSCTL_PRWTIMER_R0

#define SYSCTL_PRWTIMER_R0   0x00000001

◆ SYSCTL_PRWTIMER_R1

#define SYSCTL_PRWTIMER_R1   0x00000002

◆ SYSCTL_PRWTIMER_R2

#define SYSCTL_PRWTIMER_R2   0x00000004

◆ SYSCTL_PRWTIMER_R3

#define SYSCTL_PRWTIMER_R3   0x00000008

◆ SYSCTL_PRWTIMER_R4

#define SYSCTL_PRWTIMER_R4   0x00000010

◆ SYSCTL_PRWTIMER_R5

#define SYSCTL_PRWTIMER_R5   0x00000020

◆ SYSCTL_RCC2_BYPASS2

#define SYSCTL_RCC2_BYPASS2   0x00000800

◆ SYSCTL_RCC2_DIV400

#define SYSCTL_RCC2_DIV400   0x40000000

◆ SYSCTL_RCC2_OSCSRC2_30

#define SYSCTL_RCC2_OSCSRC2_30   0x00000030

◆ SYSCTL_RCC2_OSCSRC2_32

#define SYSCTL_RCC2_OSCSRC2_32   0x00000070

◆ SYSCTL_RCC2_OSCSRC2_IO

#define SYSCTL_RCC2_OSCSRC2_IO   0x00000010

◆ SYSCTL_RCC2_OSCSRC2_IO4

#define SYSCTL_RCC2_OSCSRC2_IO4   0x00000020

◆ SYSCTL_RCC2_OSCSRC2_M

#define SYSCTL_RCC2_OSCSRC2_M   0x00000070

◆ SYSCTL_RCC2_OSCSRC2_MO

#define SYSCTL_RCC2_OSCSRC2_MO   0x00000000

◆ SYSCTL_RCC2_PWRDN2

#define SYSCTL_RCC2_PWRDN2   0x00002000

◆ SYSCTL_RCC2_R

#define SYSCTL_RCC2_R   (*((volatile u32 *)0x400FE070))

◆ SYSCTL_RCC2_SYSDIV2_M

#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000

◆ SYSCTL_RCC2_SYSDIV2_S

#define SYSCTL_RCC2_SYSDIV2_S   23

◆ SYSCTL_RCC2_SYSDIV2LSB

#define SYSCTL_RCC2_SYSDIV2LSB   0x00400000

◆ SYSCTL_RCC2_USBPWRDN

#define SYSCTL_RCC2_USBPWRDN   0x00004000

◆ SYSCTL_RCC2_USERCC2

#define SYSCTL_RCC2_USERCC2   0x80000000

◆ SYSCTL_RCC_ACG

#define SYSCTL_RCC_ACG   0x08000000

◆ SYSCTL_RCC_BYPASS

#define SYSCTL_RCC_BYPASS   0x00000800

◆ SYSCTL_RCC_MOSCDIS

#define SYSCTL_RCC_MOSCDIS   0x00000001

◆ SYSCTL_RCC_OSCSRC_30

#define SYSCTL_RCC_OSCSRC_30   0x00000030

◆ SYSCTL_RCC_OSCSRC_INT

#define SYSCTL_RCC_OSCSRC_INT   0x00000010

◆ SYSCTL_RCC_OSCSRC_INT4

#define SYSCTL_RCC_OSCSRC_INT4   0x00000020

◆ SYSCTL_RCC_OSCSRC_M

#define SYSCTL_RCC_OSCSRC_M   0x00000030

◆ SYSCTL_RCC_OSCSRC_MAIN

#define SYSCTL_RCC_OSCSRC_MAIN   0x00000000

◆ SYSCTL_RCC_PWMDIV_16

#define SYSCTL_RCC_PWMDIV_16   0x00060000

◆ SYSCTL_RCC_PWMDIV_2

#define SYSCTL_RCC_PWMDIV_2   0x00000000

◆ SYSCTL_RCC_PWMDIV_32

#define SYSCTL_RCC_PWMDIV_32   0x00080000

◆ SYSCTL_RCC_PWMDIV_4

#define SYSCTL_RCC_PWMDIV_4   0x00020000

◆ SYSCTL_RCC_PWMDIV_64

#define SYSCTL_RCC_PWMDIV_64   0x000A0000

◆ SYSCTL_RCC_PWMDIV_8

#define SYSCTL_RCC_PWMDIV_8   0x00040000

◆ SYSCTL_RCC_PWMDIV_M

#define SYSCTL_RCC_PWMDIV_M   0x000E0000

◆ SYSCTL_RCC_PWRDN

#define SYSCTL_RCC_PWRDN   0x00002000

◆ SYSCTL_RCC_R

#define SYSCTL_RCC_R   (*((volatile u32 *)0x400FE060))

◆ SYSCTL_RCC_SYSDIV_M

#define SYSCTL_RCC_SYSDIV_M   0x07800000

◆ SYSCTL_RCC_SYSDIV_S

#define SYSCTL_RCC_SYSDIV_S   23

◆ SYSCTL_RCC_USEPWMDIV

#define SYSCTL_RCC_USEPWMDIV   0x00100000

◆ SYSCTL_RCC_USESYSDIV

#define SYSCTL_RCC_USESYSDIV   0x00400000

◆ SYSCTL_RCC_XTAL_10MHZ

#define SYSCTL_RCC_XTAL_10MHZ   0x00000400

◆ SYSCTL_RCC_XTAL_12_2MHZ

#define SYSCTL_RCC_XTAL_12_2MHZ   0x00000480

◆ SYSCTL_RCC_XTAL_12MHZ

#define SYSCTL_RCC_XTAL_12MHZ   0x00000440

◆ SYSCTL_RCC_XTAL_13_5MHZ

#define SYSCTL_RCC_XTAL_13_5MHZ   0x000004C0

◆ SYSCTL_RCC_XTAL_14_3MHZ

#define SYSCTL_RCC_XTAL_14_3MHZ   0x00000500

◆ SYSCTL_RCC_XTAL_16_3MHZ

#define SYSCTL_RCC_XTAL_16_3MHZ   0x00000580

◆ SYSCTL_RCC_XTAL_16MHZ

#define SYSCTL_RCC_XTAL_16MHZ   0x00000540

◆ SYSCTL_RCC_XTAL_18MHZ

#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0

◆ SYSCTL_RCC_XTAL_20MHZ

#define SYSCTL_RCC_XTAL_20MHZ   0x00000600

◆ SYSCTL_RCC_XTAL_24MHZ

#define SYSCTL_RCC_XTAL_24MHZ   0x00000640

◆ SYSCTL_RCC_XTAL_25MHZ

#define SYSCTL_RCC_XTAL_25MHZ   0x00000680

◆ SYSCTL_RCC_XTAL_4_09MHZ

#define SYSCTL_RCC_XTAL_4_09MHZ   0x000001C0

◆ SYSCTL_RCC_XTAL_4_91MHZ

#define SYSCTL_RCC_XTAL_4_91MHZ   0x00000200

◆ SYSCTL_RCC_XTAL_4MHZ

#define SYSCTL_RCC_XTAL_4MHZ   0x00000180

◆ SYSCTL_RCC_XTAL_5_12MHZ

#define SYSCTL_RCC_XTAL_5_12MHZ   0x00000280

◆ SYSCTL_RCC_XTAL_5MHZ

#define SYSCTL_RCC_XTAL_5MHZ   0x00000240

◆ SYSCTL_RCC_XTAL_6_14MHZ

#define SYSCTL_RCC_XTAL_6_14MHZ   0x00000300

◆ SYSCTL_RCC_XTAL_6MHZ

#define SYSCTL_RCC_XTAL_6MHZ   0x000002C0

◆ SYSCTL_RCC_XTAL_7_37MHZ

#define SYSCTL_RCC_XTAL_7_37MHZ   0x00000340

◆ SYSCTL_RCC_XTAL_8_19MHZ

#define SYSCTL_RCC_XTAL_8_19MHZ   0x000003C0

◆ SYSCTL_RCC_XTAL_8MHZ

#define SYSCTL_RCC_XTAL_8MHZ   0x00000380

◆ SYSCTL_RCC_XTAL_M

#define SYSCTL_RCC_XTAL_M   0x000007C0

◆ SYSCTL_RCGC0_ADC0

#define SYSCTL_RCGC0_ADC0   0x00010000

◆ SYSCTL_RCGC0_ADC0SPD_125K

#define SYSCTL_RCGC0_ADC0SPD_125K    0x00000000

◆ SYSCTL_RCGC0_ADC0SPD_1M

#define SYSCTL_RCGC0_ADC0SPD_1M   0x00000300

◆ SYSCTL_RCGC0_ADC0SPD_250K

#define SYSCTL_RCGC0_ADC0SPD_250K    0x00000100

◆ SYSCTL_RCGC0_ADC0SPD_500K

#define SYSCTL_RCGC0_ADC0SPD_500K    0x00000200

◆ SYSCTL_RCGC0_ADC0SPD_M

#define SYSCTL_RCGC0_ADC0SPD_M   0x00000300

◆ SYSCTL_RCGC0_ADC1

#define SYSCTL_RCGC0_ADC1   0x00020000

◆ SYSCTL_RCGC0_ADC1SPD_125K

#define SYSCTL_RCGC0_ADC1SPD_125K    0x00000000

◆ SYSCTL_RCGC0_ADC1SPD_1M

#define SYSCTL_RCGC0_ADC1SPD_1M   0x00000C00

◆ SYSCTL_RCGC0_ADC1SPD_250K

#define SYSCTL_RCGC0_ADC1SPD_250K    0x00000400

◆ SYSCTL_RCGC0_ADC1SPD_500K

#define SYSCTL_RCGC0_ADC1SPD_500K    0x00000800

◆ SYSCTL_RCGC0_ADC1SPD_M

#define SYSCTL_RCGC0_ADC1SPD_M   0x00000C00

◆ SYSCTL_RCGC0_CAN0

#define SYSCTL_RCGC0_CAN0   0x01000000

◆ SYSCTL_RCGC0_CAN1

#define SYSCTL_RCGC0_CAN1   0x02000000

◆ SYSCTL_RCGC0_HIB

#define SYSCTL_RCGC0_HIB   0x00000040

◆ SYSCTL_RCGC0_PWM0

#define SYSCTL_RCGC0_PWM0   0x00100000

◆ SYSCTL_RCGC0_R

#define SYSCTL_RCGC0_R   (*((volatile u32 *)0x400FE100))

◆ SYSCTL_RCGC0_WDT0

#define SYSCTL_RCGC0_WDT0   0x00000008

◆ SYSCTL_RCGC0_WDT1

#define SYSCTL_RCGC0_WDT1   0x10000000

◆ SYSCTL_RCGC1_COMP0

#define SYSCTL_RCGC1_COMP0   0x01000000

◆ SYSCTL_RCGC1_COMP1

#define SYSCTL_RCGC1_COMP1   0x02000000

◆ SYSCTL_RCGC1_I2C0

#define SYSCTL_RCGC1_I2C0   0x00001000

◆ SYSCTL_RCGC1_I2C1

#define SYSCTL_RCGC1_I2C1   0x00004000

◆ SYSCTL_RCGC1_QEI0

#define SYSCTL_RCGC1_QEI0   0x00000100

◆ SYSCTL_RCGC1_QEI1

#define SYSCTL_RCGC1_QEI1   0x00000200

◆ SYSCTL_RCGC1_R

#define SYSCTL_RCGC1_R   (*((volatile u32 *)0x400FE104))

◆ SYSCTL_RCGC1_SSI0

#define SYSCTL_RCGC1_SSI0   0x00000010

◆ SYSCTL_RCGC1_SSI1

#define SYSCTL_RCGC1_SSI1   0x00000020

◆ SYSCTL_RCGC1_TIMER0

#define SYSCTL_RCGC1_TIMER0   0x00010000

◆ SYSCTL_RCGC1_TIMER1

#define SYSCTL_RCGC1_TIMER1   0x00020000

◆ SYSCTL_RCGC1_TIMER2

#define SYSCTL_RCGC1_TIMER2   0x00040000

◆ SYSCTL_RCGC1_TIMER3

#define SYSCTL_RCGC1_TIMER3   0x00080000

◆ SYSCTL_RCGC1_UART0

#define SYSCTL_RCGC1_UART0   0x00000001

◆ SYSCTL_RCGC1_UART1

#define SYSCTL_RCGC1_UART1   0x00000002

◆ SYSCTL_RCGC1_UART2

#define SYSCTL_RCGC1_UART2   0x00000004

◆ SYSCTL_RCGC2_GPIOA

#define SYSCTL_RCGC2_GPIOA   0x00000001

◆ SYSCTL_RCGC2_GPIOB

#define SYSCTL_RCGC2_GPIOB   0x00000002

◆ SYSCTL_RCGC2_GPIOC

#define SYSCTL_RCGC2_GPIOC   0x00000004

◆ SYSCTL_RCGC2_GPIOD

#define SYSCTL_RCGC2_GPIOD   0x00000008

◆ SYSCTL_RCGC2_GPIOE

#define SYSCTL_RCGC2_GPIOE   0x00000010

◆ SYSCTL_RCGC2_GPIOF

#define SYSCTL_RCGC2_GPIOF   0x00000020

◆ SYSCTL_RCGC2_R

#define SYSCTL_RCGC2_R   (*((volatile u32 *)0x400FE108))

◆ SYSCTL_RCGC2_UDMA

#define SYSCTL_RCGC2_UDMA   0x00002000

◆ SYSCTL_RCGC2_USB0

#define SYSCTL_RCGC2_USB0   0x00010000

◆ SYSCTL_RCGCACMP_R

#define SYSCTL_RCGCACMP_R   (*((volatile u32 *)0x400FE63C))

◆ SYSCTL_RCGCACMP_R0

#define SYSCTL_RCGCACMP_R0   0x00000001

◆ SYSCTL_RCGCADC_R

#define SYSCTL_RCGCADC_R   (*((volatile u32 *)0x400FE638))

◆ SYSCTL_RCGCADC_R0

#define SYSCTL_RCGCADC_R0   0x00000001

◆ SYSCTL_RCGCADC_R1

#define SYSCTL_RCGCADC_R1   0x00000002

◆ SYSCTL_RCGCCAN_R

#define SYSCTL_RCGCCAN_R   (*((volatile u32 *)0x400FE634))

◆ SYSCTL_RCGCCAN_R0

#define SYSCTL_RCGCCAN_R0   0x00000001

◆ SYSCTL_RCGCCAN_R1

#define SYSCTL_RCGCCAN_R1   0x00000002

◆ SYSCTL_RCGCDMA_R

#define SYSCTL_RCGCDMA_R   (*((volatile u32 *)0x400FE60C))

◆ SYSCTL_RCGCDMA_R0

#define SYSCTL_RCGCDMA_R0   0x00000001

◆ SYSCTL_RCGCEEPROM_R

#define SYSCTL_RCGCEEPROM_R   (*((volatile u32 *)0x400FE658))

◆ SYSCTL_RCGCEEPROM_R0

#define SYSCTL_RCGCEEPROM_R0   0x00000001

◆ SYSCTL_RCGCGPIO_R

#define SYSCTL_RCGCGPIO_R   (*((volatile u32 *)0x400FE608))

◆ SYSCTL_RCGCGPIO_R0

#define SYSCTL_RCGCGPIO_R0   0x00000001

◆ SYSCTL_RCGCGPIO_R1

#define SYSCTL_RCGCGPIO_R1   0x00000002

◆ SYSCTL_RCGCGPIO_R2

#define SYSCTL_RCGCGPIO_R2   0x00000004

◆ SYSCTL_RCGCGPIO_R3

#define SYSCTL_RCGCGPIO_R3   0x00000008

◆ SYSCTL_RCGCGPIO_R4

#define SYSCTL_RCGCGPIO_R4   0x00000010

◆ SYSCTL_RCGCGPIO_R5

#define SYSCTL_RCGCGPIO_R5   0x00000020

◆ SYSCTL_RCGCHIB_R

#define SYSCTL_RCGCHIB_R   (*((volatile u32 *)0x400FE614))

◆ SYSCTL_RCGCHIB_R0

#define SYSCTL_RCGCHIB_R0   0x00000001

◆ SYSCTL_RCGCI2C_R

#define SYSCTL_RCGCI2C_R   (*((volatile u32 *)0x400FE620))

◆ SYSCTL_RCGCI2C_R0

#define SYSCTL_RCGCI2C_R0   0x00000001

◆ SYSCTL_RCGCI2C_R1

#define SYSCTL_RCGCI2C_R1   0x00000002

◆ SYSCTL_RCGCI2C_R2

#define SYSCTL_RCGCI2C_R2   0x00000004

◆ SYSCTL_RCGCI2C_R3

#define SYSCTL_RCGCI2C_R3   0x00000008

◆ SYSCTL_RCGCPWM_R

#define SYSCTL_RCGCPWM_R   (*((volatile u32 *)0x400FE640))

◆ SYSCTL_RCGCPWM_R0

#define SYSCTL_RCGCPWM_R0   0x00000001

◆ SYSCTL_RCGCPWM_R1

#define SYSCTL_RCGCPWM_R1   0x00000002

◆ SYSCTL_RCGCQEI_R

#define SYSCTL_RCGCQEI_R   (*((volatile u32 *)0x400FE644))

◆ SYSCTL_RCGCQEI_R0

#define SYSCTL_RCGCQEI_R0   0x00000001

◆ SYSCTL_RCGCQEI_R1

#define SYSCTL_RCGCQEI_R1   0x00000002

◆ SYSCTL_RCGCSSI_R

#define SYSCTL_RCGCSSI_R   (*((volatile u32 *)0x400FE61C))

◆ SYSCTL_RCGCSSI_R0

#define SYSCTL_RCGCSSI_R0   0x00000001

◆ SYSCTL_RCGCSSI_R1

#define SYSCTL_RCGCSSI_R1   0x00000002

◆ SYSCTL_RCGCSSI_R2

#define SYSCTL_RCGCSSI_R2   0x00000004

◆ SYSCTL_RCGCSSI_R3

#define SYSCTL_RCGCSSI_R3   0x00000008

◆ SYSCTL_RCGCTIMER_R

#define SYSCTL_RCGCTIMER_R   (*((volatile u32 *)0x400FE604))

◆ SYSCTL_RCGCTIMER_R0

#define SYSCTL_RCGCTIMER_R0   0x00000001

◆ SYSCTL_RCGCTIMER_R1

#define SYSCTL_RCGCTIMER_R1   0x00000002

◆ SYSCTL_RCGCTIMER_R2

#define SYSCTL_RCGCTIMER_R2   0x00000004

◆ SYSCTL_RCGCTIMER_R3

#define SYSCTL_RCGCTIMER_R3   0x00000008

◆ SYSCTL_RCGCTIMER_R4

#define SYSCTL_RCGCTIMER_R4   0x00000010

◆ SYSCTL_RCGCTIMER_R5

#define SYSCTL_RCGCTIMER_R5   0x00000020

◆ SYSCTL_RCGCUART_R

#define SYSCTL_RCGCUART_R   (*((volatile u32 *)0x400FE618))

◆ SYSCTL_RCGCUART_R0

#define SYSCTL_RCGCUART_R0   0x00000001

◆ SYSCTL_RCGCUART_R1

#define SYSCTL_RCGCUART_R1   0x00000002

◆ SYSCTL_RCGCUART_R2

#define SYSCTL_RCGCUART_R2   0x00000004

◆ SYSCTL_RCGCUART_R3

#define SYSCTL_RCGCUART_R3   0x00000008

◆ SYSCTL_RCGCUART_R4

#define SYSCTL_RCGCUART_R4   0x00000010

◆ SYSCTL_RCGCUART_R5

#define SYSCTL_RCGCUART_R5   0x00000020

◆ SYSCTL_RCGCUART_R6

#define SYSCTL_RCGCUART_R6   0x00000040

◆ SYSCTL_RCGCUART_R7

#define SYSCTL_RCGCUART_R7   0x00000080

◆ SYSCTL_RCGCUSB_R

#define SYSCTL_RCGCUSB_R   (*((volatile u32 *)0x400FE628))

◆ SYSCTL_RCGCUSB_R0

#define SYSCTL_RCGCUSB_R0   0x00000001

◆ SYSCTL_RCGCWD_R

#define SYSCTL_RCGCWD_R   (*((volatile u32 *)0x400FE600))

◆ SYSCTL_RCGCWD_R0

#define SYSCTL_RCGCWD_R0   0x00000001

◆ SYSCTL_RCGCWD_R1

#define SYSCTL_RCGCWD_R1   0x00000002

◆ SYSCTL_RCGCWTIMER_R

#define SYSCTL_RCGCWTIMER_R   (*((volatile u32 *)0x400FE65C))

◆ SYSCTL_RCGCWTIMER_R0

#define SYSCTL_RCGCWTIMER_R0   0x00000001

◆ SYSCTL_RCGCWTIMER_R1

#define SYSCTL_RCGCWTIMER_R1   0x00000002

◆ SYSCTL_RCGCWTIMER_R2

#define SYSCTL_RCGCWTIMER_R2   0x00000004

◆ SYSCTL_RCGCWTIMER_R3

#define SYSCTL_RCGCWTIMER_R3   0x00000008

◆ SYSCTL_RCGCWTIMER_R4

#define SYSCTL_RCGCWTIMER_R4   0x00000010

◆ SYSCTL_RCGCWTIMER_R5

#define SYSCTL_RCGCWTIMER_R5   0x00000020

◆ SYSCTL_RESC_BOR

#define SYSCTL_RESC_BOR   0x00000004

◆ SYSCTL_RESC_EXT

#define SYSCTL_RESC_EXT   0x00000001

◆ SYSCTL_RESC_MOSCFAIL

#define SYSCTL_RESC_MOSCFAIL   0x00010000

◆ SYSCTL_RESC_POR

#define SYSCTL_RESC_POR   0x00000002

◆ SYSCTL_RESC_R

#define SYSCTL_RESC_R   (*((volatile u32 *)0x400FE05C))

◆ SYSCTL_RESC_SW

#define SYSCTL_RESC_SW   0x00000010

◆ SYSCTL_RESC_WDT0

#define SYSCTL_RESC_WDT0   0x00000008

◆ SYSCTL_RESC_WDT1

#define SYSCTL_RESC_WDT1   0x00000020

◆ SYSCTL_RIS_BOR0RIS

#define SYSCTL_RIS_BOR0RIS   0x00000800

◆ SYSCTL_RIS_BOR1RIS

#define SYSCTL_RIS_BOR1RIS   0x00000002

◆ SYSCTL_RIS_MOFRIS

#define SYSCTL_RIS_MOFRIS   0x00000008

◆ SYSCTL_RIS_MOSCPUPRIS

#define SYSCTL_RIS_MOSCPUPRIS   0x00000100

◆ SYSCTL_RIS_PLLLRIS

#define SYSCTL_RIS_PLLLRIS   0x00000040

◆ SYSCTL_RIS_R

#define SYSCTL_RIS_R   (*((volatile u32 *)0x400FE050))

◆ SYSCTL_RIS_USBPLLLRIS

#define SYSCTL_RIS_USBPLLLRIS   0x00000080

◆ SYSCTL_RIS_VDDARIS

#define SYSCTL_RIS_VDDARIS   0x00000400

◆ SYSCTL_SCGC0_ADC0

#define SYSCTL_SCGC0_ADC0   0x00010000

◆ SYSCTL_SCGC0_ADC1

#define SYSCTL_SCGC0_ADC1   0x00020000

◆ SYSCTL_SCGC0_CAN0

#define SYSCTL_SCGC0_CAN0   0x01000000

◆ SYSCTL_SCGC0_CAN1

#define SYSCTL_SCGC0_CAN1   0x02000000

◆ SYSCTL_SCGC0_HIB

#define SYSCTL_SCGC0_HIB   0x00000040

◆ SYSCTL_SCGC0_PWM0

#define SYSCTL_SCGC0_PWM0   0x00100000

◆ SYSCTL_SCGC0_R

#define SYSCTL_SCGC0_R   (*((volatile u32 *)0x400FE110))

◆ SYSCTL_SCGC0_WDT0

#define SYSCTL_SCGC0_WDT0   0x00000008

◆ SYSCTL_SCGC0_WDT1

#define SYSCTL_SCGC0_WDT1   0x10000000

◆ SYSCTL_SCGC1_COMP0

#define SYSCTL_SCGC1_COMP0   0x01000000

◆ SYSCTL_SCGC1_COMP1

#define SYSCTL_SCGC1_COMP1   0x02000000

◆ SYSCTL_SCGC1_I2C0

#define SYSCTL_SCGC1_I2C0   0x00001000

◆ SYSCTL_SCGC1_I2C1

#define SYSCTL_SCGC1_I2C1   0x00004000

◆ SYSCTL_SCGC1_QEI0

#define SYSCTL_SCGC1_QEI0   0x00000100

◆ SYSCTL_SCGC1_QEI1

#define SYSCTL_SCGC1_QEI1   0x00000200

◆ SYSCTL_SCGC1_R

#define SYSCTL_SCGC1_R   (*((volatile u32 *)0x400FE114))

◆ SYSCTL_SCGC1_SSI0

#define SYSCTL_SCGC1_SSI0   0x00000010

◆ SYSCTL_SCGC1_SSI1

#define SYSCTL_SCGC1_SSI1   0x00000020

◆ SYSCTL_SCGC1_TIMER0

#define SYSCTL_SCGC1_TIMER0   0x00010000

◆ SYSCTL_SCGC1_TIMER1

#define SYSCTL_SCGC1_TIMER1   0x00020000

◆ SYSCTL_SCGC1_TIMER2

#define SYSCTL_SCGC1_TIMER2   0x00040000

◆ SYSCTL_SCGC1_TIMER3

#define SYSCTL_SCGC1_TIMER3   0x00080000

◆ SYSCTL_SCGC1_UART0

#define SYSCTL_SCGC1_UART0   0x00000001

◆ SYSCTL_SCGC1_UART1

#define SYSCTL_SCGC1_UART1   0x00000002

◆ SYSCTL_SCGC1_UART2

#define SYSCTL_SCGC1_UART2   0x00000004

◆ SYSCTL_SCGC2_GPIOA

#define SYSCTL_SCGC2_GPIOA   0x00000001

◆ SYSCTL_SCGC2_GPIOB

#define SYSCTL_SCGC2_GPIOB   0x00000002

◆ SYSCTL_SCGC2_GPIOC

#define SYSCTL_SCGC2_GPIOC   0x00000004

◆ SYSCTL_SCGC2_GPIOD

#define SYSCTL_SCGC2_GPIOD   0x00000008

◆ SYSCTL_SCGC2_GPIOE

#define SYSCTL_SCGC2_GPIOE   0x00000010

◆ SYSCTL_SCGC2_GPIOF

#define SYSCTL_SCGC2_GPIOF   0x00000020

◆ SYSCTL_SCGC2_R

#define SYSCTL_SCGC2_R   (*((volatile u32 *)0x400FE118))

◆ SYSCTL_SCGC2_UDMA

#define SYSCTL_SCGC2_UDMA   0x00002000

◆ SYSCTL_SCGC2_USB0

#define SYSCTL_SCGC2_USB0   0x00010000

◆ SYSCTL_SCGCACMP_R

#define SYSCTL_SCGCACMP_R   (*((volatile u32 *)0x400FE73C))

◆ SYSCTL_SCGCACMP_S0

#define SYSCTL_SCGCACMP_S0   0x00000001

◆ SYSCTL_SCGCADC_R

#define SYSCTL_SCGCADC_R   (*((volatile u32 *)0x400FE738))

◆ SYSCTL_SCGCADC_S0

#define SYSCTL_SCGCADC_S0   0x00000001

◆ SYSCTL_SCGCADC_S1

#define SYSCTL_SCGCADC_S1   0x00000002

◆ SYSCTL_SCGCCAN_R

#define SYSCTL_SCGCCAN_R   (*((volatile u32 *)0x400FE734))

◆ SYSCTL_SCGCCAN_S0

#define SYSCTL_SCGCCAN_S0   0x00000001

◆ SYSCTL_SCGCCAN_S1

#define SYSCTL_SCGCCAN_S1   0x00000002

◆ SYSCTL_SCGCDMA_R

#define SYSCTL_SCGCDMA_R   (*((volatile u32 *)0x400FE70C))

◆ SYSCTL_SCGCDMA_S0

#define SYSCTL_SCGCDMA_S0   0x00000001

◆ SYSCTL_SCGCEEPROM_R

#define SYSCTL_SCGCEEPROM_R   (*((volatile u32 *)0x400FE758))

◆ SYSCTL_SCGCEEPROM_S0

#define SYSCTL_SCGCEEPROM_S0   0x00000001

◆ SYSCTL_SCGCGPIO_R

#define SYSCTL_SCGCGPIO_R   (*((volatile u32 *)0x400FE708))

◆ SYSCTL_SCGCGPIO_S0

#define SYSCTL_SCGCGPIO_S0   0x00000001

◆ SYSCTL_SCGCGPIO_S1

#define SYSCTL_SCGCGPIO_S1   0x00000002

◆ SYSCTL_SCGCGPIO_S2

#define SYSCTL_SCGCGPIO_S2   0x00000004

◆ SYSCTL_SCGCGPIO_S3

#define SYSCTL_SCGCGPIO_S3   0x00000008

◆ SYSCTL_SCGCGPIO_S4

#define SYSCTL_SCGCGPIO_S4   0x00000010

◆ SYSCTL_SCGCGPIO_S5

#define SYSCTL_SCGCGPIO_S5   0x00000020

◆ SYSCTL_SCGCHIB_R

#define SYSCTL_SCGCHIB_R   (*((volatile u32 *)0x400FE714))

◆ SYSCTL_SCGCHIB_S0

#define SYSCTL_SCGCHIB_S0   0x00000001

◆ SYSCTL_SCGCI2C_R

#define SYSCTL_SCGCI2C_R   (*((volatile u32 *)0x400FE720))

◆ SYSCTL_SCGCI2C_S0

#define SYSCTL_SCGCI2C_S0   0x00000001

◆ SYSCTL_SCGCI2C_S1

#define SYSCTL_SCGCI2C_S1   0x00000002

◆ SYSCTL_SCGCI2C_S2

#define SYSCTL_SCGCI2C_S2   0x00000004

◆ SYSCTL_SCGCI2C_S3

#define SYSCTL_SCGCI2C_S3   0x00000008

◆ SYSCTL_SCGCPWM_R

#define SYSCTL_SCGCPWM_R   (*((volatile u32 *)0x400FE740))

◆ SYSCTL_SCGCPWM_S0

#define SYSCTL_SCGCPWM_S0   0x00000001

◆ SYSCTL_SCGCPWM_S1

#define SYSCTL_SCGCPWM_S1   0x00000002

◆ SYSCTL_SCGCQEI_R

#define SYSCTL_SCGCQEI_R   (*((volatile u32 *)0x400FE744))

◆ SYSCTL_SCGCQEI_S0

#define SYSCTL_SCGCQEI_S0   0x00000001

◆ SYSCTL_SCGCQEI_S1

#define SYSCTL_SCGCQEI_S1   0x00000002

◆ SYSCTL_SCGCSSI_R

#define SYSCTL_SCGCSSI_R   (*((volatile u32 *)0x400FE71C))

◆ SYSCTL_SCGCSSI_S0

#define SYSCTL_SCGCSSI_S0   0x00000001

◆ SYSCTL_SCGCSSI_S1

#define SYSCTL_SCGCSSI_S1   0x00000002

◆ SYSCTL_SCGCSSI_S2

#define SYSCTL_SCGCSSI_S2   0x00000004

◆ SYSCTL_SCGCSSI_S3

#define SYSCTL_SCGCSSI_S3   0x00000008

◆ SYSCTL_SCGCTIMER_R

#define SYSCTL_SCGCTIMER_R   (*((volatile u32 *)0x400FE704))

◆ SYSCTL_SCGCTIMER_S0

#define SYSCTL_SCGCTIMER_S0   0x00000001

◆ SYSCTL_SCGCTIMER_S1

#define SYSCTL_SCGCTIMER_S1   0x00000002

◆ SYSCTL_SCGCTIMER_S2

#define SYSCTL_SCGCTIMER_S2   0x00000004

◆ SYSCTL_SCGCTIMER_S3

#define SYSCTL_SCGCTIMER_S3   0x00000008

◆ SYSCTL_SCGCTIMER_S4

#define SYSCTL_SCGCTIMER_S4   0x00000010

◆ SYSCTL_SCGCTIMER_S5

#define SYSCTL_SCGCTIMER_S5   0x00000020

◆ SYSCTL_SCGCUART_R

#define SYSCTL_SCGCUART_R   (*((volatile u32 *)0x400FE718))

◆ SYSCTL_SCGCUART_S0

#define SYSCTL_SCGCUART_S0   0x00000001

◆ SYSCTL_SCGCUART_S1

#define SYSCTL_SCGCUART_S1   0x00000002

◆ SYSCTL_SCGCUART_S2

#define SYSCTL_SCGCUART_S2   0x00000004

◆ SYSCTL_SCGCUART_S3

#define SYSCTL_SCGCUART_S3   0x00000008

◆ SYSCTL_SCGCUART_S4

#define SYSCTL_SCGCUART_S4   0x00000010

◆ SYSCTL_SCGCUART_S5

#define SYSCTL_SCGCUART_S5   0x00000020

◆ SYSCTL_SCGCUART_S6

#define SYSCTL_SCGCUART_S6   0x00000040

◆ SYSCTL_SCGCUART_S7

#define SYSCTL_SCGCUART_S7   0x00000080

◆ SYSCTL_SCGCUSB_R

#define SYSCTL_SCGCUSB_R   (*((volatile u32 *)0x400FE728))

◆ SYSCTL_SCGCUSB_S0

#define SYSCTL_SCGCUSB_S0   0x00000001

◆ SYSCTL_SCGCWD_R

#define SYSCTL_SCGCWD_R   (*((volatile u32 *)0x400FE700))

◆ SYSCTL_SCGCWD_S0

#define SYSCTL_SCGCWD_S0   0x00000001

◆ SYSCTL_SCGCWD_S1

#define SYSCTL_SCGCWD_S1   0x00000002

◆ SYSCTL_SCGCWTIMER_R

#define SYSCTL_SCGCWTIMER_R   (*((volatile u32 *)0x400FE75C))

◆ SYSCTL_SCGCWTIMER_S0

#define SYSCTL_SCGCWTIMER_S0   0x00000001

◆ SYSCTL_SCGCWTIMER_S1

#define SYSCTL_SCGCWTIMER_S1   0x00000002

◆ SYSCTL_SCGCWTIMER_S2

#define SYSCTL_SCGCWTIMER_S2   0x00000004

◆ SYSCTL_SCGCWTIMER_S3

#define SYSCTL_SCGCWTIMER_S3   0x00000008

◆ SYSCTL_SCGCWTIMER_S4

#define SYSCTL_SCGCWTIMER_S4   0x00000010

◆ SYSCTL_SCGCWTIMER_S5

#define SYSCTL_SCGCWTIMER_S5   0x00000020

◆ SYSCTL_SLPPWRCFG_FLASHPM_M

#define SYSCTL_SLPPWRCFG_FLASHPM_M    0x00000030

◆ SYSCTL_SLPPWRCFG_FLASHPM_NRM

#define SYSCTL_SLPPWRCFG_FLASHPM_NRM    0x00000000

◆ SYSCTL_SLPPWRCFG_FLASHPM_SLP

#define SYSCTL_SLPPWRCFG_FLASHPM_SLP    0x00000020

◆ SYSCTL_SLPPWRCFG_R

#define SYSCTL_SLPPWRCFG_R   (*((volatile u32 *)0x400FE188))

◆ SYSCTL_SLPPWRCFG_SRAMPM_LP

#define SYSCTL_SLPPWRCFG_SRAMPM_LP    0x00000003

◆ SYSCTL_SLPPWRCFG_SRAMPM_M

#define SYSCTL_SLPPWRCFG_SRAMPM_M    0x00000003

◆ SYSCTL_SLPPWRCFG_SRAMPM_NRM

#define SYSCTL_SLPPWRCFG_SRAMPM_NRM    0x00000000

◆ SYSCTL_SLPPWRCFG_SRAMPM_SBY

#define SYSCTL_SLPPWRCFG_SRAMPM_SBY    0x00000001

◆ SYSCTL_SRACMP_R

#define SYSCTL_SRACMP_R   (*((volatile u32 *)0x400FE53C))

◆ SYSCTL_SRACMP_R0

#define SYSCTL_SRACMP_R0   0x00000001

◆ SYSCTL_SRADC_R

#define SYSCTL_SRADC_R   (*((volatile u32 *)0x400FE538))

◆ SYSCTL_SRADC_R0

#define SYSCTL_SRADC_R0   0x00000001

◆ SYSCTL_SRADC_R1

#define SYSCTL_SRADC_R1   0x00000002

◆ SYSCTL_SRCAN_R

#define SYSCTL_SRCAN_R   (*((volatile u32 *)0x400FE534))

◆ SYSCTL_SRCAN_R0

#define SYSCTL_SRCAN_R0   0x00000001

◆ SYSCTL_SRCAN_R1

#define SYSCTL_SRCAN_R1   0x00000002

◆ SYSCTL_SRCR0_ADC0

#define SYSCTL_SRCR0_ADC0   0x00010000

◆ SYSCTL_SRCR0_ADC1

#define SYSCTL_SRCR0_ADC1   0x00020000

◆ SYSCTL_SRCR0_CAN0

#define SYSCTL_SRCR0_CAN0   0x01000000

◆ SYSCTL_SRCR0_CAN1

#define SYSCTL_SRCR0_CAN1   0x02000000

◆ SYSCTL_SRCR0_HIB

#define SYSCTL_SRCR0_HIB   0x00000040

◆ SYSCTL_SRCR0_PWM0

#define SYSCTL_SRCR0_PWM0   0x00100000

◆ SYSCTL_SRCR0_R

#define SYSCTL_SRCR0_R   (*((volatile u32 *)0x400FE040))

◆ SYSCTL_SRCR0_WDT0

#define SYSCTL_SRCR0_WDT0   0x00000008

◆ SYSCTL_SRCR0_WDT1

#define SYSCTL_SRCR0_WDT1   0x10000000

◆ SYSCTL_SRCR1_COMP0

#define SYSCTL_SRCR1_COMP0   0x01000000

◆ SYSCTL_SRCR1_COMP1

#define SYSCTL_SRCR1_COMP1   0x02000000

◆ SYSCTL_SRCR1_I2C0

#define SYSCTL_SRCR1_I2C0   0x00001000

◆ SYSCTL_SRCR1_I2C1

#define SYSCTL_SRCR1_I2C1   0x00004000

◆ SYSCTL_SRCR1_QEI0

#define SYSCTL_SRCR1_QEI0   0x00000100

◆ SYSCTL_SRCR1_QEI1

#define SYSCTL_SRCR1_QEI1   0x00000200

◆ SYSCTL_SRCR1_R

#define SYSCTL_SRCR1_R   (*((volatile u32 *)0x400FE044))

◆ SYSCTL_SRCR1_SSI0

#define SYSCTL_SRCR1_SSI0   0x00000010

◆ SYSCTL_SRCR1_SSI1

#define SYSCTL_SRCR1_SSI1   0x00000020

◆ SYSCTL_SRCR1_TIMER0

#define SYSCTL_SRCR1_TIMER0   0x00010000

◆ SYSCTL_SRCR1_TIMER1

#define SYSCTL_SRCR1_TIMER1   0x00020000

◆ SYSCTL_SRCR1_TIMER2

#define SYSCTL_SRCR1_TIMER2   0x00040000

◆ SYSCTL_SRCR1_TIMER3

#define SYSCTL_SRCR1_TIMER3   0x00080000

◆ SYSCTL_SRCR1_UART0

#define SYSCTL_SRCR1_UART0   0x00000001

◆ SYSCTL_SRCR1_UART1

#define SYSCTL_SRCR1_UART1   0x00000002

◆ SYSCTL_SRCR1_UART2

#define SYSCTL_SRCR1_UART2   0x00000004

◆ SYSCTL_SRCR2_GPIOA

#define SYSCTL_SRCR2_GPIOA   0x00000001

◆ SYSCTL_SRCR2_GPIOB

#define SYSCTL_SRCR2_GPIOB   0x00000002

◆ SYSCTL_SRCR2_GPIOC

#define SYSCTL_SRCR2_GPIOC   0x00000004

◆ SYSCTL_SRCR2_GPIOD

#define SYSCTL_SRCR2_GPIOD   0x00000008

◆ SYSCTL_SRCR2_GPIOE

#define SYSCTL_SRCR2_GPIOE   0x00000010

◆ SYSCTL_SRCR2_GPIOF

#define SYSCTL_SRCR2_GPIOF   0x00000020

◆ SYSCTL_SRCR2_R

#define SYSCTL_SRCR2_R   (*((volatile u32 *)0x400FE048))

◆ SYSCTL_SRCR2_UDMA

#define SYSCTL_SRCR2_UDMA   0x00002000

◆ SYSCTL_SRCR2_USB0

#define SYSCTL_SRCR2_USB0   0x00010000

◆ SYSCTL_SRDMA_R

#define SYSCTL_SRDMA_R   (*((volatile u32 *)0x400FE50C))

◆ SYSCTL_SRDMA_R0

#define SYSCTL_SRDMA_R0   0x00000001

◆ SYSCTL_SREEPROM_R

#define SYSCTL_SREEPROM_R   (*((volatile u32 *)0x400FE558))

◆ SYSCTL_SREEPROM_R0

#define SYSCTL_SREEPROM_R0   0x00000001

◆ SYSCTL_SRGPIO_R

#define SYSCTL_SRGPIO_R   (*((volatile u32 *)0x400FE508))

◆ SYSCTL_SRGPIO_R0

#define SYSCTL_SRGPIO_R0   0x00000001

◆ SYSCTL_SRGPIO_R1

#define SYSCTL_SRGPIO_R1   0x00000002

◆ SYSCTL_SRGPIO_R2

#define SYSCTL_SRGPIO_R2   0x00000004

◆ SYSCTL_SRGPIO_R3

#define SYSCTL_SRGPIO_R3   0x00000008

◆ SYSCTL_SRGPIO_R4

#define SYSCTL_SRGPIO_R4   0x00000010

◆ SYSCTL_SRGPIO_R5

#define SYSCTL_SRGPIO_R5   0x00000020

◆ SYSCTL_SRHIB_R

#define SYSCTL_SRHIB_R   (*((volatile u32 *)0x400FE514))

◆ SYSCTL_SRHIB_R0

#define SYSCTL_SRHIB_R0   0x00000001

◆ SYSCTL_SRI2C_R

#define SYSCTL_SRI2C_R   (*((volatile u32 *)0x400FE520))

◆ SYSCTL_SRI2C_R0

#define SYSCTL_SRI2C_R0   0x00000001

◆ SYSCTL_SRI2C_R1

#define SYSCTL_SRI2C_R1   0x00000002

◆ SYSCTL_SRI2C_R2

#define SYSCTL_SRI2C_R2   0x00000004

◆ SYSCTL_SRI2C_R3

#define SYSCTL_SRI2C_R3   0x00000008

◆ SYSCTL_SRPWM_R

#define SYSCTL_SRPWM_R   (*((volatile u32 *)0x400FE540))

◆ SYSCTL_SRPWM_R0

#define SYSCTL_SRPWM_R0   0x00000001

◆ SYSCTL_SRPWM_R1

#define SYSCTL_SRPWM_R1   0x00000002

◆ SYSCTL_SRQEI_R

#define SYSCTL_SRQEI_R   (*((volatile u32 *)0x400FE544))

◆ SYSCTL_SRQEI_R0

#define SYSCTL_SRQEI_R0   0x00000001

◆ SYSCTL_SRQEI_R1

#define SYSCTL_SRQEI_R1   0x00000002

◆ SYSCTL_SRSSI_R

#define SYSCTL_SRSSI_R   (*((volatile u32 *)0x400FE51C))

◆ SYSCTL_SRSSI_R0

#define SYSCTL_SRSSI_R0   0x00000001

◆ SYSCTL_SRSSI_R1

#define SYSCTL_SRSSI_R1   0x00000002

◆ SYSCTL_SRSSI_R2

#define SYSCTL_SRSSI_R2   0x00000004

◆ SYSCTL_SRSSI_R3

#define SYSCTL_SRSSI_R3   0x00000008

◆ SYSCTL_SRTIMER_R

#define SYSCTL_SRTIMER_R   (*((volatile u32 *)0x400FE504))

◆ SYSCTL_SRTIMER_R0

#define SYSCTL_SRTIMER_R0   0x00000001

◆ SYSCTL_SRTIMER_R1

#define SYSCTL_SRTIMER_R1   0x00000002

◆ SYSCTL_SRTIMER_R2

#define SYSCTL_SRTIMER_R2   0x00000004

◆ SYSCTL_SRTIMER_R3

#define SYSCTL_SRTIMER_R3   0x00000008

◆ SYSCTL_SRTIMER_R4

#define SYSCTL_SRTIMER_R4   0x00000010

◆ SYSCTL_SRTIMER_R5

#define SYSCTL_SRTIMER_R5   0x00000020

◆ SYSCTL_SRUART_R

#define SYSCTL_SRUART_R   (*((volatile u32 *)0x400FE518))

◆ SYSCTL_SRUART_R0

#define SYSCTL_SRUART_R0   0x00000001

◆ SYSCTL_SRUART_R1

#define SYSCTL_SRUART_R1   0x00000002

◆ SYSCTL_SRUART_R2

#define SYSCTL_SRUART_R2   0x00000004

◆ SYSCTL_SRUART_R3

#define SYSCTL_SRUART_R3   0x00000008

◆ SYSCTL_SRUART_R4

#define SYSCTL_SRUART_R4   0x00000010

◆ SYSCTL_SRUART_R5

#define SYSCTL_SRUART_R5   0x00000020

◆ SYSCTL_SRUART_R6

#define SYSCTL_SRUART_R6   0x00000040

◆ SYSCTL_SRUART_R7

#define SYSCTL_SRUART_R7   0x00000080

◆ SYSCTL_SRUSB_R

#define SYSCTL_SRUSB_R   (*((volatile u32 *)0x400FE528))

◆ SYSCTL_SRUSB_R0

#define SYSCTL_SRUSB_R0   0x00000001

◆ SYSCTL_SRWD_R

#define SYSCTL_SRWD_R   (*((volatile u32 *)0x400FE500))

◆ SYSCTL_SRWD_R0

#define SYSCTL_SRWD_R0   0x00000001

◆ SYSCTL_SRWD_R1

#define SYSCTL_SRWD_R1   0x00000002

◆ SYSCTL_SRWTIMER_R

#define SYSCTL_SRWTIMER_R   (*((volatile u32 *)0x400FE55C))

◆ SYSCTL_SRWTIMER_R0

#define SYSCTL_SRWTIMER_R0   0x00000001

◆ SYSCTL_SRWTIMER_R1

#define SYSCTL_SRWTIMER_R1   0x00000002

◆ SYSCTL_SRWTIMER_R2

#define SYSCTL_SRWTIMER_R2   0x00000004

◆ SYSCTL_SRWTIMER_R3

#define SYSCTL_SRWTIMER_R3   0x00000008

◆ SYSCTL_SRWTIMER_R4

#define SYSCTL_SRWTIMER_R4   0x00000010

◆ SYSCTL_SRWTIMER_R5

#define SYSCTL_SRWTIMER_R5   0x00000020

◆ SYSCTL_SYSPROP_FPU

#define SYSCTL_SYSPROP_FPU   0x00000001

◆ SYSCTL_SYSPROP_R

#define SYSCTL_SYSPROP_R   (*((volatile u32 *)0x400FE14C))

◆ SYSEXC_IC_FPDZCIC

#define SYSEXC_IC_FPDZCIC   0x00000002

◆ SYSEXC_IC_FPIDCIC

#define SYSEXC_IC_FPIDCIC   0x00000001

◆ SYSEXC_IC_FPIOCIC

#define SYSEXC_IC_FPIOCIC   0x00000004

◆ SYSEXC_IC_FPIXCIC

#define SYSEXC_IC_FPIXCIC   0x00000020

◆ SYSEXC_IC_FPOFCIC

#define SYSEXC_IC_FPOFCIC   0x00000010

◆ SYSEXC_IC_FPUFCIC

#define SYSEXC_IC_FPUFCIC   0x00000008

◆ SYSEXC_IC_R

#define SYSEXC_IC_R   (*((volatile u32 *)0x400F900C))

◆ SYSEXC_IM_FPDZCIM

#define SYSEXC_IM_FPDZCIM   0x00000002

◆ SYSEXC_IM_FPIDCIM

#define SYSEXC_IM_FPIDCIM   0x00000001

◆ SYSEXC_IM_FPIOCIM

#define SYSEXC_IM_FPIOCIM   0x00000004

◆ SYSEXC_IM_FPIXCIM

#define SYSEXC_IM_FPIXCIM   0x00000020

◆ SYSEXC_IM_FPOFCIM

#define SYSEXC_IM_FPOFCIM   0x00000010

◆ SYSEXC_IM_FPUFCIM

#define SYSEXC_IM_FPUFCIM   0x00000008

◆ SYSEXC_IM_R

#define SYSEXC_IM_R   (*((volatile u32 *)0x400F9004))

◆ SYSEXC_MIS_FPDZCMIS

#define SYSEXC_MIS_FPDZCMIS   0x00000002

◆ SYSEXC_MIS_FPIDCMIS

#define SYSEXC_MIS_FPIDCMIS   0x00000001

◆ SYSEXC_MIS_FPIOCMIS

#define SYSEXC_MIS_FPIOCMIS   0x00000004

◆ SYSEXC_MIS_FPIXCMIS

#define SYSEXC_MIS_FPIXCMIS   0x00000020

◆ SYSEXC_MIS_FPOFCMIS

#define SYSEXC_MIS_FPOFCMIS   0x00000010

◆ SYSEXC_MIS_FPUFCMIS

#define SYSEXC_MIS_FPUFCMIS   0x00000008

◆ SYSEXC_MIS_R

#define SYSEXC_MIS_R   (*((volatile u32 *)0x400F9008))

◆ SYSEXC_RIS_FPDZCRIS

#define SYSEXC_RIS_FPDZCRIS   0x00000002

◆ SYSEXC_RIS_FPIDCRIS

#define SYSEXC_RIS_FPIDCRIS   0x00000001

◆ SYSEXC_RIS_FPIOCRIS

#define SYSEXC_RIS_FPIOCRIS   0x00000004

◆ SYSEXC_RIS_FPIXCRIS

#define SYSEXC_RIS_FPIXCRIS   0x00000020

◆ SYSEXC_RIS_FPOFCRIS

#define SYSEXC_RIS_FPOFCRIS   0x00000010

◆ SYSEXC_RIS_FPUFCRIS

#define SYSEXC_RIS_FPUFCRIS   0x00000008

◆ SYSEXC_RIS_R

#define SYSEXC_RIS_R   (*((volatile u32 *)0x400F9000))

◆ TIMER0_CFG_R

#define TIMER0_CFG_R   (*((volatile u32 *)0x40030000))

◆ TIMER0_CTL_R

#define TIMER0_CTL_R   (*((volatile u32 *)0x4003000C))

◆ TIMER0_ICR_R

#define TIMER0_ICR_R   (*((volatile u32 *)0x40030024))

◆ TIMER0_IMR_R

#define TIMER0_IMR_R   (*((volatile u32 *)0x40030018))

◆ TIMER0_MIS_R

#define TIMER0_MIS_R   (*((volatile u32 *)0x40030020))

◆ TIMER0_PP_R

#define TIMER0_PP_R   (*((volatile u32 *)0x40030FC0))

◆ TIMER0_RIS_R

#define TIMER0_RIS_R   (*((volatile u32 *)0x4003001C))

◆ TIMER0_RTCPD_R

#define TIMER0_RTCPD_R   (*((volatile u32 *)0x40030058))

◆ TIMER0_SYNC_R

#define TIMER0_SYNC_R   (*((volatile u32 *)0x40030010))

◆ TIMER0_TAILR_R

#define TIMER0_TAILR_R   (*((volatile u32 *)0x40030028))

◆ TIMER0_TAMATCHR_R

#define TIMER0_TAMATCHR_R   (*((volatile u32 *)0x40030030))

◆ TIMER0_TAMR_R

#define TIMER0_TAMR_R   (*((volatile u32 *)0x40030004))

◆ TIMER0_TAPMR_R

#define TIMER0_TAPMR_R   (*((volatile u32 *)0x40030040))

◆ TIMER0_TAPR_R

#define TIMER0_TAPR_R   (*((volatile u32 *)0x40030038))

◆ TIMER0_TAPS_R

#define TIMER0_TAPS_R   (*((volatile u32 *)0x4003005C))

◆ TIMER0_TAPV_R

#define TIMER0_TAPV_R   (*((volatile u32 *)0x40030064))

◆ TIMER0_TAR_R

#define TIMER0_TAR_R   (*((volatile u32 *)0x40030048))

◆ TIMER0_TAV_R

#define TIMER0_TAV_R   (*((volatile u32 *)0x40030050))

◆ TIMER0_TBILR_R

#define TIMER0_TBILR_R   (*((volatile u32 *)0x4003002C))

◆ TIMER0_TBMATCHR_R

#define TIMER0_TBMATCHR_R   (*((volatile u32 *)0x40030034))

◆ TIMER0_TBMR_R

#define TIMER0_TBMR_R   (*((volatile u32 *)0x40030008))

◆ TIMER0_TBPMR_R

#define TIMER0_TBPMR_R   (*((volatile u32 *)0x40030044))

◆ TIMER0_TBPR_R

#define TIMER0_TBPR_R   (*((volatile u32 *)0x4003003C))

◆ TIMER0_TBPS_R

#define TIMER0_TBPS_R   (*((volatile u32 *)0x40030060))

◆ TIMER0_TBPV_R

#define TIMER0_TBPV_R   (*((volatile u32 *)0x40030068))

◆ TIMER0_TBR_R

#define TIMER0_TBR_R   (*((volatile u32 *)0x4003004C))

◆ TIMER0_TBV_R

#define TIMER0_TBV_R   (*((volatile u32 *)0x40030054))

◆ TIMER1_CFG_R

#define TIMER1_CFG_R   (*((volatile u32 *)0x40031000))

◆ TIMER1_CTL_R

#define TIMER1_CTL_R   (*((volatile u32 *)0x4003100C))

◆ TIMER1_ICR_R

#define TIMER1_ICR_R   (*((volatile u32 *)0x40031024))

◆ TIMER1_IMR_R

#define TIMER1_IMR_R   (*((volatile u32 *)0x40031018))

◆ TIMER1_MIS_R

#define TIMER1_MIS_R   (*((volatile u32 *)0x40031020))

◆ TIMER1_PP_R

#define TIMER1_PP_R   (*((volatile u32 *)0x40031FC0))

◆ TIMER1_RIS_R

#define TIMER1_RIS_R   (*((volatile u32 *)0x4003101C))

◆ TIMER1_RTCPD_R

#define TIMER1_RTCPD_R   (*((volatile u32 *)0x40031058))

◆ TIMER1_SYNC_R

#define TIMER1_SYNC_R   (*((volatile u32 *)0x40031010))

◆ TIMER1_TAILR_R

#define TIMER1_TAILR_R   (*((volatile u32 *)0x40031028))

◆ TIMER1_TAMATCHR_R

#define TIMER1_TAMATCHR_R   (*((volatile u32 *)0x40031030))

◆ TIMER1_TAMR_R

#define TIMER1_TAMR_R   (*((volatile u32 *)0x40031004))

◆ TIMER1_TAPMR_R

#define TIMER1_TAPMR_R   (*((volatile u32 *)0x40031040))

◆ TIMER1_TAPR_R

#define TIMER1_TAPR_R   (*((volatile u32 *)0x40031038))

◆ TIMER1_TAPS_R

#define TIMER1_TAPS_R   (*((volatile u32 *)0x4003105C))

◆ TIMER1_TAPV_R

#define TIMER1_TAPV_R   (*((volatile u32 *)0x40031064))

◆ TIMER1_TAR_R

#define TIMER1_TAR_R   (*((volatile u32 *)0x40031048))

◆ TIMER1_TAV_R

#define TIMER1_TAV_R   (*((volatile u32 *)0x40031050))

◆ TIMER1_TBILR_R

#define TIMER1_TBILR_R   (*((volatile u32 *)0x4003102C))

◆ TIMER1_TBMATCHR_R

#define TIMER1_TBMATCHR_R   (*((volatile u32 *)0x40031034))

◆ TIMER1_TBMR_R

#define TIMER1_TBMR_R   (*((volatile u32 *)0x40031008))

◆ TIMER1_TBPMR_R

#define TIMER1_TBPMR_R   (*((volatile u32 *)0x40031044))

◆ TIMER1_TBPR_R

#define TIMER1_TBPR_R   (*((volatile u32 *)0x4003103C))

◆ TIMER1_TBPS_R

#define TIMER1_TBPS_R   (*((volatile u32 *)0x40031060))

◆ TIMER1_TBPV_R

#define TIMER1_TBPV_R   (*((volatile u32 *)0x40031068))

◆ TIMER1_TBR_R

#define TIMER1_TBR_R   (*((volatile u32 *)0x4003104C))

◆ TIMER1_TBV_R

#define TIMER1_TBV_R   (*((volatile u32 *)0x40031054))

◆ TIMER2_CFG_R

#define TIMER2_CFG_R   (*((volatile u32 *)0x40032000))

◆ TIMER2_CTL_R

#define TIMER2_CTL_R   (*((volatile u32 *)0x4003200C))

◆ TIMER2_ICR_R

#define TIMER2_ICR_R   (*((volatile u32 *)0x40032024))

◆ TIMER2_IMR_R

#define TIMER2_IMR_R   (*((volatile u32 *)0x40032018))

◆ TIMER2_MIS_R

#define TIMER2_MIS_R   (*((volatile u32 *)0x40032020))

◆ TIMER2_PP_R

#define TIMER2_PP_R   (*((volatile u32 *)0x40032FC0))

◆ TIMER2_RIS_R

#define TIMER2_RIS_R   (*((volatile u32 *)0x4003201C))

◆ TIMER2_RTCPD_R

#define TIMER2_RTCPD_R   (*((volatile u32 *)0x40032058))

◆ TIMER2_SYNC_R

#define TIMER2_SYNC_R   (*((volatile u32 *)0x40032010))

◆ TIMER2_TAILR_R

#define TIMER2_TAILR_R   (*((volatile u32 *)0x40032028))

◆ TIMER2_TAMATCHR_R

#define TIMER2_TAMATCHR_R   (*((volatile u32 *)0x40032030))

◆ TIMER2_TAMR_R

#define TIMER2_TAMR_R   (*((volatile u32 *)0x40032004))

◆ TIMER2_TAPMR_R

#define TIMER2_TAPMR_R   (*((volatile u32 *)0x40032040))

◆ TIMER2_TAPR_R

#define TIMER2_TAPR_R   (*((volatile u32 *)0x40032038))

◆ TIMER2_TAPS_R

#define TIMER2_TAPS_R   (*((volatile u32 *)0x4003205C))

◆ TIMER2_TAPV_R

#define TIMER2_TAPV_R   (*((volatile u32 *)0x40032064))

◆ TIMER2_TAR_R

#define TIMER2_TAR_R   (*((volatile u32 *)0x40032048))

◆ TIMER2_TAV_R

#define TIMER2_TAV_R   (*((volatile u32 *)0x40032050))

◆ TIMER2_TBILR_R

#define TIMER2_TBILR_R   (*((volatile u32 *)0x4003202C))

◆ TIMER2_TBMATCHR_R

#define TIMER2_TBMATCHR_R   (*((volatile u32 *)0x40032034))

◆ TIMER2_TBMR_R

#define TIMER2_TBMR_R   (*((volatile u32 *)0x40032008))

◆ TIMER2_TBPMR_R

#define TIMER2_TBPMR_R   (*((volatile u32 *)0x40032044))

◆ TIMER2_TBPR_R

#define TIMER2_TBPR_R   (*((volatile u32 *)0x4003203C))

◆ TIMER2_TBPS_R

#define TIMER2_TBPS_R   (*((volatile u32 *)0x40032060))

◆ TIMER2_TBPV_R

#define TIMER2_TBPV_R   (*((volatile u32 *)0x40032068))

◆ TIMER2_TBR_R

#define TIMER2_TBR_R   (*((volatile u32 *)0x4003204C))

◆ TIMER2_TBV_R

#define TIMER2_TBV_R   (*((volatile u32 *)0x40032054))

◆ TIMER3_CFG_R

#define TIMER3_CFG_R   (*((volatile u32 *)0x40033000))

◆ TIMER3_CTL_R

#define TIMER3_CTL_R   (*((volatile u32 *)0x4003300C))

◆ TIMER3_ICR_R

#define TIMER3_ICR_R   (*((volatile u32 *)0x40033024))

◆ TIMER3_IMR_R

#define TIMER3_IMR_R   (*((volatile u32 *)0x40033018))

◆ TIMER3_MIS_R

#define TIMER3_MIS_R   (*((volatile u32 *)0x40033020))

◆ TIMER3_PP_R

#define TIMER3_PP_R   (*((volatile u32 *)0x40033FC0))

◆ TIMER3_RIS_R

#define TIMER3_RIS_R   (*((volatile u32 *)0x4003301C))

◆ TIMER3_RTCPD_R

#define TIMER3_RTCPD_R   (*((volatile u32 *)0x40033058))

◆ TIMER3_SYNC_R

#define TIMER3_SYNC_R   (*((volatile u32 *)0x40033010))

◆ TIMER3_TAILR_R

#define TIMER3_TAILR_R   (*((volatile u32 *)0x40033028))

◆ TIMER3_TAMATCHR_R

#define TIMER3_TAMATCHR_R   (*((volatile u32 *)0x40033030))

◆ TIMER3_TAMR_R

#define TIMER3_TAMR_R   (*((volatile u32 *)0x40033004))

◆ TIMER3_TAPMR_R

#define TIMER3_TAPMR_R   (*((volatile u32 *)0x40033040))

◆ TIMER3_TAPR_R

#define TIMER3_TAPR_R   (*((volatile u32 *)0x40033038))

◆ TIMER3_TAPS_R

#define TIMER3_TAPS_R   (*((volatile u32 *)0x4003305C))

◆ TIMER3_TAPV_R

#define TIMER3_TAPV_R   (*((volatile u32 *)0x40033064))

◆ TIMER3_TAR_R

#define TIMER3_TAR_R   (*((volatile u32 *)0x40033048))

◆ TIMER3_TAV_R

#define TIMER3_TAV_R   (*((volatile u32 *)0x40033050))

◆ TIMER3_TBILR_R

#define TIMER3_TBILR_R   (*((volatile u32 *)0x4003302C))

◆ TIMER3_TBMATCHR_R

#define TIMER3_TBMATCHR_R   (*((volatile u32 *)0x40033034))

◆ TIMER3_TBMR_R

#define TIMER3_TBMR_R   (*((volatile u32 *)0x40033008))

◆ TIMER3_TBPMR_R

#define TIMER3_TBPMR_R   (*((volatile u32 *)0x40033044))

◆ TIMER3_TBPR_R

#define TIMER3_TBPR_R   (*((volatile u32 *)0x4003303C))

◆ TIMER3_TBPS_R

#define TIMER3_TBPS_R   (*((volatile u32 *)0x40033060))

◆ TIMER3_TBPV_R

#define TIMER3_TBPV_R   (*((volatile u32 *)0x40033068))

◆ TIMER3_TBR_R

#define TIMER3_TBR_R   (*((volatile u32 *)0x4003304C))

◆ TIMER3_TBV_R

#define TIMER3_TBV_R   (*((volatile u32 *)0x40033054))

◆ TIMER4_CFG_R

#define TIMER4_CFG_R   (*((volatile u32 *)0x40034000))

◆ TIMER4_CTL_R

#define TIMER4_CTL_R   (*((volatile u32 *)0x4003400C))

◆ TIMER4_ICR_R

#define TIMER4_ICR_R   (*((volatile u32 *)0x40034024))

◆ TIMER4_IMR_R

#define TIMER4_IMR_R   (*((volatile u32 *)0x40034018))

◆ TIMER4_MIS_R

#define TIMER4_MIS_R   (*((volatile u32 *)0x40034020))

◆ TIMER4_PP_R

#define TIMER4_PP_R   (*((volatile u32 *)0x40034FC0))

◆ TIMER4_RIS_R

#define TIMER4_RIS_R   (*((volatile u32 *)0x4003401C))

◆ TIMER4_RTCPD_R

#define TIMER4_RTCPD_R   (*((volatile u32 *)0x40034058))

◆ TIMER4_SYNC_R

#define TIMER4_SYNC_R   (*((volatile u32 *)0x40034010))

◆ TIMER4_TAILR_R

#define TIMER4_TAILR_R   (*((volatile u32 *)0x40034028))

◆ TIMER4_TAMATCHR_R

#define TIMER4_TAMATCHR_R   (*((volatile u32 *)0x40034030))

◆ TIMER4_TAMR_R

#define TIMER4_TAMR_R   (*((volatile u32 *)0x40034004))

◆ TIMER4_TAPMR_R

#define TIMER4_TAPMR_R   (*((volatile u32 *)0x40034040))

◆ TIMER4_TAPR_R

#define TIMER4_TAPR_R   (*((volatile u32 *)0x40034038))

◆ TIMER4_TAPS_R

#define TIMER4_TAPS_R   (*((volatile u32 *)0x4003405C))

◆ TIMER4_TAPV_R

#define TIMER4_TAPV_R   (*((volatile u32 *)0x40034064))

◆ TIMER4_TAR_R

#define TIMER4_TAR_R   (*((volatile u32 *)0x40034048))

◆ TIMER4_TAV_R

#define TIMER4_TAV_R   (*((volatile u32 *)0x40034050))

◆ TIMER4_TBILR_R

#define TIMER4_TBILR_R   (*((volatile u32 *)0x4003402C))

◆ TIMER4_TBMATCHR_R

#define TIMER4_TBMATCHR_R   (*((volatile u32 *)0x40034034))

◆ TIMER4_TBMR_R

#define TIMER4_TBMR_R   (*((volatile u32 *)0x40034008))

◆ TIMER4_TBPMR_R

#define TIMER4_TBPMR_R   (*((volatile u32 *)0x40034044))

◆ TIMER4_TBPR_R

#define TIMER4_TBPR_R   (*((volatile u32 *)0x4003403C))

◆ TIMER4_TBPS_R

#define TIMER4_TBPS_R   (*((volatile u32 *)0x40034060))

◆ TIMER4_TBPV_R

#define TIMER4_TBPV_R   (*((volatile u32 *)0x40034068))

◆ TIMER4_TBR_R

#define TIMER4_TBR_R   (*((volatile u32 *)0x4003404C))

◆ TIMER4_TBV_R

#define TIMER4_TBV_R   (*((volatile u32 *)0x40034054))

◆ TIMER5_CFG_R

#define TIMER5_CFG_R   (*((volatile u32 *)0x40035000))

◆ TIMER5_CTL_R

#define TIMER5_CTL_R   (*((volatile u32 *)0x4003500C))

◆ TIMER5_ICR_R

#define TIMER5_ICR_R   (*((volatile u32 *)0x40035024))

◆ TIMER5_IMR_R

#define TIMER5_IMR_R   (*((volatile u32 *)0x40035018))

◆ TIMER5_MIS_R

#define TIMER5_MIS_R   (*((volatile u32 *)0x40035020))

◆ TIMER5_PP_R

#define TIMER5_PP_R   (*((volatile u32 *)0x40035FC0))

◆ TIMER5_RIS_R

#define TIMER5_RIS_R   (*((volatile u32 *)0x4003501C))

◆ TIMER5_RTCPD_R

#define TIMER5_RTCPD_R   (*((volatile u32 *)0x40035058))

◆ TIMER5_SYNC_R

#define TIMER5_SYNC_R   (*((volatile u32 *)0x40035010))

◆ TIMER5_TAILR_R

#define TIMER5_TAILR_R   (*((volatile u32 *)0x40035028))

◆ TIMER5_TAMATCHR_R

#define TIMER5_TAMATCHR_R   (*((volatile u32 *)0x40035030))

◆ TIMER5_TAMR_R

#define TIMER5_TAMR_R   (*((volatile u32 *)0x40035004))

◆ TIMER5_TAPMR_R

#define TIMER5_TAPMR_R   (*((volatile u32 *)0x40035040))

◆ TIMER5_TAPR_R

#define TIMER5_TAPR_R   (*((volatile u32 *)0x40035038))

◆ TIMER5_TAPS_R

#define TIMER5_TAPS_R   (*((volatile u32 *)0x4003505C))

◆ TIMER5_TAPV_R

#define TIMER5_TAPV_R   (*((volatile u32 *)0x40035064))

◆ TIMER5_TAR_R

#define TIMER5_TAR_R   (*((volatile u32 *)0x40035048))

◆ TIMER5_TAV_R

#define TIMER5_TAV_R   (*((volatile u32 *)0x40035050))

◆ TIMER5_TBILR_R

#define TIMER5_TBILR_R   (*((volatile u32 *)0x4003502C))

◆ TIMER5_TBMATCHR_R

#define TIMER5_TBMATCHR_R   (*((volatile u32 *)0x40035034))

◆ TIMER5_TBMR_R

#define TIMER5_TBMR_R   (*((volatile u32 *)0x40035008))

◆ TIMER5_TBPMR_R

#define TIMER5_TBPMR_R   (*((volatile u32 *)0x40035044))

◆ TIMER5_TBPR_R

#define TIMER5_TBPR_R   (*((volatile u32 *)0x4003503C))

◆ TIMER5_TBPS_R

#define TIMER5_TBPS_R   (*((volatile u32 *)0x40035060))

◆ TIMER5_TBPV_R

#define TIMER5_TBPV_R   (*((volatile u32 *)0x40035068))

◆ TIMER5_TBR_R

#define TIMER5_TBR_R   (*((volatile u32 *)0x4003504C))

◆ TIMER5_TBV_R

#define TIMER5_TBV_R   (*((volatile u32 *)0x40035054))

◆ TIMER_CFG_16_BIT

#define TIMER_CFG_16_BIT   0x00000004

◆ TIMER_CFG_32_BIT_RTC

#define TIMER_CFG_32_BIT_RTC   0x00000001

◆ TIMER_CFG_32_BIT_TIMER

#define TIMER_CFG_32_BIT_TIMER   0x00000000

◆ TIMER_CFG_M

#define TIMER_CFG_M   0x00000007

◆ TIMER_CTL_RTCEN

#define TIMER_CTL_RTCEN   0x00000010

◆ TIMER_CTL_TAEN

#define TIMER_CTL_TAEN   0x00000001

◆ TIMER_CTL_TAEVENT_BOTH

#define TIMER_CTL_TAEVENT_BOTH   0x0000000C

◆ TIMER_CTL_TAEVENT_M

#define TIMER_CTL_TAEVENT_M   0x0000000C

◆ TIMER_CTL_TAEVENT_NEG

#define TIMER_CTL_TAEVENT_NEG   0x00000004

◆ TIMER_CTL_TAEVENT_POS

#define TIMER_CTL_TAEVENT_POS   0x00000000

◆ TIMER_CTL_TAOTE

#define TIMER_CTL_TAOTE   0x00000020

◆ TIMER_CTL_TAPWML

#define TIMER_CTL_TAPWML   0x00000040

◆ TIMER_CTL_TASTALL

#define TIMER_CTL_TASTALL   0x00000002

◆ TIMER_CTL_TBEN

#define TIMER_CTL_TBEN   0x00000100

◆ TIMER_CTL_TBEVENT_BOTH

#define TIMER_CTL_TBEVENT_BOTH   0x00000C00

◆ TIMER_CTL_TBEVENT_M

#define TIMER_CTL_TBEVENT_M   0x00000C00

◆ TIMER_CTL_TBEVENT_NEG

#define TIMER_CTL_TBEVENT_NEG   0x00000400

◆ TIMER_CTL_TBEVENT_POS

#define TIMER_CTL_TBEVENT_POS   0x00000000

◆ TIMER_CTL_TBOTE

#define TIMER_CTL_TBOTE   0x00002000

◆ TIMER_CTL_TBPWML

#define TIMER_CTL_TBPWML   0x00004000

◆ TIMER_CTL_TBSTALL

#define TIMER_CTL_TBSTALL   0x00000200

◆ TIMER_ICR_CAECINT

#define TIMER_ICR_CAECINT   0x00000004

◆ TIMER_ICR_CAMCINT

#define TIMER_ICR_CAMCINT   0x00000002

◆ TIMER_ICR_CBECINT

#define TIMER_ICR_CBECINT   0x00000400

◆ TIMER_ICR_CBMCINT

#define TIMER_ICR_CBMCINT   0x00000200

◆ TIMER_ICR_RTCCINT

#define TIMER_ICR_RTCCINT   0x00000008

◆ TIMER_ICR_TAMCINT

#define TIMER_ICR_TAMCINT   0x00000010

◆ TIMER_ICR_TATOCINT

#define TIMER_ICR_TATOCINT   0x00000001

◆ TIMER_ICR_TBMCINT

#define TIMER_ICR_TBMCINT   0x00000800

◆ TIMER_ICR_TBTOCINT

#define TIMER_ICR_TBTOCINT   0x00000100

◆ TIMER_ICR_WUECINT

#define TIMER_ICR_WUECINT   0x00010000

◆ TIMER_IMR_CAEIM

#define TIMER_IMR_CAEIM   0x00000004

◆ TIMER_IMR_CAMIM

#define TIMER_IMR_CAMIM   0x00000002

◆ TIMER_IMR_CBEIM

#define TIMER_IMR_CBEIM   0x00000400

◆ TIMER_IMR_CBMIM

#define TIMER_IMR_CBMIM   0x00000200

◆ TIMER_IMR_RTCIM

#define TIMER_IMR_RTCIM   0x00000008

◆ TIMER_IMR_TAMIM

#define TIMER_IMR_TAMIM   0x00000010

◆ TIMER_IMR_TATOIM

#define TIMER_IMR_TATOIM   0x00000001

◆ TIMER_IMR_TBMIM

#define TIMER_IMR_TBMIM   0x00000800

◆ TIMER_IMR_TBTOIM

#define TIMER_IMR_TBTOIM   0x00000100

◆ TIMER_IMR_WUEIM

#define TIMER_IMR_WUEIM   0x00010000

◆ TIMER_MIS_CAEMIS

#define TIMER_MIS_CAEMIS   0x00000004

◆ TIMER_MIS_CAMMIS

#define TIMER_MIS_CAMMIS   0x00000002

◆ TIMER_MIS_CBEMIS

#define TIMER_MIS_CBEMIS   0x00000400

◆ TIMER_MIS_CBMMIS

#define TIMER_MIS_CBMMIS   0x00000200

◆ TIMER_MIS_RTCMIS

#define TIMER_MIS_RTCMIS   0x00000008

◆ TIMER_MIS_TAMMIS

#define TIMER_MIS_TAMMIS   0x00000010

◆ TIMER_MIS_TATOMIS

#define TIMER_MIS_TATOMIS   0x00000001

◆ TIMER_MIS_TBMMIS

#define TIMER_MIS_TBMMIS   0x00000800

◆ TIMER_MIS_TBTOMIS

#define TIMER_MIS_TBTOMIS   0x00000100

◆ TIMER_MIS_WUEMIS

#define TIMER_MIS_WUEMIS   0x00010000

◆ TIMER_PP_SIZE_16

#define TIMER_PP_SIZE_16   0x00000000

◆ TIMER_PP_SIZE_32

#define TIMER_PP_SIZE_32   0x00000001

◆ TIMER_PP_SIZE_M

#define TIMER_PP_SIZE_M   0x0000000F

◆ TIMER_RIS_CAERIS

#define TIMER_RIS_CAERIS   0x00000004

◆ TIMER_RIS_CAMRIS

#define TIMER_RIS_CAMRIS   0x00000002

◆ TIMER_RIS_CBERIS

#define TIMER_RIS_CBERIS   0x00000400

◆ TIMER_RIS_CBMRIS

#define TIMER_RIS_CBMRIS   0x00000200

◆ TIMER_RIS_RTCRIS

#define TIMER_RIS_RTCRIS   0x00000008

◆ TIMER_RIS_TAMRIS

#define TIMER_RIS_TAMRIS   0x00000010

◆ TIMER_RIS_TATORIS

#define TIMER_RIS_TATORIS   0x00000001

◆ TIMER_RIS_TBMRIS

#define TIMER_RIS_TBMRIS   0x00000800

◆ TIMER_RIS_TBTORIS

#define TIMER_RIS_TBTORIS   0x00000100

◆ TIMER_RIS_WUERIS

#define TIMER_RIS_WUERIS   0x00010000

◆ TIMER_RTCPD_RTCPD_M

#define TIMER_RTCPD_RTCPD_M   0x0000FFFF

◆ TIMER_RTCPD_RTCPD_S

#define TIMER_RTCPD_RTCPD_S   0

◆ TIMER_SYNC_SYNCT0_M

#define TIMER_SYNC_SYNCT0_M   0x00000003

◆ TIMER_SYNC_SYNCT0_NONE

#define TIMER_SYNC_SYNCT0_NONE   0x00000000

◆ TIMER_SYNC_SYNCT0_TA

#define TIMER_SYNC_SYNCT0_TA   0x00000001

◆ TIMER_SYNC_SYNCT0_TATB

#define TIMER_SYNC_SYNCT0_TATB   0x00000003

◆ TIMER_SYNC_SYNCT0_TB

#define TIMER_SYNC_SYNCT0_TB   0x00000002

◆ TIMER_SYNC_SYNCT1_M

#define TIMER_SYNC_SYNCT1_M   0x0000000C

◆ TIMER_SYNC_SYNCT1_NONE

#define TIMER_SYNC_SYNCT1_NONE   0x00000000

◆ TIMER_SYNC_SYNCT1_TA

#define TIMER_SYNC_SYNCT1_TA   0x00000004

◆ TIMER_SYNC_SYNCT1_TATB

#define TIMER_SYNC_SYNCT1_TATB   0x0000000C

◆ TIMER_SYNC_SYNCT1_TB

#define TIMER_SYNC_SYNCT1_TB   0x00000008

◆ TIMER_SYNC_SYNCT2_M

#define TIMER_SYNC_SYNCT2_M   0x00000030

◆ TIMER_SYNC_SYNCT2_NONE

#define TIMER_SYNC_SYNCT2_NONE   0x00000000

◆ TIMER_SYNC_SYNCT2_TA

#define TIMER_SYNC_SYNCT2_TA   0x00000010

◆ TIMER_SYNC_SYNCT2_TATB

#define TIMER_SYNC_SYNCT2_TATB   0x00000030

◆ TIMER_SYNC_SYNCT2_TB

#define TIMER_SYNC_SYNCT2_TB   0x00000020

◆ TIMER_SYNC_SYNCT3_M

#define TIMER_SYNC_SYNCT3_M   0x000000C0

◆ TIMER_SYNC_SYNCT3_NONE

#define TIMER_SYNC_SYNCT3_NONE   0x00000000

◆ TIMER_SYNC_SYNCT3_TA

#define TIMER_SYNC_SYNCT3_TA   0x00000040

◆ TIMER_SYNC_SYNCT3_TATB

#define TIMER_SYNC_SYNCT3_TATB   0x000000C0

◆ TIMER_SYNC_SYNCT3_TB

#define TIMER_SYNC_SYNCT3_TB   0x00000080

◆ TIMER_SYNC_SYNCT4_M

#define TIMER_SYNC_SYNCT4_M   0x00000300

◆ TIMER_SYNC_SYNCT4_NONE

#define TIMER_SYNC_SYNCT4_NONE   0x00000000

◆ TIMER_SYNC_SYNCT4_TA

#define TIMER_SYNC_SYNCT4_TA   0x00000100

◆ TIMER_SYNC_SYNCT4_TATB

#define TIMER_SYNC_SYNCT4_TATB   0x00000300

◆ TIMER_SYNC_SYNCT4_TB

#define TIMER_SYNC_SYNCT4_TB   0x00000200

◆ TIMER_SYNC_SYNCT5_M

#define TIMER_SYNC_SYNCT5_M   0x00000C00

◆ TIMER_SYNC_SYNCT5_NONE

#define TIMER_SYNC_SYNCT5_NONE   0x00000000

◆ TIMER_SYNC_SYNCT5_TA

#define TIMER_SYNC_SYNCT5_TA   0x00000400

◆ TIMER_SYNC_SYNCT5_TATB

#define TIMER_SYNC_SYNCT5_TATB   0x00000C00

◆ TIMER_SYNC_SYNCT5_TB

#define TIMER_SYNC_SYNCT5_TB   0x00000800

◆ TIMER_SYNC_SYNCWT0_M

#define TIMER_SYNC_SYNCWT0_M   0x00003000

◆ TIMER_SYNC_SYNCWT0_NONE

#define TIMER_SYNC_SYNCWT0_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT0_TA

#define TIMER_SYNC_SYNCWT0_TA   0x00001000

◆ TIMER_SYNC_SYNCWT0_TATB

#define TIMER_SYNC_SYNCWT0_TATB   0x00003000

◆ TIMER_SYNC_SYNCWT0_TB

#define TIMER_SYNC_SYNCWT0_TB   0x00002000

◆ TIMER_SYNC_SYNCWT1_M

#define TIMER_SYNC_SYNCWT1_M   0x0000C000

◆ TIMER_SYNC_SYNCWT1_NONE

#define TIMER_SYNC_SYNCWT1_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT1_TA

#define TIMER_SYNC_SYNCWT1_TA   0x00004000

◆ TIMER_SYNC_SYNCWT1_TATB

#define TIMER_SYNC_SYNCWT1_TATB   0x0000C000

◆ TIMER_SYNC_SYNCWT1_TB

#define TIMER_SYNC_SYNCWT1_TB   0x00008000

◆ TIMER_SYNC_SYNCWT2_M

#define TIMER_SYNC_SYNCWT2_M   0x00030000

◆ TIMER_SYNC_SYNCWT2_NONE

#define TIMER_SYNC_SYNCWT2_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT2_TA

#define TIMER_SYNC_SYNCWT2_TA   0x00010000

◆ TIMER_SYNC_SYNCWT2_TATB

#define TIMER_SYNC_SYNCWT2_TATB   0x00030000

◆ TIMER_SYNC_SYNCWT2_TB

#define TIMER_SYNC_SYNCWT2_TB   0x00020000

◆ TIMER_SYNC_SYNCWT3_M

#define TIMER_SYNC_SYNCWT3_M   0x000C0000

◆ TIMER_SYNC_SYNCWT3_NONE

#define TIMER_SYNC_SYNCWT3_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT3_TA

#define TIMER_SYNC_SYNCWT3_TA   0x00040000

◆ TIMER_SYNC_SYNCWT3_TATB

#define TIMER_SYNC_SYNCWT3_TATB   0x000C0000

◆ TIMER_SYNC_SYNCWT3_TB

#define TIMER_SYNC_SYNCWT3_TB   0x00080000

◆ TIMER_SYNC_SYNCWT4_M

#define TIMER_SYNC_SYNCWT4_M   0x00300000

◆ TIMER_SYNC_SYNCWT4_NONE

#define TIMER_SYNC_SYNCWT4_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT4_TA

#define TIMER_SYNC_SYNCWT4_TA   0x00100000

◆ TIMER_SYNC_SYNCWT4_TATB

#define TIMER_SYNC_SYNCWT4_TATB   0x00300000

◆ TIMER_SYNC_SYNCWT4_TB

#define TIMER_SYNC_SYNCWT4_TB   0x00200000

◆ TIMER_SYNC_SYNCWT5_M

#define TIMER_SYNC_SYNCWT5_M   0x00C00000

◆ TIMER_SYNC_SYNCWT5_NONE

#define TIMER_SYNC_SYNCWT5_NONE   0x00000000

◆ TIMER_SYNC_SYNCWT5_TA

#define TIMER_SYNC_SYNCWT5_TA   0x00400000

◆ TIMER_SYNC_SYNCWT5_TATB

#define TIMER_SYNC_SYNCWT5_TATB   0x00C00000

◆ TIMER_SYNC_SYNCWT5_TB

#define TIMER_SYNC_SYNCWT5_TB   0x00800000

◆ TIMER_TAILR_M

#define TIMER_TAILR_M   0xFFFFFFFF

◆ TIMER_TAILR_S

#define TIMER_TAILR_S   0

◆ TIMER_TAMATCHR_TAMR_M

#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF

◆ TIMER_TAMATCHR_TAMR_S

#define TIMER_TAMATCHR_TAMR_S   0

◆ TIMER_TAMR_TAAMS

#define TIMER_TAMR_TAAMS   0x00000008

◆ TIMER_TAMR_TACDIR

#define TIMER_TAMR_TACDIR   0x00000010

◆ TIMER_TAMR_TACMR

#define TIMER_TAMR_TACMR   0x00000004

◆ TIMER_TAMR_TAILD

#define TIMER_TAMR_TAILD   0x00000100

◆ TIMER_TAMR_TAMIE

#define TIMER_TAMR_TAMIE   0x00000020

◆ TIMER_TAMR_TAMR_1_SHOT

#define TIMER_TAMR_TAMR_1_SHOT   0x00000001

◆ TIMER_TAMR_TAMR_CAP

#define TIMER_TAMR_TAMR_CAP   0x00000003

◆ TIMER_TAMR_TAMR_M

#define TIMER_TAMR_TAMR_M   0x00000003

◆ TIMER_TAMR_TAMR_PERIOD

#define TIMER_TAMR_TAMR_PERIOD   0x00000002

◆ TIMER_TAMR_TAMRSU

#define TIMER_TAMR_TAMRSU   0x00000400

◆ TIMER_TAMR_TAPLO

#define TIMER_TAMR_TAPLO   0x00000800

◆ TIMER_TAMR_TAPWMIE

#define TIMER_TAMR_TAPWMIE   0x00000200

◆ TIMER_TAMR_TASNAPS

#define TIMER_TAMR_TASNAPS   0x00000080

◆ TIMER_TAMR_TAWOT

#define TIMER_TAMR_TAWOT   0x00000040

◆ TIMER_TAPMR_TAPSMR_M

#define TIMER_TAPMR_TAPSMR_M   0x000000FF

◆ TIMER_TAPMR_TAPSMR_S

#define TIMER_TAPMR_TAPSMR_S   0

◆ TIMER_TAPMR_TAPSMRH_M

#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00

◆ TIMER_TAPMR_TAPSMRH_S

#define TIMER_TAPMR_TAPSMRH_S   8

◆ TIMER_TAPR_TAPSR_M

#define TIMER_TAPR_TAPSR_M   0x000000FF

◆ TIMER_TAPR_TAPSR_S

#define TIMER_TAPR_TAPSR_S   0

◆ TIMER_TAPR_TAPSRH_M

#define TIMER_TAPR_TAPSRH_M   0x0000FF00

◆ TIMER_TAPR_TAPSRH_S

#define TIMER_TAPR_TAPSRH_S   8

◆ TIMER_TAPS_PSS_M

#define TIMER_TAPS_PSS_M   0x0000FFFF

◆ TIMER_TAPS_PSS_S

#define TIMER_TAPS_PSS_S   0

◆ TIMER_TAPV_PSV_M

#define TIMER_TAPV_PSV_M   0x0000FFFF

◆ TIMER_TAPV_PSV_S

#define TIMER_TAPV_PSV_S   0

◆ TIMER_TAR_M

#define TIMER_TAR_M   0xFFFFFFFF

◆ TIMER_TAR_S

#define TIMER_TAR_S   0

◆ TIMER_TAV_M

#define TIMER_TAV_M   0xFFFFFFFF

◆ TIMER_TAV_S

#define TIMER_TAV_S   0

◆ TIMER_TBILR_M

#define TIMER_TBILR_M   0xFFFFFFFF

◆ TIMER_TBILR_S

#define TIMER_TBILR_S   0

◆ TIMER_TBMATCHR_TBMR_M

#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF

◆ TIMER_TBMATCHR_TBMR_S

#define TIMER_TBMATCHR_TBMR_S   0

◆ TIMER_TBMR_TBAMS

#define TIMER_TBMR_TBAMS   0x00000008

◆ TIMER_TBMR_TBCDIR

#define TIMER_TBMR_TBCDIR   0x00000010

◆ TIMER_TBMR_TBCMR

#define TIMER_TBMR_TBCMR   0x00000004

◆ TIMER_TBMR_TBILD

#define TIMER_TBMR_TBILD   0x00000100

◆ TIMER_TBMR_TBMIE

#define TIMER_TBMR_TBMIE   0x00000020

◆ TIMER_TBMR_TBMR_1_SHOT

#define TIMER_TBMR_TBMR_1_SHOT   0x00000001

◆ TIMER_TBMR_TBMR_CAP

#define TIMER_TBMR_TBMR_CAP   0x00000003

◆ TIMER_TBMR_TBMR_M

#define TIMER_TBMR_TBMR_M   0x00000003

◆ TIMER_TBMR_TBMR_PERIOD

#define TIMER_TBMR_TBMR_PERIOD   0x00000002

◆ TIMER_TBMR_TBMRSU

#define TIMER_TBMR_TBMRSU   0x00000400

◆ TIMER_TBMR_TBPLO

#define TIMER_TBMR_TBPLO   0x00000800

◆ TIMER_TBMR_TBPWMIE

#define TIMER_TBMR_TBPWMIE   0x00000200

◆ TIMER_TBMR_TBSNAPS

#define TIMER_TBMR_TBSNAPS   0x00000080

◆ TIMER_TBMR_TBWOT

#define TIMER_TBMR_TBWOT   0x00000040

◆ TIMER_TBPMR_TBPSMR_M

#define TIMER_TBPMR_TBPSMR_M   0x000000FF

◆ TIMER_TBPMR_TBPSMR_S

#define TIMER_TBPMR_TBPSMR_S   0

◆ TIMER_TBPMR_TBPSMRH_M

#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00

◆ TIMER_TBPMR_TBPSMRH_S

#define TIMER_TBPMR_TBPSMRH_S   8

◆ TIMER_TBPR_TBPSR_M

#define TIMER_TBPR_TBPSR_M   0x000000FF

◆ TIMER_TBPR_TBPSR_S

#define TIMER_TBPR_TBPSR_S   0

◆ TIMER_TBPR_TBPSRH_M

#define TIMER_TBPR_TBPSRH_M   0x0000FF00

◆ TIMER_TBPR_TBPSRH_S

#define TIMER_TBPR_TBPSRH_S   8

◆ TIMER_TBPS_PSS_M

#define TIMER_TBPS_PSS_M   0x0000FFFF

◆ TIMER_TBPS_PSS_S

#define TIMER_TBPS_PSS_S   0

◆ TIMER_TBPV_PSV_M

#define TIMER_TBPV_PSV_M   0x0000FFFF

◆ TIMER_TBPV_PSV_S

#define TIMER_TBPV_PSV_S   0

◆ TIMER_TBR_M

#define TIMER_TBR_M   0xFFFFFFFF

◆ TIMER_TBR_S

#define TIMER_TBR_S   0

◆ TIMER_TBV_M

#define TIMER_TBV_M   0xFFFFFFFF

◆ TIMER_TBV_S

#define TIMER_TBV_S   0

◆ UART0_9BITADDR_R

#define UART0_9BITADDR_R   (*((volatile u32 *)0x4000C0A4))

◆ UART0_9BITAMASK_R

#define UART0_9BITAMASK_R   (*((volatile u32 *)0x4000C0A8))

◆ UART0_CC_R

#define UART0_CC_R   (*((volatile u32 *)0x4000CFC8))

◆ UART0_CTL_R

#define UART0_CTL_R   (*((volatile u32 *)0x4000C030))

◆ UART0_DMACTL_R

#define UART0_DMACTL_R   (*((volatile u32 *)0x4000C048))

◆ UART0_DR_R

#define UART0_DR_R   (*((volatile u32 *)0x4000C000))

◆ UART0_ECR_R

#define UART0_ECR_R   (*((volatile u32 *)0x4000C004))

◆ UART0_FBRD_R

#define UART0_FBRD_R   (*((volatile u32 *)0x4000C028))

◆ UART0_FR_R

#define UART0_FR_R   (*((volatile u32 *)0x4000C018))

◆ UART0_IBRD_R

#define UART0_IBRD_R   (*((volatile u32 *)0x4000C024))

◆ UART0_ICR_R

#define UART0_ICR_R   (*((volatile u32 *)0x4000C044))

◆ UART0_IFLS_R

#define UART0_IFLS_R   (*((volatile u32 *)0x4000C034))

◆ UART0_ILPR_R

#define UART0_ILPR_R   (*((volatile u32 *)0x4000C020))

◆ UART0_IM_R

#define UART0_IM_R   (*((volatile u32 *)0x4000C038))

◆ UART0_LCRH_R

#define UART0_LCRH_R   (*((volatile u32 *)0x4000C02C))

◆ UART0_MIS_R

#define UART0_MIS_R   (*((volatile u32 *)0x4000C040))

◆ UART0_PP_R

#define UART0_PP_R   (*((volatile u32 *)0x4000CFC0))

◆ UART0_RIS_R

#define UART0_RIS_R   (*((volatile u32 *)0x4000C03C))

◆ UART0_RSR_R

#define UART0_RSR_R   (*((volatile u32 *)0x4000C004))

◆ UART1_9BITADDR_R

#define UART1_9BITADDR_R   (*((volatile u32 *)0x4000D0A4))

◆ UART1_9BITAMASK_R

#define UART1_9BITAMASK_R   (*((volatile u32 *)0x4000D0A8))

◆ UART1_CC_R

#define UART1_CC_R   (*((volatile u32 *)0x4000DFC8))

◆ UART1_CTL_R

#define UART1_CTL_R   (*((volatile u32 *)0x4000D030))

◆ UART1_DMACTL_R

#define UART1_DMACTL_R   (*((volatile u32 *)0x4000D048))

◆ UART1_DR_R

#define UART1_DR_R   (*((volatile u32 *)0x4000D000))

◆ UART1_ECR_R

#define UART1_ECR_R   (*((volatile u32 *)0x4000D004))

◆ UART1_FBRD_R

#define UART1_FBRD_R   (*((volatile u32 *)0x4000D028))

◆ UART1_FR_R

#define UART1_FR_R   (*((volatile u32 *)0x4000D018))

◆ UART1_IBRD_R

#define UART1_IBRD_R   (*((volatile u32 *)0x4000D024))

◆ UART1_ICR_R

#define UART1_ICR_R   (*((volatile u32 *)0x4000D044))

◆ UART1_IFLS_R

#define UART1_IFLS_R   (*((volatile u32 *)0x4000D034))

◆ UART1_ILPR_R

#define UART1_ILPR_R   (*((volatile u32 *)0x4000D020))

◆ UART1_IM_R

#define UART1_IM_R   (*((volatile u32 *)0x4000D038))

◆ UART1_LCRH_R

#define UART1_LCRH_R   (*((volatile u32 *)0x4000D02C))

◆ UART1_MIS_R

#define UART1_MIS_R   (*((volatile u32 *)0x4000D040))

◆ UART1_PP_R

#define UART1_PP_R   (*((volatile u32 *)0x4000DFC0))

◆ UART1_RIS_R

#define UART1_RIS_R   (*((volatile u32 *)0x4000D03C))

◆ UART1_RSR_R

#define UART1_RSR_R   (*((volatile u32 *)0x4000D004))

◆ UART2_9BITADDR_R

#define UART2_9BITADDR_R   (*((volatile u32 *)0x4000E0A4))

◆ UART2_9BITAMASK_R

#define UART2_9BITAMASK_R   (*((volatile u32 *)0x4000E0A8))

◆ UART2_CC_R

#define UART2_CC_R   (*((volatile u32 *)0x4000EFC8))

◆ UART2_CTL_R

#define UART2_CTL_R   (*((volatile u32 *)0x4000E030))

◆ UART2_DMACTL_R

#define UART2_DMACTL_R   (*((volatile u32 *)0x4000E048))

◆ UART2_DR_R

#define UART2_DR_R   (*((volatile u32 *)0x4000E000))

◆ UART2_ECR_R

#define UART2_ECR_R   (*((volatile u32 *)0x4000E004))

◆ UART2_FBRD_R

#define UART2_FBRD_R   (*((volatile u32 *)0x4000E028))

◆ UART2_FR_R

#define UART2_FR_R   (*((volatile u32 *)0x4000E018))

◆ UART2_IBRD_R

#define UART2_IBRD_R   (*((volatile u32 *)0x4000E024))

◆ UART2_ICR_R

#define UART2_ICR_R   (*((volatile u32 *)0x4000E044))

◆ UART2_IFLS_R

#define UART2_IFLS_R   (*((volatile u32 *)0x4000E034))

◆ UART2_ILPR_R

#define UART2_ILPR_R   (*((volatile u32 *)0x4000E020))

◆ UART2_IM_R

#define UART2_IM_R   (*((volatile u32 *)0x4000E038))

◆ UART2_LCRH_R

#define UART2_LCRH_R   (*((volatile u32 *)0x4000E02C))

◆ UART2_MIS_R

#define UART2_MIS_R   (*((volatile u32 *)0x4000E040))

◆ UART2_PP_R

#define UART2_PP_R   (*((volatile u32 *)0x4000EFC0))

◆ UART2_RIS_R

#define UART2_RIS_R   (*((volatile u32 *)0x4000E03C))

◆ UART2_RSR_R

#define UART2_RSR_R   (*((volatile u32 *)0x4000E004))

◆ UART3_9BITADDR_R

#define UART3_9BITADDR_R   (*((volatile u32 *)0x4000F0A4))

◆ UART3_9BITAMASK_R

#define UART3_9BITAMASK_R   (*((volatile u32 *)0x4000F0A8))

◆ UART3_CC_R

#define UART3_CC_R   (*((volatile u32 *)0x4000FFC8))

◆ UART3_CTL_R

#define UART3_CTL_R   (*((volatile u32 *)0x4000F030))

◆ UART3_DMACTL_R

#define UART3_DMACTL_R   (*((volatile u32 *)0x4000F048))

◆ UART3_DR_R

#define UART3_DR_R   (*((volatile u32 *)0x4000F000))

◆ UART3_ECR_R

#define UART3_ECR_R   (*((volatile u32 *)0x4000F004))

◆ UART3_FBRD_R

#define UART3_FBRD_R   (*((volatile u32 *)0x4000F028))

◆ UART3_FR_R

#define UART3_FR_R   (*((volatile u32 *)0x4000F018))

◆ UART3_IBRD_R

#define UART3_IBRD_R   (*((volatile u32 *)0x4000F024))

◆ UART3_ICR_R

#define UART3_ICR_R   (*((volatile u32 *)0x4000F044))

◆ UART3_IFLS_R

#define UART3_IFLS_R   (*((volatile u32 *)0x4000F034))

◆ UART3_ILPR_R

#define UART3_ILPR_R   (*((volatile u32 *)0x4000F020))

◆ UART3_IM_R

#define UART3_IM_R   (*((volatile u32 *)0x4000F038))

◆ UART3_LCRH_R

#define UART3_LCRH_R   (*((volatile u32 *)0x4000F02C))

◆ UART3_MIS_R

#define UART3_MIS_R   (*((volatile u32 *)0x4000F040))

◆ UART3_PP_R

#define UART3_PP_R   (*((volatile u32 *)0x4000FFC0))

◆ UART3_RIS_R

#define UART3_RIS_R   (*((volatile u32 *)0x4000F03C))

◆ UART3_RSR_R

#define UART3_RSR_R   (*((volatile u32 *)0x4000F004))

◆ UART4_9BITADDR_R

#define UART4_9BITADDR_R   (*((volatile u32 *)0x400100A4))

◆ UART4_9BITAMASK_R

#define UART4_9BITAMASK_R   (*((volatile u32 *)0x400100A8))

◆ UART4_CC_R

#define UART4_CC_R   (*((volatile u32 *)0x40010FC8))

◆ UART4_CTL_R

#define UART4_CTL_R   (*((volatile u32 *)0x40010030))

◆ UART4_DMACTL_R

#define UART4_DMACTL_R   (*((volatile u32 *)0x40010048))

◆ UART4_DR_R

#define UART4_DR_R   (*((volatile u32 *)0x40010000))

◆ UART4_ECR_R

#define UART4_ECR_R   (*((volatile u32 *)0x40010004))

◆ UART4_FBRD_R

#define UART4_FBRD_R   (*((volatile u32 *)0x40010028))

◆ UART4_FR_R

#define UART4_FR_R   (*((volatile u32 *)0x40010018))

◆ UART4_IBRD_R

#define UART4_IBRD_R   (*((volatile u32 *)0x40010024))

◆ UART4_ICR_R

#define UART4_ICR_R   (*((volatile u32 *)0x40010044))

◆ UART4_IFLS_R

#define UART4_IFLS_R   (*((volatile u32 *)0x40010034))

◆ UART4_ILPR_R

#define UART4_ILPR_R   (*((volatile u32 *)0x40010020))

◆ UART4_IM_R

#define UART4_IM_R   (*((volatile u32 *)0x40010038))

◆ UART4_LCRH_R

#define UART4_LCRH_R   (*((volatile u32 *)0x4001002C))

◆ UART4_MIS_R

#define UART4_MIS_R   (*((volatile u32 *)0x40010040))

◆ UART4_PP_R

#define UART4_PP_R   (*((volatile u32 *)0x40010FC0))

◆ UART4_RIS_R

#define UART4_RIS_R   (*((volatile u32 *)0x4001003C))

◆ UART4_RSR_R

#define UART4_RSR_R   (*((volatile u32 *)0x40010004))

◆ UART5_9BITADDR_R

#define UART5_9BITADDR_R   (*((volatile u32 *)0x400110A4))

◆ UART5_9BITAMASK_R

#define UART5_9BITAMASK_R   (*((volatile u32 *)0x400110A8))

◆ UART5_CC_R

#define UART5_CC_R   (*((volatile u32 *)0x40011FC8))

◆ UART5_CTL_R

#define UART5_CTL_R   (*((volatile u32 *)0x40011030))

◆ UART5_DMACTL_R

#define UART5_DMACTL_R   (*((volatile u32 *)0x40011048))

◆ UART5_DR_R

#define UART5_DR_R   (*((volatile u32 *)0x40011000))

◆ UART5_ECR_R

#define UART5_ECR_R   (*((volatile u32 *)0x40011004))

◆ UART5_FBRD_R

#define UART5_FBRD_R   (*((volatile u32 *)0x40011028))

◆ UART5_FR_R

#define UART5_FR_R   (*((volatile u32 *)0x40011018))

◆ UART5_IBRD_R

#define UART5_IBRD_R   (*((volatile u32 *)0x40011024))

◆ UART5_ICR_R

#define UART5_ICR_R   (*((volatile u32 *)0x40011044))

◆ UART5_IFLS_R

#define UART5_IFLS_R   (*((volatile u32 *)0x40011034))

◆ UART5_ILPR_R

#define UART5_ILPR_R   (*((volatile u32 *)0x40011020))

◆ UART5_IM_R

#define UART5_IM_R   (*((volatile u32 *)0x40011038))

◆ UART5_LCRH_R

#define UART5_LCRH_R   (*((volatile u32 *)0x4001102C))

◆ UART5_MIS_R

#define UART5_MIS_R   (*((volatile u32 *)0x40011040))

◆ UART5_PP_R

#define UART5_PP_R   (*((volatile u32 *)0x40011FC0))

◆ UART5_RIS_R

#define UART5_RIS_R   (*((volatile u32 *)0x4001103C))

◆ UART5_RSR_R

#define UART5_RSR_R   (*((volatile u32 *)0x40011004))

◆ UART6_9BITADDR_R

#define UART6_9BITADDR_R   (*((volatile u32 *)0x400120A4))

◆ UART6_9BITAMASK_R

#define UART6_9BITAMASK_R   (*((volatile u32 *)0x400120A8))

◆ UART6_CC_R

#define UART6_CC_R   (*((volatile u32 *)0x40012FC8))

◆ UART6_CTL_R

#define UART6_CTL_R   (*((volatile u32 *)0x40012030))

◆ UART6_DMACTL_R

#define UART6_DMACTL_R   (*((volatile u32 *)0x40012048))

◆ UART6_DR_R

#define UART6_DR_R   (*((volatile u32 *)0x40012000))

◆ UART6_ECR_R

#define UART6_ECR_R   (*((volatile u32 *)0x40012004))

◆ UART6_FBRD_R

#define UART6_FBRD_R   (*((volatile u32 *)0x40012028))

◆ UART6_FR_R

#define UART6_FR_R   (*((volatile u32 *)0x40012018))

◆ UART6_IBRD_R

#define UART6_IBRD_R   (*((volatile u32 *)0x40012024))

◆ UART6_ICR_R

#define UART6_ICR_R   (*((volatile u32 *)0x40012044))

◆ UART6_IFLS_R

#define UART6_IFLS_R   (*((volatile u32 *)0x40012034))

◆ UART6_ILPR_R

#define UART6_ILPR_R   (*((volatile u32 *)0x40012020))

◆ UART6_IM_R

#define UART6_IM_R   (*((volatile u32 *)0x40012038))

◆ UART6_LCRH_R

#define UART6_LCRH_R   (*((volatile u32 *)0x4001202C))

◆ UART6_MIS_R

#define UART6_MIS_R   (*((volatile u32 *)0x40012040))

◆ UART6_PP_R

#define UART6_PP_R   (*((volatile u32 *)0x40012FC0))

◆ UART6_RIS_R

#define UART6_RIS_R   (*((volatile u32 *)0x4001203C))

◆ UART6_RSR_R

#define UART6_RSR_R   (*((volatile u32 *)0x40012004))

◆ UART7_9BITADDR_R

#define UART7_9BITADDR_R   (*((volatile u32 *)0x400130A4))

◆ UART7_9BITAMASK_R

#define UART7_9BITAMASK_R   (*((volatile u32 *)0x400130A8))

◆ UART7_CC_R

#define UART7_CC_R   (*((volatile u32 *)0x40013FC8))

◆ UART7_CTL_R

#define UART7_CTL_R   (*((volatile u32 *)0x40013030))

◆ UART7_DMACTL_R

#define UART7_DMACTL_R   (*((volatile u32 *)0x40013048))

◆ UART7_DR_R

#define UART7_DR_R   (*((volatile u32 *)0x40013000))

◆ UART7_ECR_R

#define UART7_ECR_R   (*((volatile u32 *)0x40013004))

◆ UART7_FBRD_R

#define UART7_FBRD_R   (*((volatile u32 *)0x40013028))

◆ UART7_FR_R

#define UART7_FR_R   (*((volatile u32 *)0x40013018))

◆ UART7_IBRD_R

#define UART7_IBRD_R   (*((volatile u32 *)0x40013024))

◆ UART7_ICR_R

#define UART7_ICR_R   (*((volatile u32 *)0x40013044))

◆ UART7_IFLS_R

#define UART7_IFLS_R   (*((volatile u32 *)0x40013034))

◆ UART7_ILPR_R

#define UART7_ILPR_R   (*((volatile u32 *)0x40013020))

◆ UART7_IM_R

#define UART7_IM_R   (*((volatile u32 *)0x40013038))

◆ UART7_LCRH_R

#define UART7_LCRH_R   (*((volatile u32 *)0x4001302C))

◆ UART7_MIS_R

#define UART7_MIS_R   (*((volatile u32 *)0x40013040))

◆ UART7_PP_R

#define UART7_PP_R   (*((volatile u32 *)0x40013FC0))

◆ UART7_RIS_R

#define UART7_RIS_R   (*((volatile u32 *)0x4001303C))

◆ UART7_RSR_R

#define UART7_RSR_R   (*((volatile u32 *)0x40013004))

◆ UART_9BITADDR_9BITEN

#define UART_9BITADDR_9BITEN   0x00008000

◆ UART_9BITADDR_ADDR_M

#define UART_9BITADDR_ADDR_M   0x000000FF

◆ UART_9BITADDR_ADDR_S

#define UART_9BITADDR_ADDR_S   0

◆ UART_9BITAMASK_MASK_M

#define UART_9BITAMASK_MASK_M   0x000000FF

◆ UART_9BITAMASK_MASK_S

#define UART_9BITAMASK_MASK_S   0

◆ UART_CC_CS_M

#define UART_CC_CS_M   0x0000000F

◆ UART_CC_CS_PIOSC

#define UART_CC_CS_PIOSC   0x00000005

◆ UART_CC_CS_SYSCLK

#define UART_CC_CS_SYSCLK   0x00000000

◆ UART_CTL_CTSEN

#define UART_CTL_CTSEN   0x00008000

◆ UART_CTL_EOT

#define UART_CTL_EOT   0x00000010

◆ UART_CTL_HSE

#define UART_CTL_HSE   0x00000020

◆ UART_CTL_LBE

#define UART_CTL_LBE   0x00000080

◆ UART_CTL_RTS

#define UART_CTL_RTS   0x00000800

◆ UART_CTL_RTSEN

#define UART_CTL_RTSEN   0x00004000

◆ UART_CTL_RXE

#define UART_CTL_RXE   0x00000200

◆ UART_CTL_SIREN

#define UART_CTL_SIREN   0x00000002

◆ UART_CTL_SIRLP

#define UART_CTL_SIRLP   0x00000004

◆ UART_CTL_SMART

#define UART_CTL_SMART   0x00000008

◆ UART_CTL_TXE

#define UART_CTL_TXE   0x00000100

◆ UART_CTL_UARTEN

#define UART_CTL_UARTEN   0x00000001

◆ UART_DMACTL_DMAERR

#define UART_DMACTL_DMAERR   0x00000004

◆ UART_DMACTL_RXDMAE

#define UART_DMACTL_RXDMAE   0x00000001

◆ UART_DMACTL_TXDMAE

#define UART_DMACTL_TXDMAE   0x00000002

◆ UART_DR_BE

#define UART_DR_BE   0x00000400

◆ UART_DR_DATA_M

#define UART_DR_DATA_M   0x000000FF

◆ UART_DR_DATA_S

#define UART_DR_DATA_S   0

◆ UART_DR_FE

#define UART_DR_FE   0x00000100

◆ UART_DR_OE

#define UART_DR_OE   0x00000800

◆ UART_DR_PE

#define UART_DR_PE   0x00000200

◆ UART_ECR_DATA_M

#define UART_ECR_DATA_M   0x000000FF

◆ UART_ECR_DATA_S

#define UART_ECR_DATA_S   0

◆ UART_FBRD_DIVFRAC_M

#define UART_FBRD_DIVFRAC_M   0x0000003F

◆ UART_FBRD_DIVFRAC_S

#define UART_FBRD_DIVFRAC_S   0

◆ UART_FR_BUSY

#define UART_FR_BUSY   0x00000008

◆ UART_FR_CTS

#define UART_FR_CTS   0x00000001

◆ UART_FR_RXFE

#define UART_FR_RXFE   0x00000010

◆ UART_FR_RXFF

#define UART_FR_RXFF   0x00000040

◆ UART_FR_TXFE

#define UART_FR_TXFE   0x00000080

◆ UART_FR_TXFF

#define UART_FR_TXFF   0x00000020

◆ UART_IBRD_DIVINT_M

#define UART_IBRD_DIVINT_M   0x0000FFFF

◆ UART_IBRD_DIVINT_S

#define UART_IBRD_DIVINT_S   0

◆ UART_ICR_9BITIC

#define UART_ICR_9BITIC   0x00001000

◆ UART_ICR_BEIC

#define UART_ICR_BEIC   0x00000200

◆ UART_ICR_CTSMIC

#define UART_ICR_CTSMIC   0x00000002

◆ UART_ICR_FEIC

#define UART_ICR_FEIC   0x00000080

◆ UART_ICR_OEIC

#define UART_ICR_OEIC   0x00000400

◆ UART_ICR_PEIC

#define UART_ICR_PEIC   0x00000100

◆ UART_ICR_RTIC

#define UART_ICR_RTIC   0x00000040

◆ UART_ICR_RXIC

#define UART_ICR_RXIC   0x00000010

◆ UART_ICR_TXIC

#define UART_ICR_TXIC   0x00000020

◆ UART_IFLS_RX1_8

#define UART_IFLS_RX1_8   0x00000000

◆ UART_IFLS_RX2_8

#define UART_IFLS_RX2_8   0x00000008

◆ UART_IFLS_RX4_8

#define UART_IFLS_RX4_8   0x00000010

◆ UART_IFLS_RX6_8

#define UART_IFLS_RX6_8   0x00000018

◆ UART_IFLS_RX7_8

#define UART_IFLS_RX7_8   0x00000020

◆ UART_IFLS_RX_M

#define UART_IFLS_RX_M   0x00000038

◆ UART_IFLS_TX1_8

#define UART_IFLS_TX1_8   0x00000000

◆ UART_IFLS_TX2_8

#define UART_IFLS_TX2_8   0x00000001

◆ UART_IFLS_TX4_8

#define UART_IFLS_TX4_8   0x00000002

◆ UART_IFLS_TX6_8

#define UART_IFLS_TX6_8   0x00000003

◆ UART_IFLS_TX7_8

#define UART_IFLS_TX7_8   0x00000004

◆ UART_IFLS_TX_M

#define UART_IFLS_TX_M   0x00000007

◆ UART_ILPR_ILPDVSR_M

#define UART_ILPR_ILPDVSR_M   0x000000FF

◆ UART_ILPR_ILPDVSR_S

#define UART_ILPR_ILPDVSR_S   0

◆ UART_IM_9BITIM

#define UART_IM_9BITIM   0x00001000

◆ UART_IM_BEIM

#define UART_IM_BEIM   0x00000200

◆ UART_IM_CTSMIM

#define UART_IM_CTSMIM   0x00000002

◆ UART_IM_FEIM

#define UART_IM_FEIM   0x00000080

◆ UART_IM_OEIM

#define UART_IM_OEIM   0x00000400

◆ UART_IM_PEIM

#define UART_IM_PEIM   0x00000100

◆ UART_IM_RTIM

#define UART_IM_RTIM   0x00000040

◆ UART_IM_RXIM

#define UART_IM_RXIM   0x00000010

◆ UART_IM_TXIM

#define UART_IM_TXIM   0x00000020

◆ UART_LCRH_BRK

#define UART_LCRH_BRK   0x00000001

◆ UART_LCRH_EPS

#define UART_LCRH_EPS   0x00000004

◆ UART_LCRH_FEN

#define UART_LCRH_FEN   0x00000010

◆ UART_LCRH_PEN

#define UART_LCRH_PEN   0x00000002

◆ UART_LCRH_SPS

#define UART_LCRH_SPS   0x00000080

◆ UART_LCRH_STP2

#define UART_LCRH_STP2   0x00000008

◆ UART_LCRH_WLEN_5

#define UART_LCRH_WLEN_5   0x00000000

◆ UART_LCRH_WLEN_6

#define UART_LCRH_WLEN_6   0x00000020

◆ UART_LCRH_WLEN_7

#define UART_LCRH_WLEN_7   0x00000040

◆ UART_LCRH_WLEN_8

#define UART_LCRH_WLEN_8   0x00000060

◆ UART_LCRH_WLEN_M

#define UART_LCRH_WLEN_M   0x00000060

◆ UART_MIS_9BITMIS

#define UART_MIS_9BITMIS   0x00001000

◆ UART_MIS_BEMIS

#define UART_MIS_BEMIS   0x00000200

◆ UART_MIS_CTSMIS

#define UART_MIS_CTSMIS   0x00000002

◆ UART_MIS_FEMIS

#define UART_MIS_FEMIS   0x00000080

◆ UART_MIS_OEMIS

#define UART_MIS_OEMIS   0x00000400

◆ UART_MIS_PEMIS

#define UART_MIS_PEMIS   0x00000100

◆ UART_MIS_RTMIS

#define UART_MIS_RTMIS   0x00000040

◆ UART_MIS_RXMIS

#define UART_MIS_RXMIS   0x00000010

◆ UART_MIS_TXMIS

#define UART_MIS_TXMIS   0x00000020

◆ UART_PP_NB

#define UART_PP_NB   0x00000002

◆ UART_PP_SC

#define UART_PP_SC   0x00000001

◆ UART_RIS_9BITRIS

#define UART_RIS_9BITRIS   0x00001000

◆ UART_RIS_BERIS

#define UART_RIS_BERIS   0x00000200

◆ UART_RIS_CTSRIS

#define UART_RIS_CTSRIS   0x00000002

◆ UART_RIS_FERIS

#define UART_RIS_FERIS   0x00000080

◆ UART_RIS_OERIS

#define UART_RIS_OERIS   0x00000400

◆ UART_RIS_PERIS

#define UART_RIS_PERIS   0x00000100

◆ UART_RIS_RTRIS

#define UART_RIS_RTRIS   0x00000040

◆ UART_RIS_RXRIS

#define UART_RIS_RXRIS   0x00000010

◆ UART_RIS_TXRIS

#define UART_RIS_TXRIS   0x00000020

◆ UART_RSR_BE

#define UART_RSR_BE   0x00000004

◆ UART_RSR_FE

#define UART_RSR_FE   0x00000001

◆ UART_RSR_OE

#define UART_RSR_OE   0x00000008

◆ UART_RSR_PE

#define UART_RSR_PE   0x00000002

◆ UDMA_ALTBASE_ADDR_M

#define UDMA_ALTBASE_ADDR_M   0xFFFFFFFF

◆ UDMA_ALTBASE_ADDR_S

#define UDMA_ALTBASE_ADDR_S   0

◆ UDMA_ALTBASE_R

#define UDMA_ALTBASE_R   (*((volatile u32 *)0x400FF00C))

◆ UDMA_ALTCLR_CLR_M

#define UDMA_ALTCLR_CLR_M   0xFFFFFFFF

◆ UDMA_ALTCLR_R

#define UDMA_ALTCLR_R   (*((volatile u32 *)0x400FF034))

◆ UDMA_ALTSET_R

#define UDMA_ALTSET_R   (*((volatile u32 *)0x400FF030))

◆ UDMA_ALTSET_SET_M

#define UDMA_ALTSET_SET_M   0xFFFFFFFF

◆ UDMA_CFG_MASTEN

#define UDMA_CFG_MASTEN   0x00000001

◆ UDMA_CFG_R

#define UDMA_CFG_R   (*((volatile u32 *)0x400FF004))

◆ UDMA_CHASGN_M

#define UDMA_CHASGN_M   0xFFFFFFFF

◆ UDMA_CHASGN_PRIMARY

#define UDMA_CHASGN_PRIMARY   0x00000000

◆ UDMA_CHASGN_R

#define UDMA_CHASGN_R   (*((volatile u32 *)0x400FF500))

◆ UDMA_CHASGN_SECONDARY

#define UDMA_CHASGN_SECONDARY   0x00000001

◆ UDMA_CHCTL

#define UDMA_CHCTL   0x00000008

◆ UDMA_CHCTL_ARBSIZE_1

#define UDMA_CHCTL_ARBSIZE_1   0x00000000

◆ UDMA_CHCTL_ARBSIZE_1024

#define UDMA_CHCTL_ARBSIZE_1024   0x00028000

◆ UDMA_CHCTL_ARBSIZE_128

#define UDMA_CHCTL_ARBSIZE_128   0x0001C000

◆ UDMA_CHCTL_ARBSIZE_16

#define UDMA_CHCTL_ARBSIZE_16   0x00010000

◆ UDMA_CHCTL_ARBSIZE_2

#define UDMA_CHCTL_ARBSIZE_2   0x00004000

◆ UDMA_CHCTL_ARBSIZE_256

#define UDMA_CHCTL_ARBSIZE_256   0x00020000

◆ UDMA_CHCTL_ARBSIZE_32

#define UDMA_CHCTL_ARBSIZE_32   0x00014000

◆ UDMA_CHCTL_ARBSIZE_4

#define UDMA_CHCTL_ARBSIZE_4   0x00008000

◆ UDMA_CHCTL_ARBSIZE_512

#define UDMA_CHCTL_ARBSIZE_512   0x00024000

◆ UDMA_CHCTL_ARBSIZE_64

#define UDMA_CHCTL_ARBSIZE_64   0x00018000

◆ UDMA_CHCTL_ARBSIZE_8

#define UDMA_CHCTL_ARBSIZE_8   0x0000C000

◆ UDMA_CHCTL_ARBSIZE_M

#define UDMA_CHCTL_ARBSIZE_M   0x0003C000

◆ UDMA_CHCTL_DSTINC_16

#define UDMA_CHCTL_DSTINC_16   0x40000000

◆ UDMA_CHCTL_DSTINC_32

#define UDMA_CHCTL_DSTINC_32   0x80000000

◆ UDMA_CHCTL_DSTINC_8

#define UDMA_CHCTL_DSTINC_8   0x00000000

◆ UDMA_CHCTL_DSTINC_M

#define UDMA_CHCTL_DSTINC_M   0xC0000000

◆ UDMA_CHCTL_DSTINC_NONE

#define UDMA_CHCTL_DSTINC_NONE   0xC0000000

◆ UDMA_CHCTL_DSTSIZE_16

#define UDMA_CHCTL_DSTSIZE_16   0x10000000

◆ UDMA_CHCTL_DSTSIZE_32

#define UDMA_CHCTL_DSTSIZE_32   0x20000000

◆ UDMA_CHCTL_DSTSIZE_8

#define UDMA_CHCTL_DSTSIZE_8   0x00000000

◆ UDMA_CHCTL_DSTSIZE_M

#define UDMA_CHCTL_DSTSIZE_M   0x30000000

◆ UDMA_CHCTL_NXTUSEBURST

#define UDMA_CHCTL_NXTUSEBURST   0x00000008

◆ UDMA_CHCTL_SRCINC_16

#define UDMA_CHCTL_SRCINC_16   0x04000000

◆ UDMA_CHCTL_SRCINC_32

#define UDMA_CHCTL_SRCINC_32   0x08000000

◆ UDMA_CHCTL_SRCINC_8

#define UDMA_CHCTL_SRCINC_8   0x00000000

◆ UDMA_CHCTL_SRCINC_M

#define UDMA_CHCTL_SRCINC_M   0x0C000000

◆ UDMA_CHCTL_SRCINC_NONE

#define UDMA_CHCTL_SRCINC_NONE   0x0C000000

◆ UDMA_CHCTL_SRCSIZE_16

#define UDMA_CHCTL_SRCSIZE_16   0x01000000

◆ UDMA_CHCTL_SRCSIZE_32

#define UDMA_CHCTL_SRCSIZE_32   0x02000000

◆ UDMA_CHCTL_SRCSIZE_8

#define UDMA_CHCTL_SRCSIZE_8   0x00000000

◆ UDMA_CHCTL_SRCSIZE_M

#define UDMA_CHCTL_SRCSIZE_M   0x03000000

◆ UDMA_CHCTL_XFERMODE_AUTO

#define UDMA_CHCTL_XFERMODE_AUTO    0x00000002

◆ UDMA_CHCTL_XFERMODE_BASIC

#define UDMA_CHCTL_XFERMODE_BASIC    0x00000001

◆ UDMA_CHCTL_XFERMODE_M

#define UDMA_CHCTL_XFERMODE_M   0x00000007

◆ UDMA_CHCTL_XFERMODE_MEM_SG

#define UDMA_CHCTL_XFERMODE_MEM_SG    0x00000004

◆ UDMA_CHCTL_XFERMODE_MEM_SGA

#define UDMA_CHCTL_XFERMODE_MEM_SGA    0x00000005

◆ UDMA_CHCTL_XFERMODE_PER_SG

#define UDMA_CHCTL_XFERMODE_PER_SG    0x00000006

◆ UDMA_CHCTL_XFERMODE_PER_SGA

#define UDMA_CHCTL_XFERMODE_PER_SGA    0x00000007

◆ UDMA_CHCTL_XFERMODE_PINGPONG

#define UDMA_CHCTL_XFERMODE_PINGPONG    0x00000003

◆ UDMA_CHCTL_XFERMODE_STOP

#define UDMA_CHCTL_XFERMODE_STOP    0x00000000

◆ UDMA_CHCTL_XFERSIZE_M

#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0

◆ UDMA_CHCTL_XFERSIZE_S

#define UDMA_CHCTL_XFERSIZE_S   4

◆ UDMA_CHIS_M

#define UDMA_CHIS_M   0xFFFFFFFF

◆ UDMA_CHIS_R

#define UDMA_CHIS_R   (*((volatile u32 *)0x400FF504))

◆ UDMA_CHMAP0_CH0SEL_M

#define UDMA_CHMAP0_CH0SEL_M   0x0000000F

◆ UDMA_CHMAP0_CH0SEL_S

#define UDMA_CHMAP0_CH0SEL_S   0

◆ UDMA_CHMAP0_CH1SEL_M

#define UDMA_CHMAP0_CH1SEL_M   0x000000F0

◆ UDMA_CHMAP0_CH1SEL_S

#define UDMA_CHMAP0_CH1SEL_S   4

◆ UDMA_CHMAP0_CH2SEL_M

#define UDMA_CHMAP0_CH2SEL_M   0x00000F00

◆ UDMA_CHMAP0_CH2SEL_S

#define UDMA_CHMAP0_CH2SEL_S   8

◆ UDMA_CHMAP0_CH3SEL_M

#define UDMA_CHMAP0_CH3SEL_M   0x0000F000

◆ UDMA_CHMAP0_CH3SEL_S

#define UDMA_CHMAP0_CH3SEL_S   12

◆ UDMA_CHMAP0_CH4SEL_M

#define UDMA_CHMAP0_CH4SEL_M   0x000F0000

◆ UDMA_CHMAP0_CH4SEL_S

#define UDMA_CHMAP0_CH4SEL_S   16

◆ UDMA_CHMAP0_CH5SEL_M

#define UDMA_CHMAP0_CH5SEL_M   0x00F00000

◆ UDMA_CHMAP0_CH5SEL_S

#define UDMA_CHMAP0_CH5SEL_S   20

◆ UDMA_CHMAP0_CH6SEL_M

#define UDMA_CHMAP0_CH6SEL_M   0x0F000000

◆ UDMA_CHMAP0_CH6SEL_S

#define UDMA_CHMAP0_CH6SEL_S   24

◆ UDMA_CHMAP0_CH7SEL_M

#define UDMA_CHMAP0_CH7SEL_M   0xF0000000

◆ UDMA_CHMAP0_CH7SEL_S

#define UDMA_CHMAP0_CH7SEL_S   28

◆ UDMA_CHMAP0_R

#define UDMA_CHMAP0_R   (*((volatile u32 *)0x400FF510))

◆ UDMA_CHMAP1_CH10SEL_M

#define UDMA_CHMAP1_CH10SEL_M   0x00000F00

◆ UDMA_CHMAP1_CH10SEL_S

#define UDMA_CHMAP1_CH10SEL_S   8

◆ UDMA_CHMAP1_CH11SEL_M

#define UDMA_CHMAP1_CH11SEL_M   0x0000F000

◆ UDMA_CHMAP1_CH11SEL_S

#define UDMA_CHMAP1_CH11SEL_S   12

◆ UDMA_CHMAP1_CH12SEL_M

#define UDMA_CHMAP1_CH12SEL_M   0x000F0000

◆ UDMA_CHMAP1_CH12SEL_S

#define UDMA_CHMAP1_CH12SEL_S   16

◆ UDMA_CHMAP1_CH13SEL_M

#define UDMA_CHMAP1_CH13SEL_M   0x00F00000

◆ UDMA_CHMAP1_CH13SEL_S

#define UDMA_CHMAP1_CH13SEL_S   20

◆ UDMA_CHMAP1_CH14SEL_M

#define UDMA_CHMAP1_CH14SEL_M   0x0F000000

◆ UDMA_CHMAP1_CH14SEL_S

#define UDMA_CHMAP1_CH14SEL_S   24

◆ UDMA_CHMAP1_CH15SEL_M

#define UDMA_CHMAP1_CH15SEL_M   0xF0000000

◆ UDMA_CHMAP1_CH15SEL_S

#define UDMA_CHMAP1_CH15SEL_S   28

◆ UDMA_CHMAP1_CH8SEL_M

#define UDMA_CHMAP1_CH8SEL_M   0x0000000F

◆ UDMA_CHMAP1_CH8SEL_S

#define UDMA_CHMAP1_CH8SEL_S   0

◆ UDMA_CHMAP1_CH9SEL_M

#define UDMA_CHMAP1_CH9SEL_M   0x000000F0

◆ UDMA_CHMAP1_CH9SEL_S

#define UDMA_CHMAP1_CH9SEL_S   4

◆ UDMA_CHMAP1_R

#define UDMA_CHMAP1_R   (*((volatile u32 *)0x400FF514))

◆ UDMA_CHMAP2_CH16SEL_M

#define UDMA_CHMAP2_CH16SEL_M   0x0000000F

◆ UDMA_CHMAP2_CH16SEL_S

#define UDMA_CHMAP2_CH16SEL_S   0

◆ UDMA_CHMAP2_CH17SEL_M

#define UDMA_CHMAP2_CH17SEL_M   0x000000F0

◆ UDMA_CHMAP2_CH17SEL_S

#define UDMA_CHMAP2_CH17SEL_S   4

◆ UDMA_CHMAP2_CH18SEL_M

#define UDMA_CHMAP2_CH18SEL_M   0x00000F00

◆ UDMA_CHMAP2_CH18SEL_S

#define UDMA_CHMAP2_CH18SEL_S   8

◆ UDMA_CHMAP2_CH19SEL_M

#define UDMA_CHMAP2_CH19SEL_M   0x0000F000

◆ UDMA_CHMAP2_CH19SEL_S

#define UDMA_CHMAP2_CH19SEL_S   12

◆ UDMA_CHMAP2_CH20SEL_M

#define UDMA_CHMAP2_CH20SEL_M   0x000F0000

◆ UDMA_CHMAP2_CH20SEL_S

#define UDMA_CHMAP2_CH20SEL_S   16

◆ UDMA_CHMAP2_CH21SEL_M

#define UDMA_CHMAP2_CH21SEL_M   0x00F00000

◆ UDMA_CHMAP2_CH21SEL_S

#define UDMA_CHMAP2_CH21SEL_S   20

◆ UDMA_CHMAP2_CH22SEL_M

#define UDMA_CHMAP2_CH22SEL_M   0x0F000000

◆ UDMA_CHMAP2_CH22SEL_S

#define UDMA_CHMAP2_CH22SEL_S   24

◆ UDMA_CHMAP2_CH23SEL_M

#define UDMA_CHMAP2_CH23SEL_M   0xF0000000

◆ UDMA_CHMAP2_CH23SEL_S

#define UDMA_CHMAP2_CH23SEL_S   28

◆ UDMA_CHMAP2_R

#define UDMA_CHMAP2_R   (*((volatile u32 *)0x400FF518))

◆ UDMA_CHMAP3_CH24SEL_M

#define UDMA_CHMAP3_CH24SEL_M   0x0000000F

◆ UDMA_CHMAP3_CH24SEL_S

#define UDMA_CHMAP3_CH24SEL_S   0

◆ UDMA_CHMAP3_CH25SEL_M

#define UDMA_CHMAP3_CH25SEL_M   0x000000F0

◆ UDMA_CHMAP3_CH25SEL_S

#define UDMA_CHMAP3_CH25SEL_S   4

◆ UDMA_CHMAP3_CH26SEL_M

#define UDMA_CHMAP3_CH26SEL_M   0x00000F00

◆ UDMA_CHMAP3_CH26SEL_S

#define UDMA_CHMAP3_CH26SEL_S   8

◆ UDMA_CHMAP3_CH27SEL_M

#define UDMA_CHMAP3_CH27SEL_M   0x0000F000

◆ UDMA_CHMAP3_CH27SEL_S

#define UDMA_CHMAP3_CH27SEL_S   12

◆ UDMA_CHMAP3_CH28SEL_M

#define UDMA_CHMAP3_CH28SEL_M   0x000F0000

◆ UDMA_CHMAP3_CH28SEL_S

#define UDMA_CHMAP3_CH28SEL_S   16

◆ UDMA_CHMAP3_CH29SEL_M

#define UDMA_CHMAP3_CH29SEL_M   0x00F00000

◆ UDMA_CHMAP3_CH29SEL_S

#define UDMA_CHMAP3_CH29SEL_S   20

◆ UDMA_CHMAP3_CH30SEL_M

#define UDMA_CHMAP3_CH30SEL_M   0x0F000000

◆ UDMA_CHMAP3_CH30SEL_S

#define UDMA_CHMAP3_CH30SEL_S   24

◆ UDMA_CHMAP3_CH31SEL_M

#define UDMA_CHMAP3_CH31SEL_M   0xF0000000

◆ UDMA_CHMAP3_CH31SEL_S

#define UDMA_CHMAP3_CH31SEL_S   28

◆ UDMA_CHMAP3_R

#define UDMA_CHMAP3_R   (*((volatile u32 *)0x400FF51C))

◆ UDMA_CTLBASE_ADDR_M

#define UDMA_CTLBASE_ADDR_M   0xFFFFFC00

◆ UDMA_CTLBASE_ADDR_S

#define UDMA_CTLBASE_ADDR_S   10

◆ UDMA_CTLBASE_R

#define UDMA_CTLBASE_R   (*((volatile u32 *)0x400FF008))

◆ UDMA_DSTENDP

#define UDMA_DSTENDP   0x00000004

◆ UDMA_DSTENDP_ADDR_M

#define UDMA_DSTENDP_ADDR_M   0xFFFFFFFF

◆ UDMA_DSTENDP_ADDR_S

#define UDMA_DSTENDP_ADDR_S   0

◆ UDMA_ENACLR_CLR_M

#define UDMA_ENACLR_CLR_M   0xFFFFFFFF

◆ UDMA_ENACLR_R

#define UDMA_ENACLR_R   (*((volatile u32 *)0x400FF02C))

◆ UDMA_ENASET_R

#define UDMA_ENASET_R   (*((volatile u32 *)0x400FF028))

◆ UDMA_ENASET_SET_M

#define UDMA_ENASET_SET_M   0xFFFFFFFF

◆ UDMA_ERRCLR_ERRCLR

#define UDMA_ERRCLR_ERRCLR   0x00000001

◆ UDMA_ERRCLR_R

#define UDMA_ERRCLR_R   (*((volatile u32 *)0x400FF04C))

◆ UDMA_PRIOCLR_CLR_M

#define UDMA_PRIOCLR_CLR_M   0xFFFFFFFF

◆ UDMA_PRIOCLR_R

#define UDMA_PRIOCLR_R   (*((volatile u32 *)0x400FF03C))

◆ UDMA_PRIOSET_R

#define UDMA_PRIOSET_R   (*((volatile u32 *)0x400FF038))

◆ UDMA_PRIOSET_SET_M

#define UDMA_PRIOSET_SET_M   0xFFFFFFFF

◆ UDMA_REQMASKCLR_CLR_M

#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF

◆ UDMA_REQMASKCLR_R

#define UDMA_REQMASKCLR_R   (*((volatile u32 *)0x400FF024))

◆ UDMA_REQMASKSET_R

#define UDMA_REQMASKSET_R   (*((volatile u32 *)0x400FF020))

◆ UDMA_REQMASKSET_SET_M

#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF

◆ UDMA_SRCENDP

#define UDMA_SRCENDP   0x00000000

◆ UDMA_SRCENDP_ADDR_M

#define UDMA_SRCENDP_ADDR_M   0xFFFFFFFF

◆ UDMA_SRCENDP_ADDR_S

#define UDMA_SRCENDP_ADDR_S   0

◆ UDMA_STAT_DMACHANS_M

#define UDMA_STAT_DMACHANS_M   0x001F0000

◆ UDMA_STAT_DMACHANS_S

#define UDMA_STAT_DMACHANS_S   16

◆ UDMA_STAT_MASTEN

#define UDMA_STAT_MASTEN   0x00000001

◆ UDMA_STAT_R

#define UDMA_STAT_R   (*((volatile u32 *)0x400FF000))

◆ UDMA_STAT_STATE_DONE

#define UDMA_STAT_STATE_DONE   0x00000090

◆ UDMA_STAT_STATE_IDLE

#define UDMA_STAT_STATE_IDLE   0x00000000

◆ UDMA_STAT_STATE_M

#define UDMA_STAT_STATE_M   0x000000F0

◆ UDMA_STAT_STATE_RD_CTRL

#define UDMA_STAT_STATE_RD_CTRL   0x00000010

◆ UDMA_STAT_STATE_RD_DSTENDP

#define UDMA_STAT_STATE_RD_DSTENDP    0x00000030

◆ UDMA_STAT_STATE_RD_SRCDAT

#define UDMA_STAT_STATE_RD_SRCDAT    0x00000040

◆ UDMA_STAT_STATE_RD_SRCENDP

#define UDMA_STAT_STATE_RD_SRCENDP    0x00000020

◆ UDMA_STAT_STATE_STALL

#define UDMA_STAT_STATE_STALL   0x00000080

◆ UDMA_STAT_STATE_UNDEF

#define UDMA_STAT_STATE_UNDEF   0x000000A0

◆ UDMA_STAT_STATE_WAIT

#define UDMA_STAT_STATE_WAIT   0x00000060

◆ UDMA_STAT_STATE_WR_CTRL

#define UDMA_STAT_STATE_WR_CTRL   0x00000070

◆ UDMA_STAT_STATE_WR_DSTDAT

#define UDMA_STAT_STATE_WR_DSTDAT    0x00000050

◆ UDMA_SWREQ_M

#define UDMA_SWREQ_M   0xFFFFFFFF

◆ UDMA_SWREQ_R

#define UDMA_SWREQ_R   (*((volatile u32 *)0x400FF014))

◆ UDMA_USEBURSTCLR_CLR_M

#define UDMA_USEBURSTCLR_CLR_M   0xFFFFFFFF

◆ UDMA_USEBURSTCLR_R

#define UDMA_USEBURSTCLR_R   (*((volatile u32 *)0x400FF01C))

◆ UDMA_USEBURSTSET_R

#define UDMA_USEBURSTSET_R   (*((volatile u32 *)0x400FF018))

◆ UDMA_USEBURSTSET_SET_M

#define UDMA_USEBURSTSET_SET_M   0xFFFFFFFF

◆ UDMA_WAITSTAT_R

#define UDMA_WAITSTAT_R   (*((volatile u32 *)0x400FF010))

◆ UDMA_WAITSTAT_WAITREQ_M

#define UDMA_WAITSTAT_WAITREQ_M   0xFFFFFFFF

◆ USB0_CONTIM_R

#define USB0_CONTIM_R   (*((volatile uint8_t *)0x4005007A))

◆ USB0_COUNT0_R

#define USB0_COUNT0_R   (*((volatile uint8_t *)0x40050108))

◆ USB0_CSRH0_R

#define USB0_CSRH0_R   (*((volatile uint8_t *)0x40050103))

◆ USB0_CSRL0_R

#define USB0_CSRL0_R   (*((volatile uint8_t *)0x40050102))

◆ USB0_DEVCTL_R

#define USB0_DEVCTL_R   (*((volatile uint8_t *)0x40050060))

◆ USB0_DMASEL_R

#define USB0_DMASEL_R   (*((volatile u32 *)0x40050450))

◆ USB0_DRIM_R

#define USB0_DRIM_R   (*((volatile u32 *)0x40050414))

◆ USB0_DRISC_R

#define USB0_DRISC_R   (*((volatile u32 *)0x40050418))

◆ USB0_DRRIS_R

#define USB0_DRRIS_R   (*((volatile u32 *)0x40050410))

◆ USB0_EPC_R

#define USB0_EPC_R   (*((volatile u32 *)0x40050400))

◆ USB0_EPCIM_R

#define USB0_EPCIM_R   (*((volatile u32 *)0x40050408))

◆ USB0_EPCISC_R

#define USB0_EPCISC_R   (*((volatile u32 *)0x4005040C))

◆ USB0_EPCRIS_R

#define USB0_EPCRIS_R   (*((volatile u32 *)0x40050404))

◆ USB0_EPIDX_R

#define USB0_EPIDX_R   (*((volatile uint8_t *)0x4005000E))

◆ USB0_FADDR_R

#define USB0_FADDR_R   (*((volatile uint8_t *)0x40050000))

◆ USB0_FIFO0_R

#define USB0_FIFO0_R   (*((volatile u32 *)0x40050020))

◆ USB0_FIFO1_R

#define USB0_FIFO1_R   (*((volatile u32 *)0x40050024))

◆ USB0_FIFO2_R

#define USB0_FIFO2_R   (*((volatile u32 *)0x40050028))

◆ USB0_FIFO3_R

#define USB0_FIFO3_R   (*((volatile u32 *)0x4005002C))

◆ USB0_FIFO4_R

#define USB0_FIFO4_R   (*((volatile u32 *)0x40050030))

◆ USB0_FIFO5_R

#define USB0_FIFO5_R   (*((volatile u32 *)0x40050034))

◆ USB0_FIFO6_R

#define USB0_FIFO6_R   (*((volatile u32 *)0x40050038))

◆ USB0_FIFO7_R

#define USB0_FIFO7_R   (*((volatile u32 *)0x4005003C))

◆ USB0_FRAME_R

#define USB0_FRAME_R   (*((volatile uint16_t *)0x4005000C))

◆ USB0_FSEOF_R

#define USB0_FSEOF_R   (*((volatile uint8_t *)0x4005007D))

◆ USB0_GPCS_R

#define USB0_GPCS_R   (*((volatile u32 *)0x4005041C))

◆ USB0_IDVIM_R

#define USB0_IDVIM_R   (*((volatile u32 *)0x40050448))

◆ USB0_IDVISC_R

#define USB0_IDVISC_R   (*((volatile u32 *)0x4005044C))

◆ USB0_IDVRIS_R

#define USB0_IDVRIS_R   (*((volatile u32 *)0x40050444))

◆ USB0_IE_R

#define USB0_IE_R   (*((volatile uint8_t *)0x4005000B))

◆ USB0_IS_R

#define USB0_IS_R   (*((volatile uint8_t *)0x4005000A))

◆ USB0_LSEOF_R

#define USB0_LSEOF_R   (*((volatile uint8_t *)0x4005007E))

◆ USB0_NAKLMT_R

#define USB0_NAKLMT_R   (*((volatile uint8_t *)0x4005010B))

◆ USB0_POWER_R

#define USB0_POWER_R   (*((volatile uint8_t *)0x40050001))

◆ USB0_PP_R

#define USB0_PP_R   (*((volatile u32 *)0x40050FC0))

◆ USB0_RQPKTCOUNT1_R

#define USB0_RQPKTCOUNT1_R   (*((volatile uint16_t *)0x40050304))

◆ USB0_RQPKTCOUNT2_R

#define USB0_RQPKTCOUNT2_R   (*((volatile uint16_t *)0x40050308))

◆ USB0_RQPKTCOUNT3_R

#define USB0_RQPKTCOUNT3_R   (*((volatile uint16_t *)0x4005030C))

◆ USB0_RQPKTCOUNT4_R

#define USB0_RQPKTCOUNT4_R   (*((volatile uint16_t *)0x40050310))

◆ USB0_RQPKTCOUNT5_R

#define USB0_RQPKTCOUNT5_R   (*((volatile uint16_t *)0x40050314))

◆ USB0_RQPKTCOUNT6_R

#define USB0_RQPKTCOUNT6_R   (*((volatile uint16_t *)0x40050318))

◆ USB0_RQPKTCOUNT7_R

#define USB0_RQPKTCOUNT7_R   (*((volatile uint16_t *)0x4005031C))

◆ USB0_RXCOUNT1_R

#define USB0_RXCOUNT1_R   (*((volatile uint16_t *)0x40050118))

◆ USB0_RXCOUNT2_R

#define USB0_RXCOUNT2_R   (*((volatile uint16_t *)0x40050128))

◆ USB0_RXCOUNT3_R

#define USB0_RXCOUNT3_R   (*((volatile uint16_t *)0x40050138))

◆ USB0_RXCOUNT4_R

#define USB0_RXCOUNT4_R   (*((volatile uint16_t *)0x40050148))

◆ USB0_RXCOUNT5_R

#define USB0_RXCOUNT5_R   (*((volatile uint16_t *)0x40050158))

◆ USB0_RXCOUNT6_R

#define USB0_RXCOUNT6_R   (*((volatile uint16_t *)0x40050168))

◆ USB0_RXCOUNT7_R

#define USB0_RXCOUNT7_R   (*((volatile uint16_t *)0x40050178))

◆ USB0_RXCSRH1_R

#define USB0_RXCSRH1_R   (*((volatile uint8_t *)0x40050117))

◆ USB0_RXCSRH2_R

#define USB0_RXCSRH2_R   (*((volatile uint8_t *)0x40050127))

◆ USB0_RXCSRH3_R

#define USB0_RXCSRH3_R   (*((volatile uint8_t *)0x40050137))

◆ USB0_RXCSRH4_R

#define USB0_RXCSRH4_R   (*((volatile uint8_t *)0x40050147))

◆ USB0_RXCSRH5_R

#define USB0_RXCSRH5_R   (*((volatile uint8_t *)0x40050157))

◆ USB0_RXCSRH6_R

#define USB0_RXCSRH6_R   (*((volatile uint8_t *)0x40050167))

◆ USB0_RXCSRH7_R

#define USB0_RXCSRH7_R   (*((volatile uint8_t *)0x40050177))

◆ USB0_RXCSRL1_R

#define USB0_RXCSRL1_R   (*((volatile uint8_t *)0x40050116))

◆ USB0_RXCSRL2_R

#define USB0_RXCSRL2_R   (*((volatile uint8_t *)0x40050126))

◆ USB0_RXCSRL3_R

#define USB0_RXCSRL3_R   (*((volatile uint8_t *)0x40050136))

◆ USB0_RXCSRL4_R

#define USB0_RXCSRL4_R   (*((volatile uint8_t *)0x40050146))

◆ USB0_RXCSRL5_R

#define USB0_RXCSRL5_R   (*((volatile uint8_t *)0x40050156))

◆ USB0_RXCSRL6_R

#define USB0_RXCSRL6_R   (*((volatile uint8_t *)0x40050166))

◆ USB0_RXCSRL7_R

#define USB0_RXCSRL7_R   (*((volatile uint8_t *)0x40050176))

◆ USB0_RXDPKTBUFDIS_R

#define USB0_RXDPKTBUFDIS_R   (*((volatile uint16_t *)0x40050340))

◆ USB0_RXFIFOADD_R

#define USB0_RXFIFOADD_R   (*((volatile uint16_t *)0x40050066))

◆ USB0_RXFIFOSZ_R

#define USB0_RXFIFOSZ_R   (*((volatile uint8_t *)0x40050063))

◆ USB0_RXFUNCADDR1_R

#define USB0_RXFUNCADDR1_R   (*((volatile uint8_t *)0x4005008C))

◆ USB0_RXFUNCADDR2_R

#define USB0_RXFUNCADDR2_R   (*((volatile uint8_t *)0x40050094))

◆ USB0_RXFUNCADDR3_R

#define USB0_RXFUNCADDR3_R   (*((volatile uint8_t *)0x4005009C))

◆ USB0_RXFUNCADDR4_R

#define USB0_RXFUNCADDR4_R   (*((volatile uint8_t *)0x400500A4))

◆ USB0_RXFUNCADDR5_R

#define USB0_RXFUNCADDR5_R   (*((volatile uint8_t *)0x400500AC))

◆ USB0_RXFUNCADDR6_R

#define USB0_RXFUNCADDR6_R   (*((volatile uint8_t *)0x400500B4))

◆ USB0_RXFUNCADDR7_R

#define USB0_RXFUNCADDR7_R   (*((volatile uint8_t *)0x400500BC))

◆ USB0_RXHUBADDR1_R

#define USB0_RXHUBADDR1_R   (*((volatile uint8_t *)0x4005008E))

◆ USB0_RXHUBADDR2_R

#define USB0_RXHUBADDR2_R   (*((volatile uint8_t *)0x40050096))

◆ USB0_RXHUBADDR3_R

#define USB0_RXHUBADDR3_R   (*((volatile uint8_t *)0x4005009E))

◆ USB0_RXHUBADDR4_R

#define USB0_RXHUBADDR4_R   (*((volatile uint8_t *)0x400500A6))

◆ USB0_RXHUBADDR5_R

#define USB0_RXHUBADDR5_R   (*((volatile uint8_t *)0x400500AE))

◆ USB0_RXHUBADDR6_R

#define USB0_RXHUBADDR6_R   (*((volatile uint8_t *)0x400500B6))

◆ USB0_RXHUBADDR7_R

#define USB0_RXHUBADDR7_R   (*((volatile uint8_t *)0x400500BE))

◆ USB0_RXHUBPORT1_R

#define USB0_RXHUBPORT1_R   (*((volatile uint8_t *)0x4005008F))

◆ USB0_RXHUBPORT2_R

#define USB0_RXHUBPORT2_R   (*((volatile uint8_t *)0x40050097))

◆ USB0_RXHUBPORT3_R

#define USB0_RXHUBPORT3_R   (*((volatile uint8_t *)0x4005009F))

◆ USB0_RXHUBPORT4_R

#define USB0_RXHUBPORT4_R   (*((volatile uint8_t *)0x400500A7))

◆ USB0_RXHUBPORT5_R

#define USB0_RXHUBPORT5_R   (*((volatile uint8_t *)0x400500AF))

◆ USB0_RXHUBPORT6_R

#define USB0_RXHUBPORT6_R   (*((volatile uint8_t *)0x400500B7))

◆ USB0_RXHUBPORT7_R

#define USB0_RXHUBPORT7_R   (*((volatile uint8_t *)0x400500BF))

◆ USB0_RXIE_R

#define USB0_RXIE_R   (*((volatile uint16_t *)0x40050008))

◆ USB0_RXINTERVAL1_R

#define USB0_RXINTERVAL1_R   (*((volatile uint8_t *)0x4005011D))

◆ USB0_RXINTERVAL2_R

#define USB0_RXINTERVAL2_R   (*((volatile uint8_t *)0x4005012D))

◆ USB0_RXINTERVAL3_R

#define USB0_RXINTERVAL3_R   (*((volatile uint8_t *)0x4005013D))

◆ USB0_RXINTERVAL4_R

#define USB0_RXINTERVAL4_R   (*((volatile uint8_t *)0x4005014D))

◆ USB0_RXINTERVAL5_R

#define USB0_RXINTERVAL5_R   (*((volatile uint8_t *)0x4005015D))

◆ USB0_RXINTERVAL6_R

#define USB0_RXINTERVAL6_R   (*((volatile uint8_t *)0x4005016D))

◆ USB0_RXINTERVAL7_R

#define USB0_RXINTERVAL7_R   (*((volatile uint8_t *)0x4005017D))

◆ USB0_RXIS_R

#define USB0_RXIS_R   (*((volatile uint16_t *)0x40050004))

◆ USB0_RXMAXP1_R

#define USB0_RXMAXP1_R   (*((volatile uint16_t *)0x40050114))

◆ USB0_RXMAXP2_R

#define USB0_RXMAXP2_R   (*((volatile uint16_t *)0x40050124))

◆ USB0_RXMAXP3_R

#define USB0_RXMAXP3_R   (*((volatile uint16_t *)0x40050134))

◆ USB0_RXMAXP4_R

#define USB0_RXMAXP4_R   (*((volatile uint16_t *)0x40050144))

◆ USB0_RXMAXP5_R

#define USB0_RXMAXP5_R   (*((volatile uint16_t *)0x40050154))

◆ USB0_RXMAXP6_R

#define USB0_RXMAXP6_R   (*((volatile uint16_t *)0x40050164))

◆ USB0_RXMAXP7_R

#define USB0_RXMAXP7_R   (*((volatile uint16_t *)0x40050174))

◆ USB0_RXTYPE1_R

#define USB0_RXTYPE1_R   (*((volatile uint8_t *)0x4005011C))

◆ USB0_RXTYPE2_R

#define USB0_RXTYPE2_R   (*((volatile uint8_t *)0x4005012C))

◆ USB0_RXTYPE3_R

#define USB0_RXTYPE3_R   (*((volatile uint8_t *)0x4005013C))

◆ USB0_RXTYPE4_R

#define USB0_RXTYPE4_R   (*((volatile uint8_t *)0x4005014C))

◆ USB0_RXTYPE5_R

#define USB0_RXTYPE5_R   (*((volatile uint8_t *)0x4005015C))

◆ USB0_RXTYPE6_R

#define USB0_RXTYPE6_R   (*((volatile uint8_t *)0x4005016C))

◆ USB0_RXTYPE7_R

#define USB0_RXTYPE7_R   (*((volatile uint8_t *)0x4005017C))

◆ USB0_TEST_R

#define USB0_TEST_R   (*((volatile uint8_t *)0x4005000F))

◆ USB0_TXCSRH1_R

#define USB0_TXCSRH1_R   (*((volatile uint8_t *)0x40050113))

◆ USB0_TXCSRH2_R

#define USB0_TXCSRH2_R   (*((volatile uint8_t *)0x40050123))

◆ USB0_TXCSRH3_R

#define USB0_TXCSRH3_R   (*((volatile uint8_t *)0x40050133))

◆ USB0_TXCSRH4_R

#define USB0_TXCSRH4_R   (*((volatile uint8_t *)0x40050143))

◆ USB0_TXCSRH5_R

#define USB0_TXCSRH5_R   (*((volatile uint8_t *)0x40050153))

◆ USB0_TXCSRH6_R

#define USB0_TXCSRH6_R   (*((volatile uint8_t *)0x40050163))

◆ USB0_TXCSRH7_R

#define USB0_TXCSRH7_R   (*((volatile uint8_t *)0x40050173))

◆ USB0_TXCSRL1_R

#define USB0_TXCSRL1_R   (*((volatile uint8_t *)0x40050112))

◆ USB0_TXCSRL2_R

#define USB0_TXCSRL2_R   (*((volatile uint8_t *)0x40050122))

◆ USB0_TXCSRL3_R

#define USB0_TXCSRL3_R   (*((volatile uint8_t *)0x40050132))

◆ USB0_TXCSRL4_R

#define USB0_TXCSRL4_R   (*((volatile uint8_t *)0x40050142))

◆ USB0_TXCSRL5_R

#define USB0_TXCSRL5_R   (*((volatile uint8_t *)0x40050152))

◆ USB0_TXCSRL6_R

#define USB0_TXCSRL6_R   (*((volatile uint8_t *)0x40050162))

◆ USB0_TXCSRL7_R

#define USB0_TXCSRL7_R   (*((volatile uint8_t *)0x40050172))

◆ USB0_TXDPKTBUFDIS_R

#define USB0_TXDPKTBUFDIS_R   (*((volatile uint16_t *)0x40050342))

◆ USB0_TXFIFOADD_R

#define USB0_TXFIFOADD_R   (*((volatile uint16_t *)0x40050064))

◆ USB0_TXFIFOSZ_R

#define USB0_TXFIFOSZ_R   (*((volatile uint8_t *)0x40050062))

◆ USB0_TXFUNCADDR0_R

#define USB0_TXFUNCADDR0_R   (*((volatile uint8_t *)0x40050080))

◆ USB0_TXFUNCADDR1_R

#define USB0_TXFUNCADDR1_R   (*((volatile uint8_t *)0x40050088))

◆ USB0_TXFUNCADDR2_R

#define USB0_TXFUNCADDR2_R   (*((volatile uint8_t *)0x40050090))

◆ USB0_TXFUNCADDR3_R

#define USB0_TXFUNCADDR3_R   (*((volatile uint8_t *)0x40050098))

◆ USB0_TXFUNCADDR4_R

#define USB0_TXFUNCADDR4_R   (*((volatile uint8_t *)0x400500A0))

◆ USB0_TXFUNCADDR5_R

#define USB0_TXFUNCADDR5_R   (*((volatile uint8_t *)0x400500A8))

◆ USB0_TXFUNCADDR6_R

#define USB0_TXFUNCADDR6_R   (*((volatile uint8_t *)0x400500B0))

◆ USB0_TXFUNCADDR7_R

#define USB0_TXFUNCADDR7_R   (*((volatile uint8_t *)0x400500B8))

◆ USB0_TXHUBADDR0_R

#define USB0_TXHUBADDR0_R   (*((volatile uint8_t *)0x40050082))

◆ USB0_TXHUBADDR1_R

#define USB0_TXHUBADDR1_R   (*((volatile uint8_t *)0x4005008A))

◆ USB0_TXHUBADDR2_R

#define USB0_TXHUBADDR2_R   (*((volatile uint8_t *)0x40050092))

◆ USB0_TXHUBADDR3_R

#define USB0_TXHUBADDR3_R   (*((volatile uint8_t *)0x4005009A))

◆ USB0_TXHUBADDR4_R

#define USB0_TXHUBADDR4_R   (*((volatile uint8_t *)0x400500A2))

◆ USB0_TXHUBADDR5_R

#define USB0_TXHUBADDR5_R   (*((volatile uint8_t *)0x400500AA))

◆ USB0_TXHUBADDR6_R

#define USB0_TXHUBADDR6_R   (*((volatile uint8_t *)0x400500B2))

◆ USB0_TXHUBADDR7_R

#define USB0_TXHUBADDR7_R   (*((volatile uint8_t *)0x400500BA))

◆ USB0_TXHUBPORT0_R

#define USB0_TXHUBPORT0_R   (*((volatile uint8_t *)0x40050083))

◆ USB0_TXHUBPORT1_R

#define USB0_TXHUBPORT1_R   (*((volatile uint8_t *)0x4005008B))

◆ USB0_TXHUBPORT2_R

#define USB0_TXHUBPORT2_R   (*((volatile uint8_t *)0x40050093))

◆ USB0_TXHUBPORT3_R

#define USB0_TXHUBPORT3_R   (*((volatile uint8_t *)0x4005009B))

◆ USB0_TXHUBPORT4_R

#define USB0_TXHUBPORT4_R   (*((volatile uint8_t *)0x400500A3))

◆ USB0_TXHUBPORT5_R

#define USB0_TXHUBPORT5_R   (*((volatile uint8_t *)0x400500AB))

◆ USB0_TXHUBPORT6_R

#define USB0_TXHUBPORT6_R   (*((volatile uint8_t *)0x400500B3))

◆ USB0_TXHUBPORT7_R

#define USB0_TXHUBPORT7_R   (*((volatile uint8_t *)0x400500BB))

◆ USB0_TXIE_R

#define USB0_TXIE_R   (*((volatile uint16_t *)0x40050006))

◆ USB0_TXINTERVAL1_R

#define USB0_TXINTERVAL1_R   (*((volatile uint8_t *)0x4005011B))

◆ USB0_TXINTERVAL2_R

#define USB0_TXINTERVAL2_R   (*((volatile uint8_t *)0x4005012B))

◆ USB0_TXINTERVAL3_R

#define USB0_TXINTERVAL3_R   (*((volatile uint8_t *)0x4005013B))

◆ USB0_TXINTERVAL4_R

#define USB0_TXINTERVAL4_R   (*((volatile uint8_t *)0x4005014B))

◆ USB0_TXINTERVAL5_R

#define USB0_TXINTERVAL5_R   (*((volatile uint8_t *)0x4005015B))

◆ USB0_TXINTERVAL6_R

#define USB0_TXINTERVAL6_R   (*((volatile uint8_t *)0x4005016B))

◆ USB0_TXINTERVAL7_R

#define USB0_TXINTERVAL7_R   (*((volatile uint8_t *)0x4005017B))

◆ USB0_TXIS_R

#define USB0_TXIS_R   (*((volatile uint16_t *)0x40050002))

◆ USB0_TXMAXP1_R

#define USB0_TXMAXP1_R   (*((volatile uint16_t *)0x40050110))

◆ USB0_TXMAXP2_R

#define USB0_TXMAXP2_R   (*((volatile uint16_t *)0x40050120))

◆ USB0_TXMAXP3_R

#define USB0_TXMAXP3_R   (*((volatile uint16_t *)0x40050130))

◆ USB0_TXMAXP4_R

#define USB0_TXMAXP4_R   (*((volatile uint16_t *)0x40050140))

◆ USB0_TXMAXP5_R

#define USB0_TXMAXP5_R   (*((volatile uint16_t *)0x40050150))

◆ USB0_TXMAXP6_R

#define USB0_TXMAXP6_R   (*((volatile uint16_t *)0x40050160))

◆ USB0_TXMAXP7_R

#define USB0_TXMAXP7_R   (*((volatile uint16_t *)0x40050170))

◆ USB0_TXTYPE1_R

#define USB0_TXTYPE1_R   (*((volatile uint8_t *)0x4005011A))

◆ USB0_TXTYPE2_R

#define USB0_TXTYPE2_R   (*((volatile uint8_t *)0x4005012A))

◆ USB0_TXTYPE3_R

#define USB0_TXTYPE3_R   (*((volatile uint8_t *)0x4005013A))

◆ USB0_TXTYPE4_R

#define USB0_TXTYPE4_R   (*((volatile uint8_t *)0x4005014A))

◆ USB0_TXTYPE5_R

#define USB0_TXTYPE5_R   (*((volatile uint8_t *)0x4005015A))

◆ USB0_TXTYPE6_R

#define USB0_TXTYPE6_R   (*((volatile uint8_t *)0x4005016A))

◆ USB0_TXTYPE7_R

#define USB0_TXTYPE7_R   (*((volatile uint8_t *)0x4005017A))

◆ USB0_TYPE0_R

#define USB0_TYPE0_R   (*((volatile uint8_t *)0x4005010A))

◆ USB0_VDC_R

#define USB0_VDC_R   (*((volatile u32 *)0x40050430))

◆ USB0_VDCIM_R

#define USB0_VDCIM_R   (*((volatile u32 *)0x40050438))

◆ USB0_VDCISC_R

#define USB0_VDCISC_R   (*((volatile u32 *)0x4005043C))

◆ USB0_VDCRIS_R

#define USB0_VDCRIS_R   (*((volatile u32 *)0x40050434))

◆ USB0_VPLEN_R

#define USB0_VPLEN_R   (*((volatile uint8_t *)0x4005007B))

◆ USB_CONTIM_WTCON_M

#define USB_CONTIM_WTCON_M   0x000000F0

◆ USB_CONTIM_WTCON_S

#define USB_CONTIM_WTCON_S   4

◆ USB_CONTIM_WTID_M

#define USB_CONTIM_WTID_M   0x0000000F

◆ USB_CONTIM_WTID_S

#define USB_CONTIM_WTID_S   0

◆ USB_COUNT0_COUNT_M

#define USB_COUNT0_COUNT_M   0x0000007F

◆ USB_COUNT0_COUNT_S

#define USB_COUNT0_COUNT_S   0

◆ USB_CSRH0_DT

#define USB_CSRH0_DT   0x00000002

◆ USB_CSRH0_DTWE

#define USB_CSRH0_DTWE   0x00000004

◆ USB_CSRH0_FLUSH

#define USB_CSRH0_FLUSH   0x00000001

◆ USB_CSRL0_DATAEND

#define USB_CSRL0_DATAEND   0x00000008

◆ USB_CSRL0_ERROR

#define USB_CSRL0_ERROR   0x00000010

◆ USB_CSRL0_NAKTO

#define USB_CSRL0_NAKTO   0x00000080

◆ USB_CSRL0_REQPKT

#define USB_CSRL0_REQPKT   0x00000020

◆ USB_CSRL0_RXRDY

#define USB_CSRL0_RXRDY   0x00000001

◆ USB_CSRL0_RXRDYC

#define USB_CSRL0_RXRDYC   0x00000040

◆ USB_CSRL0_SETEND

#define USB_CSRL0_SETEND   0x00000010

◆ USB_CSRL0_SETENDC

#define USB_CSRL0_SETENDC   0x00000080

◆ USB_CSRL0_SETUP

#define USB_CSRL0_SETUP   0x00000008

◆ USB_CSRL0_STALL

#define USB_CSRL0_STALL   0x00000020

◆ USB_CSRL0_STALLED

#define USB_CSRL0_STALLED   0x00000004

◆ USB_CSRL0_STATUS

#define USB_CSRL0_STATUS   0x00000040

◆ USB_CSRL0_TXRDY

#define USB_CSRL0_TXRDY   0x00000002

◆ USB_DEVCTL_DEV

#define USB_DEVCTL_DEV   0x00000080

◆ USB_DEVCTL_FSDEV

#define USB_DEVCTL_FSDEV   0x00000040

◆ USB_DEVCTL_HOST

#define USB_DEVCTL_HOST   0x00000004

◆ USB_DEVCTL_HOSTREQ

#define USB_DEVCTL_HOSTREQ   0x00000002

◆ USB_DEVCTL_LSDEV

#define USB_DEVCTL_LSDEV   0x00000020

◆ USB_DEVCTL_SESSION

#define USB_DEVCTL_SESSION   0x00000001

◆ USB_DEVCTL_VBUS_AVALID

#define USB_DEVCTL_VBUS_AVALID   0x00000010

◆ USB_DEVCTL_VBUS_M

#define USB_DEVCTL_VBUS_M   0x00000018

◆ USB_DEVCTL_VBUS_NONE

#define USB_DEVCTL_VBUS_NONE   0x00000000

◆ USB_DEVCTL_VBUS_SEND

#define USB_DEVCTL_VBUS_SEND   0x00000008

◆ USB_DEVCTL_VBUS_VALID

#define USB_DEVCTL_VBUS_VALID   0x00000018

◆ USB_DMASEL_DMAARX_M

#define USB_DMASEL_DMAARX_M   0x0000000F

◆ USB_DMASEL_DMAARX_S

#define USB_DMASEL_DMAARX_S   0

◆ USB_DMASEL_DMAATX_M

#define USB_DMASEL_DMAATX_M   0x000000F0

◆ USB_DMASEL_DMAATX_S

#define USB_DMASEL_DMAATX_S   4

◆ USB_DMASEL_DMABRX_M

#define USB_DMASEL_DMABRX_M   0x00000F00

◆ USB_DMASEL_DMABRX_S

#define USB_DMASEL_DMABRX_S   8

◆ USB_DMASEL_DMABTX_M

#define USB_DMASEL_DMABTX_M   0x0000F000

◆ USB_DMASEL_DMABTX_S

#define USB_DMASEL_DMABTX_S   12

◆ USB_DMASEL_DMACRX_M

#define USB_DMASEL_DMACRX_M   0x000F0000

◆ USB_DMASEL_DMACRX_S

#define USB_DMASEL_DMACRX_S   16

◆ USB_DMASEL_DMACTX_M

#define USB_DMASEL_DMACTX_M   0x00F00000

◆ USB_DMASEL_DMACTX_S

#define USB_DMASEL_DMACTX_S   20

◆ USB_DRIM_RESUME

#define USB_DRIM_RESUME   0x00000001

◆ USB_DRISC_RESUME

#define USB_DRISC_RESUME   0x00000001

◆ USB_DRRIS_RESUME

#define USB_DRRIS_RESUME   0x00000001

◆ USB_EPC_EPEN_HIGH

#define USB_EPC_EPEN_HIGH   0x00000001

◆ USB_EPC_EPEN_LOW

#define USB_EPC_EPEN_LOW   0x00000000

◆ USB_EPC_EPEN_M

#define USB_EPC_EPEN_M   0x00000003

◆ USB_EPC_EPEN_VBHIGH

#define USB_EPC_EPEN_VBHIGH   0x00000003

◆ USB_EPC_EPEN_VBLOW

#define USB_EPC_EPEN_VBLOW   0x00000002

◆ USB_EPC_EPENDE

#define USB_EPC_EPENDE   0x00000004

◆ USB_EPC_PFLTACT_HIGH

#define USB_EPC_PFLTACT_HIGH   0x00000300

◆ USB_EPC_PFLTACT_LOW

#define USB_EPC_PFLTACT_LOW   0x00000200

◆ USB_EPC_PFLTACT_M

#define USB_EPC_PFLTACT_M   0x00000300

◆ USB_EPC_PFLTACT_TRIS

#define USB_EPC_PFLTACT_TRIS   0x00000100

◆ USB_EPC_PFLTACT_UNCHG

#define USB_EPC_PFLTACT_UNCHG   0x00000000

◆ USB_EPC_PFLTAEN

#define USB_EPC_PFLTAEN   0x00000040

◆ USB_EPC_PFLTEN

#define USB_EPC_PFLTEN   0x00000010

◆ USB_EPC_PFLTSEN_HIGH

#define USB_EPC_PFLTSEN_HIGH   0x00000020

◆ USB_EPCIM_PF

#define USB_EPCIM_PF   0x00000001

◆ USB_EPCISC_PF

#define USB_EPCISC_PF   0x00000001

◆ USB_EPCRIS_PF

#define USB_EPCRIS_PF   0x00000001

◆ USB_EPIDX_EPIDX_M

#define USB_EPIDX_EPIDX_M   0x0000000F

◆ USB_EPIDX_EPIDX_S

#define USB_EPIDX_EPIDX_S   0

◆ USB_FADDR_M

#define USB_FADDR_M   0x0000007F

◆ USB_FADDR_S

#define USB_FADDR_S   0

◆ USB_FIFO0_EPDATA_M

#define USB_FIFO0_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO0_EPDATA_S

#define USB_FIFO0_EPDATA_S   0

◆ USB_FIFO1_EPDATA_M

#define USB_FIFO1_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO1_EPDATA_S

#define USB_FIFO1_EPDATA_S   0

◆ USB_FIFO2_EPDATA_M

#define USB_FIFO2_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO2_EPDATA_S

#define USB_FIFO2_EPDATA_S   0

◆ USB_FIFO3_EPDATA_M

#define USB_FIFO3_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO3_EPDATA_S

#define USB_FIFO3_EPDATA_S   0

◆ USB_FIFO4_EPDATA_M

#define USB_FIFO4_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO4_EPDATA_S

#define USB_FIFO4_EPDATA_S   0

◆ USB_FIFO5_EPDATA_M

#define USB_FIFO5_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO5_EPDATA_S

#define USB_FIFO5_EPDATA_S   0

◆ USB_FIFO6_EPDATA_M

#define USB_FIFO6_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO6_EPDATA_S

#define USB_FIFO6_EPDATA_S   0

◆ USB_FIFO7_EPDATA_M

#define USB_FIFO7_EPDATA_M   0xFFFFFFFF

◆ USB_FIFO7_EPDATA_S

#define USB_FIFO7_EPDATA_S   0

◆ USB_FRAME_M

#define USB_FRAME_M   0x000007FF

◆ USB_FRAME_S

#define USB_FRAME_S   0

◆ USB_FSEOF_FSEOFG_M

#define USB_FSEOF_FSEOFG_M   0x000000FF

◆ USB_FSEOF_FSEOFG_S

#define USB_FSEOF_FSEOFG_S   0

◆ USB_GPCS_DEVMOD

#define USB_GPCS_DEVMOD   0x00000001

◆ USB_GPCS_DEVMODOTG

#define USB_GPCS_DEVMODOTG   0x00000002

◆ USB_IDVIM_ID

#define USB_IDVIM_ID   0x00000001

◆ USB_IDVISC_ID

#define USB_IDVISC_ID   0x00000001

◆ USB_IDVRIS_ID

#define USB_IDVRIS_ID   0x00000001

◆ USB_IE_BABBLE

#define USB_IE_BABBLE   0x00000004

◆ USB_IE_CONN

#define USB_IE_CONN   0x00000010

◆ USB_IE_DISCON

#define USB_IE_DISCON   0x00000020

◆ USB_IE_RESET

#define USB_IE_RESET   0x00000004

◆ USB_IE_RESUME

#define USB_IE_RESUME   0x00000002

◆ USB_IE_SESREQ

#define USB_IE_SESREQ   0x00000040

◆ USB_IE_SOF

#define USB_IE_SOF   0x00000008

◆ USB_IE_SUSPND

#define USB_IE_SUSPND   0x00000001

◆ USB_IE_VBUSERR

#define USB_IE_VBUSERR   0x00000080

◆ USB_IS_BABBLE

#define USB_IS_BABBLE   0x00000004

◆ USB_IS_CONN

#define USB_IS_CONN   0x00000010

◆ USB_IS_DISCON

#define USB_IS_DISCON   0x00000020

◆ USB_IS_RESET

#define USB_IS_RESET   0x00000004

◆ USB_IS_RESUME

#define USB_IS_RESUME   0x00000002

◆ USB_IS_SESREQ

#define USB_IS_SESREQ   0x00000040

◆ USB_IS_SOF

#define USB_IS_SOF   0x00000008

◆ USB_IS_SUSPEND

#define USB_IS_SUSPEND   0x00000001

◆ USB_IS_VBUSERR

#define USB_IS_VBUSERR   0x00000080

◆ USB_LSEOF_LSEOFG_M

#define USB_LSEOF_LSEOFG_M   0x000000FF

◆ USB_LSEOF_LSEOFG_S

#define USB_LSEOF_LSEOFG_S   0

◆ USB_NAKLMT_NAKLMT_M

#define USB_NAKLMT_NAKLMT_M   0x0000001F

◆ USB_NAKLMT_NAKLMT_S

#define USB_NAKLMT_NAKLMT_S   0

◆ USB_POWER_ISOUP

#define USB_POWER_ISOUP   0x00000080

◆ USB_POWER_PWRDNPHY

#define USB_POWER_PWRDNPHY   0x00000001

◆ USB_POWER_RESET

#define USB_POWER_RESET   0x00000008

◆ USB_POWER_RESUME

#define USB_POWER_RESUME   0x00000004

◆ USB_POWER_SOFTCONN

#define USB_POWER_SOFTCONN   0x00000040

◆ USB_POWER_SUSPEND

#define USB_POWER_SUSPEND   0x00000002

◆ USB_PP_ECNT_M

#define USB_PP_ECNT_M   0x0000FF00

◆ USB_PP_ECNT_S

#define USB_PP_ECNT_S   8

◆ USB_PP_PHY

#define USB_PP_PHY   0x00000010

◆ USB_PP_TYPE_0

#define USB_PP_TYPE_0   0x00000000

◆ USB_PP_TYPE_M

#define USB_PP_TYPE_M   0x0000000F

◆ USB_PP_USB_DEVICE

#define USB_PP_USB_DEVICE   0x00000040

◆ USB_PP_USB_HOSTDEVICE

#define USB_PP_USB_HOSTDEVICE   0x00000080

◆ USB_PP_USB_M

#define USB_PP_USB_M   0x000000C0

◆ USB_PP_USB_OTG

#define USB_PP_USB_OTG   0x000000C0

◆ USB_RQPKTCOUNT1_M

#define USB_RQPKTCOUNT1_M   0x0000FFFF

◆ USB_RQPKTCOUNT1_S

#define USB_RQPKTCOUNT1_S   0

◆ USB_RQPKTCOUNT2_M

#define USB_RQPKTCOUNT2_M   0x0000FFFF

◆ USB_RQPKTCOUNT2_S

#define USB_RQPKTCOUNT2_S   0

◆ USB_RQPKTCOUNT3_M

#define USB_RQPKTCOUNT3_M   0x0000FFFF

◆ USB_RQPKTCOUNT3_S

#define USB_RQPKTCOUNT3_S   0

◆ USB_RQPKTCOUNT4_COUNT_M

#define USB_RQPKTCOUNT4_COUNT_M   0x0000FFFF

◆ USB_RQPKTCOUNT4_COUNT_S

#define USB_RQPKTCOUNT4_COUNT_S   0

◆ USB_RQPKTCOUNT5_COUNT_M

#define USB_RQPKTCOUNT5_COUNT_M   0x0000FFFF

◆ USB_RQPKTCOUNT5_COUNT_S

#define USB_RQPKTCOUNT5_COUNT_S   0

◆ USB_RQPKTCOUNT6_COUNT_M

#define USB_RQPKTCOUNT6_COUNT_M   0x0000FFFF

◆ USB_RQPKTCOUNT6_COUNT_S

#define USB_RQPKTCOUNT6_COUNT_S   0

◆ USB_RQPKTCOUNT7_COUNT_M

#define USB_RQPKTCOUNT7_COUNT_M   0x0000FFFF

◆ USB_RQPKTCOUNT7_COUNT_S

#define USB_RQPKTCOUNT7_COUNT_S   0

◆ USB_RXCOUNT1_COUNT_M

#define USB_RXCOUNT1_COUNT_M   0x00001FFF

◆ USB_RXCOUNT1_COUNT_S

#define USB_RXCOUNT1_COUNT_S   0

◆ USB_RXCOUNT2_COUNT_M

#define USB_RXCOUNT2_COUNT_M   0x00001FFF

◆ USB_RXCOUNT2_COUNT_S

#define USB_RXCOUNT2_COUNT_S   0

◆ USB_RXCOUNT3_COUNT_M

#define USB_RXCOUNT3_COUNT_M   0x00001FFF

◆ USB_RXCOUNT3_COUNT_S

#define USB_RXCOUNT3_COUNT_S   0

◆ USB_RXCOUNT4_COUNT_M

#define USB_RXCOUNT4_COUNT_M   0x00001FFF

◆ USB_RXCOUNT4_COUNT_S

#define USB_RXCOUNT4_COUNT_S   0

◆ USB_RXCOUNT5_COUNT_M

#define USB_RXCOUNT5_COUNT_M   0x00001FFF

◆ USB_RXCOUNT5_COUNT_S

#define USB_RXCOUNT5_COUNT_S   0

◆ USB_RXCOUNT6_COUNT_M

#define USB_RXCOUNT6_COUNT_M   0x00001FFF

◆ USB_RXCOUNT6_COUNT_S

#define USB_RXCOUNT6_COUNT_S   0

◆ USB_RXCOUNT7_COUNT_M

#define USB_RXCOUNT7_COUNT_M   0x00001FFF

◆ USB_RXCOUNT7_COUNT_S

#define USB_RXCOUNT7_COUNT_S   0

◆ USB_RXCSRH1_AUTOCL

#define USB_RXCSRH1_AUTOCL   0x00000080

◆ USB_RXCSRH1_AUTORQ

#define USB_RXCSRH1_AUTORQ   0x00000040

◆ USB_RXCSRH1_DISNYET

#define USB_RXCSRH1_DISNYET   0x00000010

◆ USB_RXCSRH1_DMAEN

#define USB_RXCSRH1_DMAEN   0x00000020

◆ USB_RXCSRH1_DMAMOD

#define USB_RXCSRH1_DMAMOD   0x00000008

◆ USB_RXCSRH1_DT

#define USB_RXCSRH1_DT   0x00000002

◆ USB_RXCSRH1_DTWE

#define USB_RXCSRH1_DTWE   0x00000004

◆ USB_RXCSRH1_ISO

#define USB_RXCSRH1_ISO   0x00000040

◆ USB_RXCSRH1_PIDERR

#define USB_RXCSRH1_PIDERR   0x00000010

◆ USB_RXCSRH2_AUTOCL

#define USB_RXCSRH2_AUTOCL   0x00000080

◆ USB_RXCSRH2_AUTORQ

#define USB_RXCSRH2_AUTORQ   0x00000040

◆ USB_RXCSRH2_DISNYET

#define USB_RXCSRH2_DISNYET   0x00000010

◆ USB_RXCSRH2_DMAEN

#define USB_RXCSRH2_DMAEN   0x00000020

◆ USB_RXCSRH2_DMAMOD

#define USB_RXCSRH2_DMAMOD   0x00000008

◆ USB_RXCSRH2_DT

#define USB_RXCSRH2_DT   0x00000002

◆ USB_RXCSRH2_DTWE

#define USB_RXCSRH2_DTWE   0x00000004

◆ USB_RXCSRH2_ISO

#define USB_RXCSRH2_ISO   0x00000040

◆ USB_RXCSRH2_PIDERR

#define USB_RXCSRH2_PIDERR   0x00000010

◆ USB_RXCSRH3_AUTOCL

#define USB_RXCSRH3_AUTOCL   0x00000080

◆ USB_RXCSRH3_AUTORQ

#define USB_RXCSRH3_AUTORQ   0x00000040

◆ USB_RXCSRH3_DISNYET

#define USB_RXCSRH3_DISNYET   0x00000010

◆ USB_RXCSRH3_DMAEN

#define USB_RXCSRH3_DMAEN   0x00000020

◆ USB_RXCSRH3_DMAMOD

#define USB_RXCSRH3_DMAMOD   0x00000008

◆ USB_RXCSRH3_DT

#define USB_RXCSRH3_DT   0x00000002

◆ USB_RXCSRH3_DTWE

#define USB_RXCSRH3_DTWE   0x00000004

◆ USB_RXCSRH3_ISO

#define USB_RXCSRH3_ISO   0x00000040

◆ USB_RXCSRH3_PIDERR

#define USB_RXCSRH3_PIDERR   0x00000010

◆ USB_RXCSRH4_AUTOCL

#define USB_RXCSRH4_AUTOCL   0x00000080

◆ USB_RXCSRH4_AUTORQ

#define USB_RXCSRH4_AUTORQ   0x00000040

◆ USB_RXCSRH4_DISNYET

#define USB_RXCSRH4_DISNYET   0x00000010

◆ USB_RXCSRH4_DMAEN

#define USB_RXCSRH4_DMAEN   0x00000020

◆ USB_RXCSRH4_DMAMOD

#define USB_RXCSRH4_DMAMOD   0x00000008

◆ USB_RXCSRH4_DT

#define USB_RXCSRH4_DT   0x00000002

◆ USB_RXCSRH4_DTWE

#define USB_RXCSRH4_DTWE   0x00000004

◆ USB_RXCSRH4_ISO

#define USB_RXCSRH4_ISO   0x00000040

◆ USB_RXCSRH4_PIDERR

#define USB_RXCSRH4_PIDERR   0x00000010

◆ USB_RXCSRH5_AUTOCL

#define USB_RXCSRH5_AUTOCL   0x00000080

◆ USB_RXCSRH5_AUTORQ

#define USB_RXCSRH5_AUTORQ   0x00000040

◆ USB_RXCSRH5_DISNYET

#define USB_RXCSRH5_DISNYET   0x00000010

◆ USB_RXCSRH5_DMAEN

#define USB_RXCSRH5_DMAEN   0x00000020

◆ USB_RXCSRH5_DMAMOD

#define USB_RXCSRH5_DMAMOD   0x00000008

◆ USB_RXCSRH5_DT

#define USB_RXCSRH5_DT   0x00000002

◆ USB_RXCSRH5_DTWE

#define USB_RXCSRH5_DTWE   0x00000004

◆ USB_RXCSRH5_ISO

#define USB_RXCSRH5_ISO   0x00000040

◆ USB_RXCSRH5_PIDERR

#define USB_RXCSRH5_PIDERR   0x00000010

◆ USB_RXCSRH6_AUTOCL

#define USB_RXCSRH6_AUTOCL   0x00000080

◆ USB_RXCSRH6_AUTORQ

#define USB_RXCSRH6_AUTORQ   0x00000040

◆ USB_RXCSRH6_DISNYET

#define USB_RXCSRH6_DISNYET   0x00000010

◆ USB_RXCSRH6_DMAEN

#define USB_RXCSRH6_DMAEN   0x00000020

◆ USB_RXCSRH6_DMAMOD

#define USB_RXCSRH6_DMAMOD   0x00000008

◆ USB_RXCSRH6_DT

#define USB_RXCSRH6_DT   0x00000002

◆ USB_RXCSRH6_DTWE

#define USB_RXCSRH6_DTWE   0x00000004

◆ USB_RXCSRH6_ISO

#define USB_RXCSRH6_ISO   0x00000040

◆ USB_RXCSRH6_PIDERR

#define USB_RXCSRH6_PIDERR   0x00000010

◆ USB_RXCSRH7_AUTOCL

#define USB_RXCSRH7_AUTOCL   0x00000080

◆ USB_RXCSRH7_AUTORQ

#define USB_RXCSRH7_AUTORQ   0x00000040

◆ USB_RXCSRH7_DISNYET

#define USB_RXCSRH7_DISNYET   0x00000010

◆ USB_RXCSRH7_DMAEN

#define USB_RXCSRH7_DMAEN   0x00000020

◆ USB_RXCSRH7_DMAMOD

#define USB_RXCSRH7_DMAMOD   0x00000008

◆ USB_RXCSRH7_DT

#define USB_RXCSRH7_DT   0x00000002

◆ USB_RXCSRH7_DTWE

#define USB_RXCSRH7_DTWE   0x00000004

◆ USB_RXCSRH7_ISO

#define USB_RXCSRH7_ISO   0x00000040

◆ USB_RXCSRH7_PIDERR

#define USB_RXCSRH7_PIDERR   0x00000010

◆ USB_RXCSRL1_CLRDT

#define USB_RXCSRL1_CLRDT   0x00000080

◆ USB_RXCSRL1_DATAERR

#define USB_RXCSRL1_DATAERR   0x00000008

◆ USB_RXCSRL1_ERROR

#define USB_RXCSRL1_ERROR   0x00000004

◆ USB_RXCSRL1_FLUSH

#define USB_RXCSRL1_FLUSH   0x00000010

◆ USB_RXCSRL1_FULL

#define USB_RXCSRL1_FULL   0x00000002

◆ USB_RXCSRL1_NAKTO

#define USB_RXCSRL1_NAKTO   0x00000008

◆ USB_RXCSRL1_OVER

#define USB_RXCSRL1_OVER   0x00000004

◆ USB_RXCSRL1_REQPKT

#define USB_RXCSRL1_REQPKT   0x00000020

◆ USB_RXCSRL1_RXRDY

#define USB_RXCSRL1_RXRDY   0x00000001

◆ USB_RXCSRL1_STALL

#define USB_RXCSRL1_STALL   0x00000020

◆ USB_RXCSRL1_STALLED

#define USB_RXCSRL1_STALLED   0x00000040

◆ USB_RXCSRL2_CLRDT

#define USB_RXCSRL2_CLRDT   0x00000080

◆ USB_RXCSRL2_DATAERR

#define USB_RXCSRL2_DATAERR   0x00000008

◆ USB_RXCSRL2_ERROR

#define USB_RXCSRL2_ERROR   0x00000004

◆ USB_RXCSRL2_FLUSH

#define USB_RXCSRL2_FLUSH   0x00000010

◆ USB_RXCSRL2_FULL

#define USB_RXCSRL2_FULL   0x00000002

◆ USB_RXCSRL2_NAKTO

#define USB_RXCSRL2_NAKTO   0x00000008

◆ USB_RXCSRL2_OVER

#define USB_RXCSRL2_OVER   0x00000004

◆ USB_RXCSRL2_REQPKT

#define USB_RXCSRL2_REQPKT   0x00000020

◆ USB_RXCSRL2_RXRDY

#define USB_RXCSRL2_RXRDY   0x00000001

◆ USB_RXCSRL2_STALL

#define USB_RXCSRL2_STALL   0x00000020

◆ USB_RXCSRL2_STALLED

#define USB_RXCSRL2_STALLED   0x00000040

◆ USB_RXCSRL3_CLRDT

#define USB_RXCSRL3_CLRDT   0x00000080

◆ USB_RXCSRL3_DATAERR

#define USB_RXCSRL3_DATAERR   0x00000008

◆ USB_RXCSRL3_ERROR

#define USB_RXCSRL3_ERROR   0x00000004

◆ USB_RXCSRL3_FLUSH

#define USB_RXCSRL3_FLUSH   0x00000010

◆ USB_RXCSRL3_FULL

#define USB_RXCSRL3_FULL   0x00000002

◆ USB_RXCSRL3_NAKTO

#define USB_RXCSRL3_NAKTO   0x00000008

◆ USB_RXCSRL3_OVER

#define USB_RXCSRL3_OVER   0x00000004

◆ USB_RXCSRL3_REQPKT

#define USB_RXCSRL3_REQPKT   0x00000020

◆ USB_RXCSRL3_RXRDY

#define USB_RXCSRL3_RXRDY   0x00000001

◆ USB_RXCSRL3_STALL

#define USB_RXCSRL3_STALL   0x00000020

◆ USB_RXCSRL3_STALLED

#define USB_RXCSRL3_STALLED   0x00000040

◆ USB_RXCSRL4_CLRDT

#define USB_RXCSRL4_CLRDT   0x00000080

◆ USB_RXCSRL4_DATAERR

#define USB_RXCSRL4_DATAERR   0x00000008

◆ USB_RXCSRL4_ERROR

#define USB_RXCSRL4_ERROR   0x00000004

◆ USB_RXCSRL4_FLUSH

#define USB_RXCSRL4_FLUSH   0x00000010

◆ USB_RXCSRL4_FULL

#define USB_RXCSRL4_FULL   0x00000002

◆ USB_RXCSRL4_NAKTO

#define USB_RXCSRL4_NAKTO   0x00000008

◆ USB_RXCSRL4_OVER

#define USB_RXCSRL4_OVER   0x00000004

◆ USB_RXCSRL4_REQPKT

#define USB_RXCSRL4_REQPKT   0x00000020

◆ USB_RXCSRL4_RXRDY

#define USB_RXCSRL4_RXRDY   0x00000001

◆ USB_RXCSRL4_STALL

#define USB_RXCSRL4_STALL   0x00000020

◆ USB_RXCSRL4_STALLED

#define USB_RXCSRL4_STALLED   0x00000040

◆ USB_RXCSRL5_CLRDT

#define USB_RXCSRL5_CLRDT   0x00000080

◆ USB_RXCSRL5_DATAERR

#define USB_RXCSRL5_DATAERR   0x00000008

◆ USB_RXCSRL5_ERROR

#define USB_RXCSRL5_ERROR   0x00000004

◆ USB_RXCSRL5_FLUSH

#define USB_RXCSRL5_FLUSH   0x00000010

◆ USB_RXCSRL5_FULL

#define USB_RXCSRL5_FULL   0x00000002

◆ USB_RXCSRL5_NAKTO

#define USB_RXCSRL5_NAKTO   0x00000008

◆ USB_RXCSRL5_OVER

#define USB_RXCSRL5_OVER   0x00000004

◆ USB_RXCSRL5_REQPKT

#define USB_RXCSRL5_REQPKT   0x00000020

◆ USB_RXCSRL5_RXRDY

#define USB_RXCSRL5_RXRDY   0x00000001

◆ USB_RXCSRL5_STALL

#define USB_RXCSRL5_STALL   0x00000020

◆ USB_RXCSRL5_STALLED

#define USB_RXCSRL5_STALLED   0x00000040

◆ USB_RXCSRL6_CLRDT

#define USB_RXCSRL6_CLRDT   0x00000080

◆ USB_RXCSRL6_DATAERR

#define USB_RXCSRL6_DATAERR   0x00000008

◆ USB_RXCSRL6_ERROR

#define USB_RXCSRL6_ERROR   0x00000004

◆ USB_RXCSRL6_FLUSH

#define USB_RXCSRL6_FLUSH   0x00000010

◆ USB_RXCSRL6_FULL

#define USB_RXCSRL6_FULL   0x00000002

◆ USB_RXCSRL6_NAKTO

#define USB_RXCSRL6_NAKTO   0x00000008

◆ USB_RXCSRL6_OVER

#define USB_RXCSRL6_OVER   0x00000004

◆ USB_RXCSRL6_REQPKT

#define USB_RXCSRL6_REQPKT   0x00000020

◆ USB_RXCSRL6_RXRDY

#define USB_RXCSRL6_RXRDY   0x00000001

◆ USB_RXCSRL6_STALL

#define USB_RXCSRL6_STALL   0x00000020

◆ USB_RXCSRL6_STALLED

#define USB_RXCSRL6_STALLED   0x00000040

◆ USB_RXCSRL7_CLRDT

#define USB_RXCSRL7_CLRDT   0x00000080

◆ USB_RXCSRL7_DATAERR

#define USB_RXCSRL7_DATAERR   0x00000008

◆ USB_RXCSRL7_ERROR

#define USB_RXCSRL7_ERROR   0x00000004

◆ USB_RXCSRL7_FLUSH

#define USB_RXCSRL7_FLUSH   0x00000010

◆ USB_RXCSRL7_FULL

#define USB_RXCSRL7_FULL   0x00000002

◆ USB_RXCSRL7_NAKTO

#define USB_RXCSRL7_NAKTO   0x00000008

◆ USB_RXCSRL7_OVER

#define USB_RXCSRL7_OVER   0x00000004

◆ USB_RXCSRL7_REQPKT

#define USB_RXCSRL7_REQPKT   0x00000020

◆ USB_RXCSRL7_RXRDY

#define USB_RXCSRL7_RXRDY   0x00000001

◆ USB_RXCSRL7_STALL

#define USB_RXCSRL7_STALL   0x00000020

◆ USB_RXCSRL7_STALLED

#define USB_RXCSRL7_STALLED   0x00000040

◆ USB_RXDPKTBUFDIS_EP1

#define USB_RXDPKTBUFDIS_EP1   0x00000002

◆ USB_RXDPKTBUFDIS_EP2

#define USB_RXDPKTBUFDIS_EP2   0x00000004

◆ USB_RXDPKTBUFDIS_EP3

#define USB_RXDPKTBUFDIS_EP3   0x00000008

◆ USB_RXDPKTBUFDIS_EP4

#define USB_RXDPKTBUFDIS_EP4   0x00000010

◆ USB_RXDPKTBUFDIS_EP5

#define USB_RXDPKTBUFDIS_EP5   0x00000020

◆ USB_RXDPKTBUFDIS_EP6

#define USB_RXDPKTBUFDIS_EP6   0x00000040

◆ USB_RXDPKTBUFDIS_EP7

#define USB_RXDPKTBUFDIS_EP7   0x00000080

◆ USB_RXFIFOADD_ADDR_M

#define USB_RXFIFOADD_ADDR_M   0x000001FF

◆ USB_RXFIFOADD_ADDR_S

#define USB_RXFIFOADD_ADDR_S   0

◆ USB_RXFIFOSZ_DPB

#define USB_RXFIFOSZ_DPB   0x00000010

◆ USB_RXFIFOSZ_SIZE_1024

#define USB_RXFIFOSZ_SIZE_1024   0x00000007

◆ USB_RXFIFOSZ_SIZE_128

#define USB_RXFIFOSZ_SIZE_128   0x00000004

◆ USB_RXFIFOSZ_SIZE_16

#define USB_RXFIFOSZ_SIZE_16   0x00000001

◆ USB_RXFIFOSZ_SIZE_2048

#define USB_RXFIFOSZ_SIZE_2048   0x00000008

◆ USB_RXFIFOSZ_SIZE_256

#define USB_RXFIFOSZ_SIZE_256   0x00000005

◆ USB_RXFIFOSZ_SIZE_32

#define USB_RXFIFOSZ_SIZE_32   0x00000002

◆ USB_RXFIFOSZ_SIZE_512

#define USB_RXFIFOSZ_SIZE_512   0x00000006

◆ USB_RXFIFOSZ_SIZE_64

#define USB_RXFIFOSZ_SIZE_64   0x00000003

◆ USB_RXFIFOSZ_SIZE_8

#define USB_RXFIFOSZ_SIZE_8   0x00000000

◆ USB_RXFIFOSZ_SIZE_M

#define USB_RXFIFOSZ_SIZE_M   0x0000000F

◆ USB_RXFUNCADDR1_ADDR_M

#define USB_RXFUNCADDR1_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR1_ADDR_S

#define USB_RXFUNCADDR1_ADDR_S   0

◆ USB_RXFUNCADDR2_ADDR_M

#define USB_RXFUNCADDR2_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR2_ADDR_S

#define USB_RXFUNCADDR2_ADDR_S   0

◆ USB_RXFUNCADDR3_ADDR_M

#define USB_RXFUNCADDR3_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR3_ADDR_S

#define USB_RXFUNCADDR3_ADDR_S   0

◆ USB_RXFUNCADDR4_ADDR_M

#define USB_RXFUNCADDR4_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR4_ADDR_S

#define USB_RXFUNCADDR4_ADDR_S   0

◆ USB_RXFUNCADDR5_ADDR_M

#define USB_RXFUNCADDR5_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR5_ADDR_S

#define USB_RXFUNCADDR5_ADDR_S   0

◆ USB_RXFUNCADDR6_ADDR_M

#define USB_RXFUNCADDR6_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR6_ADDR_S

#define USB_RXFUNCADDR6_ADDR_S   0

◆ USB_RXFUNCADDR7_ADDR_M

#define USB_RXFUNCADDR7_ADDR_M   0x0000007F

◆ USB_RXFUNCADDR7_ADDR_S

#define USB_RXFUNCADDR7_ADDR_S   0

◆ USB_RXHUBADDR1_ADDR_M

#define USB_RXHUBADDR1_ADDR_M   0x0000007F

◆ USB_RXHUBADDR1_ADDR_S

#define USB_RXHUBADDR1_ADDR_S   0

◆ USB_RXHUBADDR2_ADDR_M

#define USB_RXHUBADDR2_ADDR_M   0x0000007F

◆ USB_RXHUBADDR2_ADDR_S

#define USB_RXHUBADDR2_ADDR_S   0

◆ USB_RXHUBADDR3_ADDR_M

#define USB_RXHUBADDR3_ADDR_M   0x0000007F

◆ USB_RXHUBADDR3_ADDR_S

#define USB_RXHUBADDR3_ADDR_S   0

◆ USB_RXHUBADDR4_ADDR_M

#define USB_RXHUBADDR4_ADDR_M   0x0000007F

◆ USB_RXHUBADDR4_ADDR_S

#define USB_RXHUBADDR4_ADDR_S   0

◆ USB_RXHUBADDR5_ADDR_M

#define USB_RXHUBADDR5_ADDR_M   0x0000007F

◆ USB_RXHUBADDR5_ADDR_S

#define USB_RXHUBADDR5_ADDR_S   0

◆ USB_RXHUBADDR6_ADDR_M

#define USB_RXHUBADDR6_ADDR_M   0x0000007F

◆ USB_RXHUBADDR6_ADDR_S

#define USB_RXHUBADDR6_ADDR_S   0

◆ USB_RXHUBADDR7_ADDR_M

#define USB_RXHUBADDR7_ADDR_M   0x0000007F

◆ USB_RXHUBADDR7_ADDR_S

#define USB_RXHUBADDR7_ADDR_S   0

◆ USB_RXHUBPORT1_PORT_M

#define USB_RXHUBPORT1_PORT_M   0x0000007F

◆ USB_RXHUBPORT1_PORT_S

#define USB_RXHUBPORT1_PORT_S   0

◆ USB_RXHUBPORT2_PORT_M

#define USB_RXHUBPORT2_PORT_M   0x0000007F

◆ USB_RXHUBPORT2_PORT_S

#define USB_RXHUBPORT2_PORT_S   0

◆ USB_RXHUBPORT3_PORT_M

#define USB_RXHUBPORT3_PORT_M   0x0000007F

◆ USB_RXHUBPORT3_PORT_S

#define USB_RXHUBPORT3_PORT_S   0

◆ USB_RXHUBPORT4_PORT_M

#define USB_RXHUBPORT4_PORT_M   0x0000007F

◆ USB_RXHUBPORT4_PORT_S

#define USB_RXHUBPORT4_PORT_S   0

◆ USB_RXHUBPORT5_PORT_M

#define USB_RXHUBPORT5_PORT_M   0x0000007F

◆ USB_RXHUBPORT5_PORT_S

#define USB_RXHUBPORT5_PORT_S   0

◆ USB_RXHUBPORT6_PORT_M

#define USB_RXHUBPORT6_PORT_M   0x0000007F

◆ USB_RXHUBPORT6_PORT_S

#define USB_RXHUBPORT6_PORT_S   0

◆ USB_RXHUBPORT7_PORT_M

#define USB_RXHUBPORT7_PORT_M   0x0000007F

◆ USB_RXHUBPORT7_PORT_S

#define USB_RXHUBPORT7_PORT_S   0

◆ USB_RXIE_EP1

#define USB_RXIE_EP1   0x00000002

◆ USB_RXIE_EP2

#define USB_RXIE_EP2   0x00000004

◆ USB_RXIE_EP3

#define USB_RXIE_EP3   0x00000008

◆ USB_RXIE_EP4

#define USB_RXIE_EP4   0x00000010

◆ USB_RXIE_EP5

#define USB_RXIE_EP5   0x00000020

◆ USB_RXIE_EP6

#define USB_RXIE_EP6   0x00000040

◆ USB_RXIE_EP7

#define USB_RXIE_EP7   0x00000080

◆ USB_RXINTERVAL1_NAKLMT_M

#define USB_RXINTERVAL1_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL1_NAKLMT_S

#define USB_RXINTERVAL1_NAKLMT_S    0

◆ USB_RXINTERVAL1_TXPOLL_M

#define USB_RXINTERVAL1_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL1_TXPOLL_S

#define USB_RXINTERVAL1_TXPOLL_S    0

◆ USB_RXINTERVAL2_NAKLMT_M

#define USB_RXINTERVAL2_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL2_NAKLMT_S

#define USB_RXINTERVAL2_NAKLMT_S    0

◆ USB_RXINTERVAL2_TXPOLL_M

#define USB_RXINTERVAL2_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL2_TXPOLL_S

#define USB_RXINTERVAL2_TXPOLL_S    0

◆ USB_RXINTERVAL3_NAKLMT_M

#define USB_RXINTERVAL3_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL3_NAKLMT_S

#define USB_RXINTERVAL3_NAKLMT_S    0

◆ USB_RXINTERVAL3_TXPOLL_M

#define USB_RXINTERVAL3_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL3_TXPOLL_S

#define USB_RXINTERVAL3_TXPOLL_S    0

◆ USB_RXINTERVAL4_NAKLMT_M

#define USB_RXINTERVAL4_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL4_NAKLMT_S

#define USB_RXINTERVAL4_NAKLMT_S    0

◆ USB_RXINTERVAL4_TXPOLL_M

#define USB_RXINTERVAL4_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL4_TXPOLL_S

#define USB_RXINTERVAL4_TXPOLL_S    0

◆ USB_RXINTERVAL5_NAKLMT_M

#define USB_RXINTERVAL5_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL5_NAKLMT_S

#define USB_RXINTERVAL5_NAKLMT_S    0

◆ USB_RXINTERVAL5_TXPOLL_M

#define USB_RXINTERVAL5_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL5_TXPOLL_S

#define USB_RXINTERVAL5_TXPOLL_S    0

◆ USB_RXINTERVAL6_NAKLMT_M

#define USB_RXINTERVAL6_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL6_NAKLMT_S

#define USB_RXINTERVAL6_NAKLMT_S    0

◆ USB_RXINTERVAL6_TXPOLL_M

#define USB_RXINTERVAL6_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL6_TXPOLL_S

#define USB_RXINTERVAL6_TXPOLL_S    0

◆ USB_RXINTERVAL7_NAKLMT_M

#define USB_RXINTERVAL7_NAKLMT_M    0x000000FF

◆ USB_RXINTERVAL7_NAKLMT_S

#define USB_RXINTERVAL7_NAKLMT_S    0

◆ USB_RXINTERVAL7_TXPOLL_M

#define USB_RXINTERVAL7_TXPOLL_M    0x000000FF

◆ USB_RXINTERVAL7_TXPOLL_S

#define USB_RXINTERVAL7_TXPOLL_S    0

◆ USB_RXIS_EP1

#define USB_RXIS_EP1   0x00000002

◆ USB_RXIS_EP2

#define USB_RXIS_EP2   0x00000004

◆ USB_RXIS_EP3

#define USB_RXIS_EP3   0x00000008

◆ USB_RXIS_EP4

#define USB_RXIS_EP4   0x00000010

◆ USB_RXIS_EP5

#define USB_RXIS_EP5   0x00000020

◆ USB_RXIS_EP6

#define USB_RXIS_EP6   0x00000040

◆ USB_RXIS_EP7

#define USB_RXIS_EP7   0x00000080

◆ USB_RXMAXP1_MAXLOAD_M

#define USB_RXMAXP1_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP1_MAXLOAD_S

#define USB_RXMAXP1_MAXLOAD_S   0

◆ USB_RXMAXP2_MAXLOAD_M

#define USB_RXMAXP2_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP2_MAXLOAD_S

#define USB_RXMAXP2_MAXLOAD_S   0

◆ USB_RXMAXP3_MAXLOAD_M

#define USB_RXMAXP3_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP3_MAXLOAD_S

#define USB_RXMAXP3_MAXLOAD_S   0

◆ USB_RXMAXP4_MAXLOAD_M

#define USB_RXMAXP4_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP4_MAXLOAD_S

#define USB_RXMAXP4_MAXLOAD_S   0

◆ USB_RXMAXP5_MAXLOAD_M

#define USB_RXMAXP5_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP5_MAXLOAD_S

#define USB_RXMAXP5_MAXLOAD_S   0

◆ USB_RXMAXP6_MAXLOAD_M

#define USB_RXMAXP6_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP6_MAXLOAD_S

#define USB_RXMAXP6_MAXLOAD_S   0

◆ USB_RXMAXP7_MAXLOAD_M

#define USB_RXMAXP7_MAXLOAD_M   0x000007FF

◆ USB_RXMAXP7_MAXLOAD_S

#define USB_RXMAXP7_MAXLOAD_S   0

◆ USB_RXTYPE1_PROTO_BULK

#define USB_RXTYPE1_PROTO_BULK   0x00000020

◆ USB_RXTYPE1_PROTO_CTRL

#define USB_RXTYPE1_PROTO_CTRL   0x00000000

◆ USB_RXTYPE1_PROTO_INT

#define USB_RXTYPE1_PROTO_INT   0x00000030

◆ USB_RXTYPE1_PROTO_ISOC

#define USB_RXTYPE1_PROTO_ISOC   0x00000010

◆ USB_RXTYPE1_PROTO_M

#define USB_RXTYPE1_PROTO_M   0x00000030

◆ USB_RXTYPE1_SPEED_DFLT

#define USB_RXTYPE1_SPEED_DFLT   0x00000000

◆ USB_RXTYPE1_SPEED_FULL

#define USB_RXTYPE1_SPEED_FULL   0x00000080

◆ USB_RXTYPE1_SPEED_LOW

#define USB_RXTYPE1_SPEED_LOW   0x000000C0

◆ USB_RXTYPE1_SPEED_M

#define USB_RXTYPE1_SPEED_M   0x000000C0

◆ USB_RXTYPE1_TEP_M

#define USB_RXTYPE1_TEP_M   0x0000000F

◆ USB_RXTYPE1_TEP_S

#define USB_RXTYPE1_TEP_S   0

◆ USB_RXTYPE2_PROTO_BULK

#define USB_RXTYPE2_PROTO_BULK   0x00000020

◆ USB_RXTYPE2_PROTO_CTRL

#define USB_RXTYPE2_PROTO_CTRL   0x00000000

◆ USB_RXTYPE2_PROTO_INT

#define USB_RXTYPE2_PROTO_INT   0x00000030

◆ USB_RXTYPE2_PROTO_ISOC

#define USB_RXTYPE2_PROTO_ISOC   0x00000010

◆ USB_RXTYPE2_PROTO_M

#define USB_RXTYPE2_PROTO_M   0x00000030

◆ USB_RXTYPE2_SPEED_DFLT

#define USB_RXTYPE2_SPEED_DFLT   0x00000000

◆ USB_RXTYPE2_SPEED_FULL

#define USB_RXTYPE2_SPEED_FULL   0x00000080

◆ USB_RXTYPE2_SPEED_LOW

#define USB_RXTYPE2_SPEED_LOW   0x000000C0

◆ USB_RXTYPE2_SPEED_M

#define USB_RXTYPE2_SPEED_M   0x000000C0

◆ USB_RXTYPE2_TEP_M

#define USB_RXTYPE2_TEP_M   0x0000000F

◆ USB_RXTYPE2_TEP_S

#define USB_RXTYPE2_TEP_S   0

◆ USB_RXTYPE3_PROTO_BULK

#define USB_RXTYPE3_PROTO_BULK   0x00000020

◆ USB_RXTYPE3_PROTO_CTRL

#define USB_RXTYPE3_PROTO_CTRL   0x00000000

◆ USB_RXTYPE3_PROTO_INT

#define USB_RXTYPE3_PROTO_INT   0x00000030

◆ USB_RXTYPE3_PROTO_ISOC

#define USB_RXTYPE3_PROTO_ISOC   0x00000010

◆ USB_RXTYPE3_PROTO_M

#define USB_RXTYPE3_PROTO_M   0x00000030

◆ USB_RXTYPE3_SPEED_DFLT

#define USB_RXTYPE3_SPEED_DFLT   0x00000000

◆ USB_RXTYPE3_SPEED_FULL

#define USB_RXTYPE3_SPEED_FULL   0x00000080

◆ USB_RXTYPE3_SPEED_LOW

#define USB_RXTYPE3_SPEED_LOW   0x000000C0

◆ USB_RXTYPE3_SPEED_M

#define USB_RXTYPE3_SPEED_M   0x000000C0

◆ USB_RXTYPE3_TEP_M

#define USB_RXTYPE3_TEP_M   0x0000000F

◆ USB_RXTYPE3_TEP_S

#define USB_RXTYPE3_TEP_S   0

◆ USB_RXTYPE4_PROTO_BULK

#define USB_RXTYPE4_PROTO_BULK   0x00000020

◆ USB_RXTYPE4_PROTO_CTRL

#define USB_RXTYPE4_PROTO_CTRL   0x00000000

◆ USB_RXTYPE4_PROTO_INT

#define USB_RXTYPE4_PROTO_INT   0x00000030

◆ USB_RXTYPE4_PROTO_ISOC

#define USB_RXTYPE4_PROTO_ISOC   0x00000010

◆ USB_RXTYPE4_PROTO_M

#define USB_RXTYPE4_PROTO_M   0x00000030

◆ USB_RXTYPE4_SPEED_DFLT

#define USB_RXTYPE4_SPEED_DFLT   0x00000000

◆ USB_RXTYPE4_SPEED_FULL

#define USB_RXTYPE4_SPEED_FULL   0x00000080

◆ USB_RXTYPE4_SPEED_LOW

#define USB_RXTYPE4_SPEED_LOW   0x000000C0

◆ USB_RXTYPE4_SPEED_M

#define USB_RXTYPE4_SPEED_M   0x000000C0

◆ USB_RXTYPE4_TEP_M

#define USB_RXTYPE4_TEP_M   0x0000000F

◆ USB_RXTYPE4_TEP_S

#define USB_RXTYPE4_TEP_S   0

◆ USB_RXTYPE5_PROTO_BULK

#define USB_RXTYPE5_PROTO_BULK   0x00000020

◆ USB_RXTYPE5_PROTO_CTRL

#define USB_RXTYPE5_PROTO_CTRL   0x00000000

◆ USB_RXTYPE5_PROTO_INT

#define USB_RXTYPE5_PROTO_INT   0x00000030

◆ USB_RXTYPE5_PROTO_ISOC

#define USB_RXTYPE5_PROTO_ISOC   0x00000010

◆ USB_RXTYPE5_PROTO_M

#define USB_RXTYPE5_PROTO_M   0x00000030

◆ USB_RXTYPE5_SPEED_DFLT

#define USB_RXTYPE5_SPEED_DFLT   0x00000000

◆ USB_RXTYPE5_SPEED_FULL

#define USB_RXTYPE5_SPEED_FULL   0x00000080

◆ USB_RXTYPE5_SPEED_LOW

#define USB_RXTYPE5_SPEED_LOW   0x000000C0

◆ USB_RXTYPE5_SPEED_M

#define USB_RXTYPE5_SPEED_M   0x000000C0

◆ USB_RXTYPE5_TEP_M

#define USB_RXTYPE5_TEP_M   0x0000000F

◆ USB_RXTYPE5_TEP_S

#define USB_RXTYPE5_TEP_S   0

◆ USB_RXTYPE6_PROTO_BULK

#define USB_RXTYPE6_PROTO_BULK   0x00000020

◆ USB_RXTYPE6_PROTO_CTRL

#define USB_RXTYPE6_PROTO_CTRL   0x00000000

◆ USB_RXTYPE6_PROTO_INT

#define USB_RXTYPE6_PROTO_INT   0x00000030

◆ USB_RXTYPE6_PROTO_ISOC

#define USB_RXTYPE6_PROTO_ISOC   0x00000010

◆ USB_RXTYPE6_PROTO_M

#define USB_RXTYPE6_PROTO_M   0x00000030

◆ USB_RXTYPE6_SPEED_DFLT

#define USB_RXTYPE6_SPEED_DFLT   0x00000000

◆ USB_RXTYPE6_SPEED_FULL

#define USB_RXTYPE6_SPEED_FULL   0x00000080

◆ USB_RXTYPE6_SPEED_LOW

#define USB_RXTYPE6_SPEED_LOW   0x000000C0

◆ USB_RXTYPE6_SPEED_M

#define USB_RXTYPE6_SPEED_M   0x000000C0

◆ USB_RXTYPE6_TEP_M

#define USB_RXTYPE6_TEP_M   0x0000000F

◆ USB_RXTYPE6_TEP_S

#define USB_RXTYPE6_TEP_S   0

◆ USB_RXTYPE7_PROTO_BULK

#define USB_RXTYPE7_PROTO_BULK   0x00000020

◆ USB_RXTYPE7_PROTO_CTRL

#define USB_RXTYPE7_PROTO_CTRL   0x00000000

◆ USB_RXTYPE7_PROTO_INT

#define USB_RXTYPE7_PROTO_INT   0x00000030

◆ USB_RXTYPE7_PROTO_ISOC

#define USB_RXTYPE7_PROTO_ISOC   0x00000010

◆ USB_RXTYPE7_PROTO_M

#define USB_RXTYPE7_PROTO_M   0x00000030

◆ USB_RXTYPE7_SPEED_DFLT

#define USB_RXTYPE7_SPEED_DFLT   0x00000000

◆ USB_RXTYPE7_SPEED_FULL

#define USB_RXTYPE7_SPEED_FULL   0x00000080

◆ USB_RXTYPE7_SPEED_LOW

#define USB_RXTYPE7_SPEED_LOW   0x000000C0

◆ USB_RXTYPE7_SPEED_M

#define USB_RXTYPE7_SPEED_M   0x000000C0

◆ USB_RXTYPE7_TEP_M

#define USB_RXTYPE7_TEP_M   0x0000000F

◆ USB_RXTYPE7_TEP_S

#define USB_RXTYPE7_TEP_S   0

◆ USB_TEST_FIFOACC

#define USB_TEST_FIFOACC   0x00000040

◆ USB_TEST_FORCEFS

#define USB_TEST_FORCEFS   0x00000020

◆ USB_TEST_FORCEH

#define USB_TEST_FORCEH   0x00000080

◆ USB_TXCSRH1_AUTOSET

#define USB_TXCSRH1_AUTOSET   0x00000080

◆ USB_TXCSRH1_DMAEN

#define USB_TXCSRH1_DMAEN   0x00000010

◆ USB_TXCSRH1_DMAMOD

#define USB_TXCSRH1_DMAMOD   0x00000004

◆ USB_TXCSRH1_DT

#define USB_TXCSRH1_DT   0x00000001

◆ USB_TXCSRH1_DTWE

#define USB_TXCSRH1_DTWE   0x00000002

◆ USB_TXCSRH1_FDT

#define USB_TXCSRH1_FDT   0x00000008

◆ USB_TXCSRH1_ISO

#define USB_TXCSRH1_ISO   0x00000040

◆ USB_TXCSRH1_MODE

#define USB_TXCSRH1_MODE   0x00000020

◆ USB_TXCSRH2_AUTOSET

#define USB_TXCSRH2_AUTOSET   0x00000080

◆ USB_TXCSRH2_DMAEN

#define USB_TXCSRH2_DMAEN   0x00000010

◆ USB_TXCSRH2_DMAMOD

#define USB_TXCSRH2_DMAMOD   0x00000004

◆ USB_TXCSRH2_DT

#define USB_TXCSRH2_DT   0x00000001

◆ USB_TXCSRH2_DTWE

#define USB_TXCSRH2_DTWE   0x00000002

◆ USB_TXCSRH2_FDT

#define USB_TXCSRH2_FDT   0x00000008

◆ USB_TXCSRH2_ISO

#define USB_TXCSRH2_ISO   0x00000040

◆ USB_TXCSRH2_MODE

#define USB_TXCSRH2_MODE   0x00000020

◆ USB_TXCSRH3_AUTOSET

#define USB_TXCSRH3_AUTOSET   0x00000080

◆ USB_TXCSRH3_DMAEN

#define USB_TXCSRH3_DMAEN   0x00000010

◆ USB_TXCSRH3_DMAMOD

#define USB_TXCSRH3_DMAMOD   0x00000004

◆ USB_TXCSRH3_DT

#define USB_TXCSRH3_DT   0x00000001

◆ USB_TXCSRH3_DTWE

#define USB_TXCSRH3_DTWE   0x00000002

◆ USB_TXCSRH3_FDT

#define USB_TXCSRH3_FDT   0x00000008

◆ USB_TXCSRH3_ISO

#define USB_TXCSRH3_ISO   0x00000040

◆ USB_TXCSRH3_MODE

#define USB_TXCSRH3_MODE   0x00000020

◆ USB_TXCSRH4_AUTOSET

#define USB_TXCSRH4_AUTOSET   0x00000080

◆ USB_TXCSRH4_DMAEN

#define USB_TXCSRH4_DMAEN   0x00000010

◆ USB_TXCSRH4_DMAMOD

#define USB_TXCSRH4_DMAMOD   0x00000004

◆ USB_TXCSRH4_DT

#define USB_TXCSRH4_DT   0x00000001

◆ USB_TXCSRH4_DTWE

#define USB_TXCSRH4_DTWE   0x00000002

◆ USB_TXCSRH4_FDT

#define USB_TXCSRH4_FDT   0x00000008

◆ USB_TXCSRH4_ISO

#define USB_TXCSRH4_ISO   0x00000040

◆ USB_TXCSRH4_MODE

#define USB_TXCSRH4_MODE   0x00000020

◆ USB_TXCSRH5_AUTOSET

#define USB_TXCSRH5_AUTOSET   0x00000080

◆ USB_TXCSRH5_DMAEN

#define USB_TXCSRH5_DMAEN   0x00000010

◆ USB_TXCSRH5_DMAMOD

#define USB_TXCSRH5_DMAMOD   0x00000004

◆ USB_TXCSRH5_DT

#define USB_TXCSRH5_DT   0x00000001

◆ USB_TXCSRH5_DTWE

#define USB_TXCSRH5_DTWE   0x00000002

◆ USB_TXCSRH5_FDT

#define USB_TXCSRH5_FDT   0x00000008

◆ USB_TXCSRH5_ISO

#define USB_TXCSRH5_ISO   0x00000040

◆ USB_TXCSRH5_MODE

#define USB_TXCSRH5_MODE   0x00000020

◆ USB_TXCSRH6_AUTOSET

#define USB_TXCSRH6_AUTOSET   0x00000080

◆ USB_TXCSRH6_DMAEN

#define USB_TXCSRH6_DMAEN   0x00000010

◆ USB_TXCSRH6_DMAMOD

#define USB_TXCSRH6_DMAMOD   0x00000004

◆ USB_TXCSRH6_DT

#define USB_TXCSRH6_DT   0x00000001

◆ USB_TXCSRH6_DTWE

#define USB_TXCSRH6_DTWE   0x00000002

◆ USB_TXCSRH6_FDT

#define USB_TXCSRH6_FDT   0x00000008

◆ USB_TXCSRH6_ISO

#define USB_TXCSRH6_ISO   0x00000040

◆ USB_TXCSRH6_MODE

#define USB_TXCSRH6_MODE   0x00000020

◆ USB_TXCSRH7_AUTOSET

#define USB_TXCSRH7_AUTOSET   0x00000080

◆ USB_TXCSRH7_DMAEN

#define USB_TXCSRH7_DMAEN   0x00000010

◆ USB_TXCSRH7_DMAMOD

#define USB_TXCSRH7_DMAMOD   0x00000004

◆ USB_TXCSRH7_DT

#define USB_TXCSRH7_DT   0x00000001

◆ USB_TXCSRH7_DTWE

#define USB_TXCSRH7_DTWE   0x00000002

◆ USB_TXCSRH7_FDT

#define USB_TXCSRH7_FDT   0x00000008

◆ USB_TXCSRH7_ISO

#define USB_TXCSRH7_ISO   0x00000040

◆ USB_TXCSRH7_MODE

#define USB_TXCSRH7_MODE   0x00000020

◆ USB_TXCSRL1_CLRDT

#define USB_TXCSRL1_CLRDT   0x00000040

◆ USB_TXCSRL1_ERROR

#define USB_TXCSRL1_ERROR   0x00000004

◆ USB_TXCSRL1_FIFONE

#define USB_TXCSRL1_FIFONE   0x00000002

◆ USB_TXCSRL1_FLUSH

#define USB_TXCSRL1_FLUSH   0x00000008

◆ USB_TXCSRL1_NAKTO

#define USB_TXCSRL1_NAKTO   0x00000080

◆ USB_TXCSRL1_SETUP

#define USB_TXCSRL1_SETUP   0x00000010

◆ USB_TXCSRL1_STALL

#define USB_TXCSRL1_STALL   0x00000010

◆ USB_TXCSRL1_STALLED

#define USB_TXCSRL1_STALLED   0x00000020

◆ USB_TXCSRL1_TXRDY

#define USB_TXCSRL1_TXRDY   0x00000001

◆ USB_TXCSRL1_UNDRN

#define USB_TXCSRL1_UNDRN   0x00000004

◆ USB_TXCSRL2_CLRDT

#define USB_TXCSRL2_CLRDT   0x00000040

◆ USB_TXCSRL2_ERROR

#define USB_TXCSRL2_ERROR   0x00000004

◆ USB_TXCSRL2_FIFONE

#define USB_TXCSRL2_FIFONE   0x00000002

◆ USB_TXCSRL2_FLUSH

#define USB_TXCSRL2_FLUSH   0x00000008

◆ USB_TXCSRL2_NAKTO

#define USB_TXCSRL2_NAKTO   0x00000080

◆ USB_TXCSRL2_SETUP

#define USB_TXCSRL2_SETUP   0x00000010

◆ USB_TXCSRL2_STALL

#define USB_TXCSRL2_STALL   0x00000010

◆ USB_TXCSRL2_STALLED

#define USB_TXCSRL2_STALLED   0x00000020

◆ USB_TXCSRL2_TXRDY

#define USB_TXCSRL2_TXRDY   0x00000001

◆ USB_TXCSRL2_UNDRN

#define USB_TXCSRL2_UNDRN   0x00000004

◆ USB_TXCSRL3_CLRDT

#define USB_TXCSRL3_CLRDT   0x00000040

◆ USB_TXCSRL3_ERROR

#define USB_TXCSRL3_ERROR   0x00000004

◆ USB_TXCSRL3_FIFONE

#define USB_TXCSRL3_FIFONE   0x00000002

◆ USB_TXCSRL3_FLUSH

#define USB_TXCSRL3_FLUSH   0x00000008

◆ USB_TXCSRL3_NAKTO

#define USB_TXCSRL3_NAKTO   0x00000080

◆ USB_TXCSRL3_SETUP

#define USB_TXCSRL3_SETUP   0x00000010

◆ USB_TXCSRL3_STALL

#define USB_TXCSRL3_STALL   0x00000010

◆ USB_TXCSRL3_STALLED

#define USB_TXCSRL3_STALLED   0x00000020

◆ USB_TXCSRL3_TXRDY

#define USB_TXCSRL3_TXRDY   0x00000001

◆ USB_TXCSRL3_UNDRN

#define USB_TXCSRL3_UNDRN   0x00000004

◆ USB_TXCSRL4_CLRDT

#define USB_TXCSRL4_CLRDT   0x00000040

◆ USB_TXCSRL4_ERROR

#define USB_TXCSRL4_ERROR   0x00000004

◆ USB_TXCSRL4_FIFONE

#define USB_TXCSRL4_FIFONE   0x00000002

◆ USB_TXCSRL4_FLUSH

#define USB_TXCSRL4_FLUSH   0x00000008

◆ USB_TXCSRL4_NAKTO

#define USB_TXCSRL4_NAKTO   0x00000080

◆ USB_TXCSRL4_SETUP

#define USB_TXCSRL4_SETUP   0x00000010

◆ USB_TXCSRL4_STALL

#define USB_TXCSRL4_STALL   0x00000010

◆ USB_TXCSRL4_STALLED

#define USB_TXCSRL4_STALLED   0x00000020

◆ USB_TXCSRL4_TXRDY

#define USB_TXCSRL4_TXRDY   0x00000001

◆ USB_TXCSRL4_UNDRN

#define USB_TXCSRL4_UNDRN   0x00000004

◆ USB_TXCSRL5_CLRDT

#define USB_TXCSRL5_CLRDT   0x00000040

◆ USB_TXCSRL5_ERROR

#define USB_TXCSRL5_ERROR   0x00000004

◆ USB_TXCSRL5_FIFONE

#define USB_TXCSRL5_FIFONE   0x00000002

◆ USB_TXCSRL5_FLUSH

#define USB_TXCSRL5_FLUSH   0x00000008

◆ USB_TXCSRL5_NAKTO

#define USB_TXCSRL5_NAKTO   0x00000080

◆ USB_TXCSRL5_SETUP

#define USB_TXCSRL5_SETUP   0x00000010

◆ USB_TXCSRL5_STALL

#define USB_TXCSRL5_STALL   0x00000010

◆ USB_TXCSRL5_STALLED

#define USB_TXCSRL5_STALLED   0x00000020

◆ USB_TXCSRL5_TXRDY

#define USB_TXCSRL5_TXRDY   0x00000001

◆ USB_TXCSRL5_UNDRN

#define USB_TXCSRL5_UNDRN   0x00000004

◆ USB_TXCSRL6_CLRDT

#define USB_TXCSRL6_CLRDT   0x00000040

◆ USB_TXCSRL6_ERROR

#define USB_TXCSRL6_ERROR   0x00000004

◆ USB_TXCSRL6_FIFONE

#define USB_TXCSRL6_FIFONE   0x00000002

◆ USB_TXCSRL6_FLUSH

#define USB_TXCSRL6_FLUSH   0x00000008

◆ USB_TXCSRL6_NAKTO

#define USB_TXCSRL6_NAKTO   0x00000080

◆ USB_TXCSRL6_SETUP

#define USB_TXCSRL6_SETUP   0x00000010

◆ USB_TXCSRL6_STALL

#define USB_TXCSRL6_STALL   0x00000010

◆ USB_TXCSRL6_STALLED

#define USB_TXCSRL6_STALLED   0x00000020

◆ USB_TXCSRL6_TXRDY

#define USB_TXCSRL6_TXRDY   0x00000001

◆ USB_TXCSRL6_UNDRN

#define USB_TXCSRL6_UNDRN   0x00000004

◆ USB_TXCSRL7_CLRDT

#define USB_TXCSRL7_CLRDT   0x00000040

◆ USB_TXCSRL7_ERROR

#define USB_TXCSRL7_ERROR   0x00000004

◆ USB_TXCSRL7_FIFONE

#define USB_TXCSRL7_FIFONE   0x00000002

◆ USB_TXCSRL7_FLUSH

#define USB_TXCSRL7_FLUSH   0x00000008

◆ USB_TXCSRL7_NAKTO

#define USB_TXCSRL7_NAKTO   0x00000080

◆ USB_TXCSRL7_SETUP

#define USB_TXCSRL7_SETUP   0x00000010

◆ USB_TXCSRL7_STALL

#define USB_TXCSRL7_STALL   0x00000010

◆ USB_TXCSRL7_STALLED

#define USB_TXCSRL7_STALLED   0x00000020

◆ USB_TXCSRL7_TXRDY

#define USB_TXCSRL7_TXRDY   0x00000001

◆ USB_TXCSRL7_UNDRN

#define USB_TXCSRL7_UNDRN   0x00000004

◆ USB_TXDPKTBUFDIS_EP1

#define USB_TXDPKTBUFDIS_EP1   0x00000002

◆ USB_TXDPKTBUFDIS_EP2

#define USB_TXDPKTBUFDIS_EP2   0x00000004

◆ USB_TXDPKTBUFDIS_EP3

#define USB_TXDPKTBUFDIS_EP3   0x00000008

◆ USB_TXDPKTBUFDIS_EP4

#define USB_TXDPKTBUFDIS_EP4   0x00000010

◆ USB_TXDPKTBUFDIS_EP5

#define USB_TXDPKTBUFDIS_EP5   0x00000020

◆ USB_TXDPKTBUFDIS_EP6

#define USB_TXDPKTBUFDIS_EP6   0x00000040

◆ USB_TXDPKTBUFDIS_EP7

#define USB_TXDPKTBUFDIS_EP7   0x00000080

◆ USB_TXFIFOADD_ADDR_M

#define USB_TXFIFOADD_ADDR_M   0x000001FF

◆ USB_TXFIFOADD_ADDR_S

#define USB_TXFIFOADD_ADDR_S   0

◆ USB_TXFIFOSZ_DPB

#define USB_TXFIFOSZ_DPB   0x00000010

◆ USB_TXFIFOSZ_SIZE_1024

#define USB_TXFIFOSZ_SIZE_1024   0x00000007

◆ USB_TXFIFOSZ_SIZE_128

#define USB_TXFIFOSZ_SIZE_128   0x00000004

◆ USB_TXFIFOSZ_SIZE_16

#define USB_TXFIFOSZ_SIZE_16   0x00000001

◆ USB_TXFIFOSZ_SIZE_2048

#define USB_TXFIFOSZ_SIZE_2048   0x00000008

◆ USB_TXFIFOSZ_SIZE_256

#define USB_TXFIFOSZ_SIZE_256   0x00000005

◆ USB_TXFIFOSZ_SIZE_32

#define USB_TXFIFOSZ_SIZE_32   0x00000002

◆ USB_TXFIFOSZ_SIZE_512

#define USB_TXFIFOSZ_SIZE_512   0x00000006

◆ USB_TXFIFOSZ_SIZE_64

#define USB_TXFIFOSZ_SIZE_64   0x00000003

◆ USB_TXFIFOSZ_SIZE_8

#define USB_TXFIFOSZ_SIZE_8   0x00000000

◆ USB_TXFIFOSZ_SIZE_M

#define USB_TXFIFOSZ_SIZE_M   0x0000000F

◆ USB_TXFUNCADDR0_ADDR_M

#define USB_TXFUNCADDR0_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR0_ADDR_S

#define USB_TXFUNCADDR0_ADDR_S   0

◆ USB_TXFUNCADDR1_ADDR_M

#define USB_TXFUNCADDR1_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR1_ADDR_S

#define USB_TXFUNCADDR1_ADDR_S   0

◆ USB_TXFUNCADDR2_ADDR_M

#define USB_TXFUNCADDR2_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR2_ADDR_S

#define USB_TXFUNCADDR2_ADDR_S   0

◆ USB_TXFUNCADDR3_ADDR_M

#define USB_TXFUNCADDR3_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR3_ADDR_S

#define USB_TXFUNCADDR3_ADDR_S   0

◆ USB_TXFUNCADDR4_ADDR_M

#define USB_TXFUNCADDR4_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR4_ADDR_S

#define USB_TXFUNCADDR4_ADDR_S   0

◆ USB_TXFUNCADDR5_ADDR_M

#define USB_TXFUNCADDR5_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR5_ADDR_S

#define USB_TXFUNCADDR5_ADDR_S   0

◆ USB_TXFUNCADDR6_ADDR_M

#define USB_TXFUNCADDR6_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR6_ADDR_S

#define USB_TXFUNCADDR6_ADDR_S   0

◆ USB_TXFUNCADDR7_ADDR_M

#define USB_TXFUNCADDR7_ADDR_M   0x0000007F

◆ USB_TXFUNCADDR7_ADDR_S

#define USB_TXFUNCADDR7_ADDR_S   0

◆ USB_TXHUBADDR0_ADDR_M

#define USB_TXHUBADDR0_ADDR_M   0x0000007F

◆ USB_TXHUBADDR0_ADDR_S

#define USB_TXHUBADDR0_ADDR_S   0

◆ USB_TXHUBADDR1_ADDR_M

#define USB_TXHUBADDR1_ADDR_M   0x0000007F

◆ USB_TXHUBADDR1_ADDR_S

#define USB_TXHUBADDR1_ADDR_S   0

◆ USB_TXHUBADDR2_ADDR_M

#define USB_TXHUBADDR2_ADDR_M   0x0000007F

◆ USB_TXHUBADDR2_ADDR_S

#define USB_TXHUBADDR2_ADDR_S   0

◆ USB_TXHUBADDR3_ADDR_M

#define USB_TXHUBADDR3_ADDR_M   0x0000007F

◆ USB_TXHUBADDR3_ADDR_S

#define USB_TXHUBADDR3_ADDR_S   0

◆ USB_TXHUBADDR4_ADDR_M

#define USB_TXHUBADDR4_ADDR_M   0x0000007F

◆ USB_TXHUBADDR4_ADDR_S

#define USB_TXHUBADDR4_ADDR_S   0

◆ USB_TXHUBADDR5_ADDR_M

#define USB_TXHUBADDR5_ADDR_M   0x0000007F

◆ USB_TXHUBADDR5_ADDR_S

#define USB_TXHUBADDR5_ADDR_S   0

◆ USB_TXHUBADDR6_ADDR_M

#define USB_TXHUBADDR6_ADDR_M   0x0000007F

◆ USB_TXHUBADDR6_ADDR_S

#define USB_TXHUBADDR6_ADDR_S   0

◆ USB_TXHUBADDR7_ADDR_M

#define USB_TXHUBADDR7_ADDR_M   0x0000007F

◆ USB_TXHUBADDR7_ADDR_S

#define USB_TXHUBADDR7_ADDR_S   0

◆ USB_TXHUBPORT0_PORT_M

#define USB_TXHUBPORT0_PORT_M   0x0000007F

◆ USB_TXHUBPORT0_PORT_S

#define USB_TXHUBPORT0_PORT_S   0

◆ USB_TXHUBPORT1_PORT_M

#define USB_TXHUBPORT1_PORT_M   0x0000007F

◆ USB_TXHUBPORT1_PORT_S

#define USB_TXHUBPORT1_PORT_S   0

◆ USB_TXHUBPORT2_PORT_M

#define USB_TXHUBPORT2_PORT_M   0x0000007F

◆ USB_TXHUBPORT2_PORT_S

#define USB_TXHUBPORT2_PORT_S   0

◆ USB_TXHUBPORT3_PORT_M

#define USB_TXHUBPORT3_PORT_M   0x0000007F

◆ USB_TXHUBPORT3_PORT_S

#define USB_TXHUBPORT3_PORT_S   0

◆ USB_TXHUBPORT4_PORT_M

#define USB_TXHUBPORT4_PORT_M   0x0000007F

◆ USB_TXHUBPORT4_PORT_S

#define USB_TXHUBPORT4_PORT_S   0

◆ USB_TXHUBPORT5_PORT_M

#define USB_TXHUBPORT5_PORT_M   0x0000007F

◆ USB_TXHUBPORT5_PORT_S

#define USB_TXHUBPORT5_PORT_S   0

◆ USB_TXHUBPORT6_PORT_M

#define USB_TXHUBPORT6_PORT_M   0x0000007F

◆ USB_TXHUBPORT6_PORT_S

#define USB_TXHUBPORT6_PORT_S   0

◆ USB_TXHUBPORT7_PORT_M

#define USB_TXHUBPORT7_PORT_M   0x0000007F

◆ USB_TXHUBPORT7_PORT_S

#define USB_TXHUBPORT7_PORT_S   0

◆ USB_TXIE_EP0

#define USB_TXIE_EP0   0x00000001

◆ USB_TXIE_EP1

#define USB_TXIE_EP1   0x00000002

◆ USB_TXIE_EP2

#define USB_TXIE_EP2   0x00000004

◆ USB_TXIE_EP3

#define USB_TXIE_EP3   0x00000008

◆ USB_TXIE_EP4

#define USB_TXIE_EP4   0x00000010

◆ USB_TXIE_EP5

#define USB_TXIE_EP5   0x00000020

◆ USB_TXIE_EP6

#define USB_TXIE_EP6   0x00000040

◆ USB_TXIE_EP7

#define USB_TXIE_EP7   0x00000080

◆ USB_TXINTERVAL1_NAKLMT_M

#define USB_TXINTERVAL1_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL1_NAKLMT_S

#define USB_TXINTERVAL1_NAKLMT_S    0

◆ USB_TXINTERVAL1_TXPOLL_M

#define USB_TXINTERVAL1_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL1_TXPOLL_S

#define USB_TXINTERVAL1_TXPOLL_S    0

◆ USB_TXINTERVAL2_NAKLMT_M

#define USB_TXINTERVAL2_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL2_NAKLMT_S

#define USB_TXINTERVAL2_NAKLMT_S    0

◆ USB_TXINTERVAL2_TXPOLL_M

#define USB_TXINTERVAL2_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL2_TXPOLL_S

#define USB_TXINTERVAL2_TXPOLL_S    0

◆ USB_TXINTERVAL3_NAKLMT_M

#define USB_TXINTERVAL3_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL3_NAKLMT_S

#define USB_TXINTERVAL3_NAKLMT_S    0

◆ USB_TXINTERVAL3_TXPOLL_M

#define USB_TXINTERVAL3_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL3_TXPOLL_S

#define USB_TXINTERVAL3_TXPOLL_S    0

◆ USB_TXINTERVAL4_NAKLMT_M

#define USB_TXINTERVAL4_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL4_NAKLMT_S

#define USB_TXINTERVAL4_NAKLMT_S    0

◆ USB_TXINTERVAL4_TXPOLL_M

#define USB_TXINTERVAL4_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL4_TXPOLL_S

#define USB_TXINTERVAL4_TXPOLL_S    0

◆ USB_TXINTERVAL5_NAKLMT_M

#define USB_TXINTERVAL5_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL5_NAKLMT_S

#define USB_TXINTERVAL5_NAKLMT_S    0

◆ USB_TXINTERVAL5_TXPOLL_M

#define USB_TXINTERVAL5_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL5_TXPOLL_S

#define USB_TXINTERVAL5_TXPOLL_S    0

◆ USB_TXINTERVAL6_NAKLMT_M

#define USB_TXINTERVAL6_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL6_NAKLMT_S

#define USB_TXINTERVAL6_NAKLMT_S    0

◆ USB_TXINTERVAL6_TXPOLL_M

#define USB_TXINTERVAL6_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL6_TXPOLL_S

#define USB_TXINTERVAL6_TXPOLL_S    0

◆ USB_TXINTERVAL7_NAKLMT_M

#define USB_TXINTERVAL7_NAKLMT_M    0x000000FF

◆ USB_TXINTERVAL7_NAKLMT_S

#define USB_TXINTERVAL7_NAKLMT_S    0

◆ USB_TXINTERVAL7_TXPOLL_M

#define USB_TXINTERVAL7_TXPOLL_M    0x000000FF

◆ USB_TXINTERVAL7_TXPOLL_S

#define USB_TXINTERVAL7_TXPOLL_S    0

◆ USB_TXIS_EP0

#define USB_TXIS_EP0   0x00000001

◆ USB_TXIS_EP1

#define USB_TXIS_EP1   0x00000002

◆ USB_TXIS_EP2

#define USB_TXIS_EP2   0x00000004

◆ USB_TXIS_EP3

#define USB_TXIS_EP3   0x00000008

◆ USB_TXIS_EP4

#define USB_TXIS_EP4   0x00000010

◆ USB_TXIS_EP5

#define USB_TXIS_EP5   0x00000020

◆ USB_TXIS_EP6

#define USB_TXIS_EP6   0x00000040

◆ USB_TXIS_EP7

#define USB_TXIS_EP7   0x00000080

◆ USB_TXMAXP1_MAXLOAD_M

#define USB_TXMAXP1_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP1_MAXLOAD_S

#define USB_TXMAXP1_MAXLOAD_S   0

◆ USB_TXMAXP2_MAXLOAD_M

#define USB_TXMAXP2_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP2_MAXLOAD_S

#define USB_TXMAXP2_MAXLOAD_S   0

◆ USB_TXMAXP3_MAXLOAD_M

#define USB_TXMAXP3_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP3_MAXLOAD_S

#define USB_TXMAXP3_MAXLOAD_S   0

◆ USB_TXMAXP4_MAXLOAD_M

#define USB_TXMAXP4_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP4_MAXLOAD_S

#define USB_TXMAXP4_MAXLOAD_S   0

◆ USB_TXMAXP5_MAXLOAD_M

#define USB_TXMAXP5_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP5_MAXLOAD_S

#define USB_TXMAXP5_MAXLOAD_S   0

◆ USB_TXMAXP6_MAXLOAD_M

#define USB_TXMAXP6_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP6_MAXLOAD_S

#define USB_TXMAXP6_MAXLOAD_S   0

◆ USB_TXMAXP7_MAXLOAD_M

#define USB_TXMAXP7_MAXLOAD_M   0x000007FF

◆ USB_TXMAXP7_MAXLOAD_S

#define USB_TXMAXP7_MAXLOAD_S   0

◆ USB_TXTYPE1_PROTO_BULK

#define USB_TXTYPE1_PROTO_BULK   0x00000020

◆ USB_TXTYPE1_PROTO_CTRL

#define USB_TXTYPE1_PROTO_CTRL   0x00000000

◆ USB_TXTYPE1_PROTO_INT

#define USB_TXTYPE1_PROTO_INT   0x00000030

◆ USB_TXTYPE1_PROTO_ISOC

#define USB_TXTYPE1_PROTO_ISOC   0x00000010

◆ USB_TXTYPE1_PROTO_M

#define USB_TXTYPE1_PROTO_M   0x00000030

◆ USB_TXTYPE1_SPEED_DFLT

#define USB_TXTYPE1_SPEED_DFLT   0x00000000

◆ USB_TXTYPE1_SPEED_FULL

#define USB_TXTYPE1_SPEED_FULL   0x00000080

◆ USB_TXTYPE1_SPEED_LOW

#define USB_TXTYPE1_SPEED_LOW   0x000000C0

◆ USB_TXTYPE1_SPEED_M

#define USB_TXTYPE1_SPEED_M   0x000000C0

◆ USB_TXTYPE1_TEP_M

#define USB_TXTYPE1_TEP_M   0x0000000F

◆ USB_TXTYPE1_TEP_S

#define USB_TXTYPE1_TEP_S   0

◆ USB_TXTYPE2_PROTO_BULK

#define USB_TXTYPE2_PROTO_BULK   0x00000020

◆ USB_TXTYPE2_PROTO_CTRL

#define USB_TXTYPE2_PROTO_CTRL   0x00000000

◆ USB_TXTYPE2_PROTO_INT

#define USB_TXTYPE2_PROTO_INT   0x00000030

◆ USB_TXTYPE2_PROTO_ISOC

#define USB_TXTYPE2_PROTO_ISOC   0x00000010

◆ USB_TXTYPE2_PROTO_M

#define USB_TXTYPE2_PROTO_M   0x00000030

◆ USB_TXTYPE2_SPEED_DFLT

#define USB_TXTYPE2_SPEED_DFLT   0x00000000

◆ USB_TXTYPE2_SPEED_FULL

#define USB_TXTYPE2_SPEED_FULL   0x00000080

◆ USB_TXTYPE2_SPEED_LOW

#define USB_TXTYPE2_SPEED_LOW   0x000000C0

◆ USB_TXTYPE2_SPEED_M

#define USB_TXTYPE2_SPEED_M   0x000000C0

◆ USB_TXTYPE2_TEP_M

#define USB_TXTYPE2_TEP_M   0x0000000F

◆ USB_TXTYPE2_TEP_S

#define USB_TXTYPE2_TEP_S   0

◆ USB_TXTYPE3_PROTO_BULK

#define USB_TXTYPE3_PROTO_BULK   0x00000020

◆ USB_TXTYPE3_PROTO_CTRL

#define USB_TXTYPE3_PROTO_CTRL   0x00000000

◆ USB_TXTYPE3_PROTO_INT

#define USB_TXTYPE3_PROTO_INT   0x00000030

◆ USB_TXTYPE3_PROTO_ISOC

#define USB_TXTYPE3_PROTO_ISOC   0x00000010

◆ USB_TXTYPE3_PROTO_M

#define USB_TXTYPE3_PROTO_M   0x00000030

◆ USB_TXTYPE3_SPEED_DFLT

#define USB_TXTYPE3_SPEED_DFLT   0x00000000

◆ USB_TXTYPE3_SPEED_FULL

#define USB_TXTYPE3_SPEED_FULL   0x00000080

◆ USB_TXTYPE3_SPEED_LOW

#define USB_TXTYPE3_SPEED_LOW   0x000000C0

◆ USB_TXTYPE3_SPEED_M

#define USB_TXTYPE3_SPEED_M   0x000000C0

◆ USB_TXTYPE3_TEP_M

#define USB_TXTYPE3_TEP_M   0x0000000F

◆ USB_TXTYPE3_TEP_S

#define USB_TXTYPE3_TEP_S   0

◆ USB_TXTYPE4_PROTO_BULK

#define USB_TXTYPE4_PROTO_BULK   0x00000020

◆ USB_TXTYPE4_PROTO_CTRL

#define USB_TXTYPE4_PROTO_CTRL   0x00000000

◆ USB_TXTYPE4_PROTO_INT

#define USB_TXTYPE4_PROTO_INT   0x00000030

◆ USB_TXTYPE4_PROTO_ISOC

#define USB_TXTYPE4_PROTO_ISOC   0x00000010

◆ USB_TXTYPE4_PROTO_M

#define USB_TXTYPE4_PROTO_M   0x00000030

◆ USB_TXTYPE4_SPEED_DFLT

#define USB_TXTYPE4_SPEED_DFLT   0x00000000

◆ USB_TXTYPE4_SPEED_FULL

#define USB_TXTYPE4_SPEED_FULL   0x00000080

◆ USB_TXTYPE4_SPEED_LOW

#define USB_TXTYPE4_SPEED_LOW   0x000000C0

◆ USB_TXTYPE4_SPEED_M

#define USB_TXTYPE4_SPEED_M   0x000000C0

◆ USB_TXTYPE4_TEP_M

#define USB_TXTYPE4_TEP_M   0x0000000F

◆ USB_TXTYPE4_TEP_S

#define USB_TXTYPE4_TEP_S   0

◆ USB_TXTYPE5_PROTO_BULK

#define USB_TXTYPE5_PROTO_BULK   0x00000020

◆ USB_TXTYPE5_PROTO_CTRL

#define USB_TXTYPE5_PROTO_CTRL   0x00000000

◆ USB_TXTYPE5_PROTO_INT

#define USB_TXTYPE5_PROTO_INT   0x00000030

◆ USB_TXTYPE5_PROTO_ISOC

#define USB_TXTYPE5_PROTO_ISOC   0x00000010

◆ USB_TXTYPE5_PROTO_M

#define USB_TXTYPE5_PROTO_M   0x00000030

◆ USB_TXTYPE5_SPEED_DFLT

#define USB_TXTYPE5_SPEED_DFLT   0x00000000

◆ USB_TXTYPE5_SPEED_FULL

#define USB_TXTYPE5_SPEED_FULL   0x00000080

◆ USB_TXTYPE5_SPEED_LOW

#define USB_TXTYPE5_SPEED_LOW   0x000000C0

◆ USB_TXTYPE5_SPEED_M

#define USB_TXTYPE5_SPEED_M   0x000000C0

◆ USB_TXTYPE5_TEP_M

#define USB_TXTYPE5_TEP_M   0x0000000F

◆ USB_TXTYPE5_TEP_S

#define USB_TXTYPE5_TEP_S   0

◆ USB_TXTYPE6_PROTO_BULK

#define USB_TXTYPE6_PROTO_BULK   0x00000020

◆ USB_TXTYPE6_PROTO_CTRL

#define USB_TXTYPE6_PROTO_CTRL   0x00000000

◆ USB_TXTYPE6_PROTO_INT

#define USB_TXTYPE6_PROTO_INT   0x00000030

◆ USB_TXTYPE6_PROTO_ISOC

#define USB_TXTYPE6_PROTO_ISOC   0x00000010

◆ USB_TXTYPE6_PROTO_M

#define USB_TXTYPE6_PROTO_M   0x00000030

◆ USB_TXTYPE6_SPEED_DFLT

#define USB_TXTYPE6_SPEED_DFLT   0x00000000

◆ USB_TXTYPE6_SPEED_FULL

#define USB_TXTYPE6_SPEED_FULL   0x00000080

◆ USB_TXTYPE6_SPEED_LOW

#define USB_TXTYPE6_SPEED_LOW   0x000000C0

◆ USB_TXTYPE6_SPEED_M

#define USB_TXTYPE6_SPEED_M   0x000000C0

◆ USB_TXTYPE6_TEP_M

#define USB_TXTYPE6_TEP_M   0x0000000F

◆ USB_TXTYPE6_TEP_S

#define USB_TXTYPE6_TEP_S   0

◆ USB_TXTYPE7_PROTO_BULK

#define USB_TXTYPE7_PROTO_BULK   0x00000020

◆ USB_TXTYPE7_PROTO_CTRL

#define USB_TXTYPE7_PROTO_CTRL   0x00000000

◆ USB_TXTYPE7_PROTO_INT

#define USB_TXTYPE7_PROTO_INT   0x00000030

◆ USB_TXTYPE7_PROTO_ISOC

#define USB_TXTYPE7_PROTO_ISOC   0x00000010

◆ USB_TXTYPE7_PROTO_M

#define USB_TXTYPE7_PROTO_M   0x00000030

◆ USB_TXTYPE7_SPEED_DFLT

#define USB_TXTYPE7_SPEED_DFLT   0x00000000

◆ USB_TXTYPE7_SPEED_FULL

#define USB_TXTYPE7_SPEED_FULL   0x00000080

◆ USB_TXTYPE7_SPEED_LOW

#define USB_TXTYPE7_SPEED_LOW   0x000000C0

◆ USB_TXTYPE7_SPEED_M

#define USB_TXTYPE7_SPEED_M   0x000000C0

◆ USB_TXTYPE7_TEP_M

#define USB_TXTYPE7_TEP_M   0x0000000F

◆ USB_TXTYPE7_TEP_S

#define USB_TXTYPE7_TEP_S   0

◆ USB_TYPE0_SPEED_FULL

#define USB_TYPE0_SPEED_FULL   0x00000080

◆ USB_TYPE0_SPEED_LOW

#define USB_TYPE0_SPEED_LOW   0x000000C0

◆ USB_TYPE0_SPEED_M

#define USB_TYPE0_SPEED_M   0x000000C0

◆ USB_VDC_VBDEN

#define USB_VDC_VBDEN   0x00000001

◆ USB_VDCIM_VD

#define USB_VDCIM_VD   0x00000001

◆ USB_VDCISC_VD

#define USB_VDCISC_VD   0x00000001

◆ USB_VDCRIS_VD

#define USB_VDCRIS_VD   0x00000001

◆ USB_VPLEN_VPLEN_M

#define USB_VPLEN_VPLEN_M   0x000000FF

◆ USB_VPLEN_VPLEN_S

#define USB_VPLEN_VPLEN_S   0

◆ WATCHDOG0_CTL_R

#define WATCHDOG0_CTL_R   (*((volatile u32 *)0x40000008))

◆ WATCHDOG0_ICR_R

#define WATCHDOG0_ICR_R   (*((volatile u32 *)0x4000000C))

◆ WATCHDOG0_LOAD_R

#define WATCHDOG0_LOAD_R   (*((volatile u32 *)0x40000000))

◆ WATCHDOG0_LOCK_R

#define WATCHDOG0_LOCK_R   (*((volatile u32 *)0x40000C00))

◆ WATCHDOG0_MIS_R

#define WATCHDOG0_MIS_R   (*((volatile u32 *)0x40000014))

◆ WATCHDOG0_RIS_R

#define WATCHDOG0_RIS_R   (*((volatile u32 *)0x40000010))

◆ WATCHDOG0_TEST_R

#define WATCHDOG0_TEST_R   (*((volatile u32 *)0x40000418))

◆ WATCHDOG0_VALUE_R

#define WATCHDOG0_VALUE_R   (*((volatile u32 *)0x40000004))

◆ WATCHDOG1_CTL_R

#define WATCHDOG1_CTL_R   (*((volatile u32 *)0x40001008))

◆ WATCHDOG1_ICR_R

#define WATCHDOG1_ICR_R   (*((volatile u32 *)0x4000100C))

◆ WATCHDOG1_LOAD_R

#define WATCHDOG1_LOAD_R   (*((volatile u32 *)0x40001000))

◆ WATCHDOG1_LOCK_R

#define WATCHDOG1_LOCK_R   (*((volatile u32 *)0x40001C00))

◆ WATCHDOG1_MIS_R

#define WATCHDOG1_MIS_R   (*((volatile u32 *)0x40001014))

◆ WATCHDOG1_RIS_R

#define WATCHDOG1_RIS_R   (*((volatile u32 *)0x40001010))

◆ WATCHDOG1_TEST_R

#define WATCHDOG1_TEST_R   (*((volatile u32 *)0x40001418))

◆ WATCHDOG1_VALUE_R

#define WATCHDOG1_VALUE_R   (*((volatile u32 *)0x40001004))

◆ WDT_CTL_INTEN

#define WDT_CTL_INTEN   0x00000001

◆ WDT_CTL_INTTYPE

#define WDT_CTL_INTTYPE   0x00000004

◆ WDT_CTL_RESEN

#define WDT_CTL_RESEN   0x00000002

◆ WDT_CTL_WRC

#define WDT_CTL_WRC   0x80000000

◆ WDT_ICR_M

#define WDT_ICR_M   0xFFFFFFFF

◆ WDT_ICR_S

#define WDT_ICR_S   0

◆ WDT_LOAD_M

#define WDT_LOAD_M   0xFFFFFFFF

◆ WDT_LOAD_S

#define WDT_LOAD_S   0

◆ WDT_LOCK_LOCKED

#define WDT_LOCK_LOCKED   0x00000001

◆ WDT_LOCK_M

#define WDT_LOCK_M   0xFFFFFFFF

◆ WDT_LOCK_UNLOCK

#define WDT_LOCK_UNLOCK   0x1ACCE551

◆ WDT_LOCK_UNLOCKED

#define WDT_LOCK_UNLOCKED   0x00000000

◆ WDT_MIS_WDTMIS

#define WDT_MIS_WDTMIS   0x00000001

◆ WDT_RIS_WDTRIS

#define WDT_RIS_WDTRIS   0x00000001

◆ WDT_TEST_STALL

#define WDT_TEST_STALL   0x00000100

◆ WDT_VALUE_M

#define WDT_VALUE_M   0xFFFFFFFF

◆ WDT_VALUE_S

#define WDT_VALUE_S   0

◆ WTIMER0_CFG_R

#define WTIMER0_CFG_R   (*((volatile u32 *)0x40036000))

◆ WTIMER0_CTL_R

#define WTIMER0_CTL_R   (*((volatile u32 *)0x4003600C))

◆ WTIMER0_ICR_R

#define WTIMER0_ICR_R   (*((volatile u32 *)0x40036024))

◆ WTIMER0_IMR_R

#define WTIMER0_IMR_R   (*((volatile u32 *)0x40036018))

◆ WTIMER0_MIS_R

#define WTIMER0_MIS_R   (*((volatile u32 *)0x40036020))

◆ WTIMER0_PP_R

#define WTIMER0_PP_R   (*((volatile u32 *)0x40036FC0))

◆ WTIMER0_RIS_R

#define WTIMER0_RIS_R   (*((volatile u32 *)0x4003601C))

◆ WTIMER0_RTCPD_R

#define WTIMER0_RTCPD_R   (*((volatile u32 *)0x40036058))

◆ WTIMER0_SYNC_R

#define WTIMER0_SYNC_R   (*((volatile u32 *)0x40036010))

◆ WTIMER0_TAILR_R

#define WTIMER0_TAILR_R   (*((volatile u32 *)0x40036028))

◆ WTIMER0_TAMATCHR_R

#define WTIMER0_TAMATCHR_R   (*((volatile u32 *)0x40036030))

◆ WTIMER0_TAMR_R

#define WTIMER0_TAMR_R   (*((volatile u32 *)0x40036004))

◆ WTIMER0_TAPMR_R

#define WTIMER0_TAPMR_R   (*((volatile u32 *)0x40036040))

◆ WTIMER0_TAPR_R

#define WTIMER0_TAPR_R   (*((volatile u32 *)0x40036038))

◆ WTIMER0_TAPS_R

#define WTIMER0_TAPS_R   (*((volatile u32 *)0x4003605C))

◆ WTIMER0_TAPV_R

#define WTIMER0_TAPV_R   (*((volatile u32 *)0x40036064))

◆ WTIMER0_TAR_R

#define WTIMER0_TAR_R   (*((volatile u32 *)0x40036048))

◆ WTIMER0_TAV_R

#define WTIMER0_TAV_R   (*((volatile u32 *)0x40036050))

◆ WTIMER0_TBILR_R

#define WTIMER0_TBILR_R   (*((volatile u32 *)0x4003602C))

◆ WTIMER0_TBMATCHR_R

#define WTIMER0_TBMATCHR_R   (*((volatile u32 *)0x40036034))

◆ WTIMER0_TBMR_R

#define WTIMER0_TBMR_R   (*((volatile u32 *)0x40036008))

◆ WTIMER0_TBPMR_R

#define WTIMER0_TBPMR_R   (*((volatile u32 *)0x40036044))

◆ WTIMER0_TBPR_R

#define WTIMER0_TBPR_R   (*((volatile u32 *)0x4003603C))

◆ WTIMER0_TBPS_R

#define WTIMER0_TBPS_R   (*((volatile u32 *)0x40036060))

◆ WTIMER0_TBPV_R

#define WTIMER0_TBPV_R   (*((volatile u32 *)0x40036068))

◆ WTIMER0_TBR_R

#define WTIMER0_TBR_R   (*((volatile u32 *)0x4003604C))

◆ WTIMER0_TBV_R

#define WTIMER0_TBV_R   (*((volatile u32 *)0x40036054))

◆ WTIMER1_CFG_R

#define WTIMER1_CFG_R   (*((volatile u32 *)0x40037000))

◆ WTIMER1_CTL_R

#define WTIMER1_CTL_R   (*((volatile u32 *)0x4003700C))

◆ WTIMER1_ICR_R

#define WTIMER1_ICR_R   (*((volatile u32 *)0x40037024))

◆ WTIMER1_IMR_R

#define WTIMER1_IMR_R   (*((volatile u32 *)0x40037018))

◆ WTIMER1_MIS_R

#define WTIMER1_MIS_R   (*((volatile u32 *)0x40037020))

◆ WTIMER1_PP_R

#define WTIMER1_PP_R   (*((volatile u32 *)0x40037FC0))

◆ WTIMER1_RIS_R

#define WTIMER1_RIS_R   (*((volatile u32 *)0x4003701C))

◆ WTIMER1_RTCPD_R

#define WTIMER1_RTCPD_R   (*((volatile u32 *)0x40037058))

◆ WTIMER1_SYNC_R

#define WTIMER1_SYNC_R   (*((volatile u32 *)0x40037010))

◆ WTIMER1_TAILR_R

#define WTIMER1_TAILR_R   (*((volatile u32 *)0x40037028))

◆ WTIMER1_TAMATCHR_R

#define WTIMER1_TAMATCHR_R   (*((volatile u32 *)0x40037030))

◆ WTIMER1_TAMR_R

#define WTIMER1_TAMR_R   (*((volatile u32 *)0x40037004))

◆ WTIMER1_TAPMR_R

#define WTIMER1_TAPMR_R   (*((volatile u32 *)0x40037040))

◆ WTIMER1_TAPR_R

#define WTIMER1_TAPR_R   (*((volatile u32 *)0x40037038))

◆ WTIMER1_TAPS_R

#define WTIMER1_TAPS_R   (*((volatile u32 *)0x4003705C))

◆ WTIMER1_TAPV_R

#define WTIMER1_TAPV_R   (*((volatile u32 *)0x40037064))

◆ WTIMER1_TAR_R

#define WTIMER1_TAR_R   (*((volatile u32 *)0x40037048))

◆ WTIMER1_TAV_R

#define WTIMER1_TAV_R   (*((volatile u32 *)0x40037050))

◆ WTIMER1_TBILR_R

#define WTIMER1_TBILR_R   (*((volatile u32 *)0x4003702C))

◆ WTIMER1_TBMATCHR_R

#define WTIMER1_TBMATCHR_R   (*((volatile u32 *)0x40037034))

◆ WTIMER1_TBMR_R

#define WTIMER1_TBMR_R   (*((volatile u32 *)0x40037008))

◆ WTIMER1_TBPMR_R

#define WTIMER1_TBPMR_R   (*((volatile u32 *)0x40037044))

◆ WTIMER1_TBPR_R

#define WTIMER1_TBPR_R   (*((volatile u32 *)0x4003703C))

◆ WTIMER1_TBPS_R

#define WTIMER1_TBPS_R   (*((volatile u32 *)0x40037060))

◆ WTIMER1_TBPV_R

#define WTIMER1_TBPV_R   (*((volatile u32 *)0x40037068))

◆ WTIMER1_TBR_R

#define WTIMER1_TBR_R   (*((volatile u32 *)0x4003704C))

◆ WTIMER1_TBV_R

#define WTIMER1_TBV_R   (*((volatile u32 *)0x40037054))

◆ WTIMER2_CFG_R

#define WTIMER2_CFG_R   (*((volatile u32 *)0x4004C000))

◆ WTIMER2_CTL_R

#define WTIMER2_CTL_R   (*((volatile u32 *)0x4004C00C))

◆ WTIMER2_ICR_R

#define WTIMER2_ICR_R   (*((volatile u32 *)0x4004C024))

◆ WTIMER2_IMR_R

#define WTIMER2_IMR_R   (*((volatile u32 *)0x4004C018))

◆ WTIMER2_MIS_R

#define WTIMER2_MIS_R   (*((volatile u32 *)0x4004C020))

◆ WTIMER2_PP_R

#define WTIMER2_PP_R   (*((volatile u32 *)0x4004CFC0))

◆ WTIMER2_RIS_R

#define WTIMER2_RIS_R   (*((volatile u32 *)0x4004C01C))

◆ WTIMER2_RTCPD_R

#define WTIMER2_RTCPD_R   (*((volatile u32 *)0x4004C058))

◆ WTIMER2_SYNC_R

#define WTIMER2_SYNC_R   (*((volatile u32 *)0x4004C010))

◆ WTIMER2_TAILR_R

#define WTIMER2_TAILR_R   (*((volatile u32 *)0x4004C028))

◆ WTIMER2_TAMATCHR_R

#define WTIMER2_TAMATCHR_R   (*((volatile u32 *)0x4004C030))

◆ WTIMER2_TAMR_R

#define WTIMER2_TAMR_R   (*((volatile u32 *)0x4004C004))

◆ WTIMER2_TAPMR_R

#define WTIMER2_TAPMR_R   (*((volatile u32 *)0x4004C040))

◆ WTIMER2_TAPR_R

#define WTIMER2_TAPR_R   (*((volatile u32 *)0x4004C038))

◆ WTIMER2_TAPS_R

#define WTIMER2_TAPS_R   (*((volatile u32 *)0x4004C05C))

◆ WTIMER2_TAPV_R

#define WTIMER2_TAPV_R   (*((volatile u32 *)0x4004C064))

◆ WTIMER2_TAR_R

#define WTIMER2_TAR_R   (*((volatile u32 *)0x4004C048))

◆ WTIMER2_TAV_R

#define WTIMER2_TAV_R   (*((volatile u32 *)0x4004C050))

◆ WTIMER2_TBILR_R

#define WTIMER2_TBILR_R   (*((volatile u32 *)0x4004C02C))

◆ WTIMER2_TBMATCHR_R

#define WTIMER2_TBMATCHR_R   (*((volatile u32 *)0x4004C034))

◆ WTIMER2_TBMR_R

#define WTIMER2_TBMR_R   (*((volatile u32 *)0x4004C008))

◆ WTIMER2_TBPMR_R

#define WTIMER2_TBPMR_R   (*((volatile u32 *)0x4004C044))

◆ WTIMER2_TBPR_R

#define WTIMER2_TBPR_R   (*((volatile u32 *)0x4004C03C))

◆ WTIMER2_TBPS_R

#define WTIMER2_TBPS_R   (*((volatile u32 *)0x4004C060))

◆ WTIMER2_TBPV_R

#define WTIMER2_TBPV_R   (*((volatile u32 *)0x4004C068))

◆ WTIMER2_TBR_R

#define WTIMER2_TBR_R   (*((volatile u32 *)0x4004C04C))

◆ WTIMER2_TBV_R

#define WTIMER2_TBV_R   (*((volatile u32 *)0x4004C054))

◆ WTIMER3_CFG_R

#define WTIMER3_CFG_R   (*((volatile u32 *)0x4004D000))

◆ WTIMER3_CTL_R

#define WTIMER3_CTL_R   (*((volatile u32 *)0x4004D00C))

◆ WTIMER3_ICR_R

#define WTIMER3_ICR_R   (*((volatile u32 *)0x4004D024))

◆ WTIMER3_IMR_R

#define WTIMER3_IMR_R   (*((volatile u32 *)0x4004D018))

◆ WTIMER3_MIS_R

#define WTIMER3_MIS_R   (*((volatile u32 *)0x4004D020))

◆ WTIMER3_PP_R

#define WTIMER3_PP_R   (*((volatile u32 *)0x4004DFC0))

◆ WTIMER3_RIS_R

#define WTIMER3_RIS_R   (*((volatile u32 *)0x4004D01C))

◆ WTIMER3_RTCPD_R

#define WTIMER3_RTCPD_R   (*((volatile u32 *)0x4004D058))

◆ WTIMER3_SYNC_R

#define WTIMER3_SYNC_R   (*((volatile u32 *)0x4004D010))

◆ WTIMER3_TAILR_R

#define WTIMER3_TAILR_R   (*((volatile u32 *)0x4004D028))

◆ WTIMER3_TAMATCHR_R

#define WTIMER3_TAMATCHR_R   (*((volatile u32 *)0x4004D030))

◆ WTIMER3_TAMR_R

#define WTIMER3_TAMR_R   (*((volatile u32 *)0x4004D004))

◆ WTIMER3_TAPMR_R

#define WTIMER3_TAPMR_R   (*((volatile u32 *)0x4004D040))

◆ WTIMER3_TAPR_R

#define WTIMER3_TAPR_R   (*((volatile u32 *)0x4004D038))

◆ WTIMER3_TAPS_R

#define WTIMER3_TAPS_R   (*((volatile u32 *)0x4004D05C))

◆ WTIMER3_TAPV_R

#define WTIMER3_TAPV_R   (*((volatile u32 *)0x4004D064))

◆ WTIMER3_TAR_R

#define WTIMER3_TAR_R   (*((volatile u32 *)0x4004D048))

◆ WTIMER3_TAV_R

#define WTIMER3_TAV_R   (*((volatile u32 *)0x4004D050))

◆ WTIMER3_TBILR_R

#define WTIMER3_TBILR_R   (*((volatile u32 *)0x4004D02C))

◆ WTIMER3_TBMATCHR_R

#define WTIMER3_TBMATCHR_R   (*((volatile u32 *)0x4004D034))

◆ WTIMER3_TBMR_R

#define WTIMER3_TBMR_R   (*((volatile u32 *)0x4004D008))

◆ WTIMER3_TBPMR_R

#define WTIMER3_TBPMR_R   (*((volatile u32 *)0x4004D044))

◆ WTIMER3_TBPR_R

#define WTIMER3_TBPR_R   (*((volatile u32 *)0x4004D03C))

◆ WTIMER3_TBPS_R

#define WTIMER3_TBPS_R   (*((volatile u32 *)0x4004D060))

◆ WTIMER3_TBPV_R

#define WTIMER3_TBPV_R   (*((volatile u32 *)0x4004D068))

◆ WTIMER3_TBR_R

#define WTIMER3_TBR_R   (*((volatile u32 *)0x4004D04C))

◆ WTIMER3_TBV_R

#define WTIMER3_TBV_R   (*((volatile u32 *)0x4004D054))

◆ WTIMER4_CFG_R

#define WTIMER4_CFG_R   (*((volatile u32 *)0x4004E000))

◆ WTIMER4_CTL_R

#define WTIMER4_CTL_R   (*((volatile u32 *)0x4004E00C))

◆ WTIMER4_ICR_R

#define WTIMER4_ICR_R   (*((volatile u32 *)0x4004E024))

◆ WTIMER4_IMR_R

#define WTIMER4_IMR_R   (*((volatile u32 *)0x4004E018))

◆ WTIMER4_MIS_R

#define WTIMER4_MIS_R   (*((volatile u32 *)0x4004E020))

◆ WTIMER4_PP_R

#define WTIMER4_PP_R   (*((volatile u32 *)0x4004EFC0))

◆ WTIMER4_RIS_R

#define WTIMER4_RIS_R   (*((volatile u32 *)0x4004E01C))

◆ WTIMER4_RTCPD_R

#define WTIMER4_RTCPD_R   (*((volatile u32 *)0x4004E058))

◆ WTIMER4_SYNC_R

#define WTIMER4_SYNC_R   (*((volatile u32 *)0x4004E010))

◆ WTIMER4_TAILR_R

#define WTIMER4_TAILR_R   (*((volatile u32 *)0x4004E028))

◆ WTIMER4_TAMATCHR_R

#define WTIMER4_TAMATCHR_R   (*((volatile u32 *)0x4004E030))

◆ WTIMER4_TAMR_R

#define WTIMER4_TAMR_R   (*((volatile u32 *)0x4004E004))

◆ WTIMER4_TAPMR_R

#define WTIMER4_TAPMR_R   (*((volatile u32 *)0x4004E040))

◆ WTIMER4_TAPR_R

#define WTIMER4_TAPR_R   (*((volatile u32 *)0x4004E038))

◆ WTIMER4_TAPS_R

#define WTIMER4_TAPS_R   (*((volatile u32 *)0x4004E05C))

◆ WTIMER4_TAPV_R

#define WTIMER4_TAPV_R   (*((volatile u32 *)0x4004E064))

◆ WTIMER4_TAR_R

#define WTIMER4_TAR_R   (*((volatile u32 *)0x4004E048))

◆ WTIMER4_TAV_R

#define WTIMER4_TAV_R   (*((volatile u32 *)0x4004E050))

◆ WTIMER4_TBILR_R

#define WTIMER4_TBILR_R   (*((volatile u32 *)0x4004E02C))

◆ WTIMER4_TBMATCHR_R

#define WTIMER4_TBMATCHR_R   (*((volatile u32 *)0x4004E034))

◆ WTIMER4_TBMR_R

#define WTIMER4_TBMR_R   (*((volatile u32 *)0x4004E008))

◆ WTIMER4_TBPMR_R

#define WTIMER4_TBPMR_R   (*((volatile u32 *)0x4004E044))

◆ WTIMER4_TBPR_R

#define WTIMER4_TBPR_R   (*((volatile u32 *)0x4004E03C))

◆ WTIMER4_TBPS_R

#define WTIMER4_TBPS_R   (*((volatile u32 *)0x4004E060))

◆ WTIMER4_TBPV_R

#define WTIMER4_TBPV_R   (*((volatile u32 *)0x4004E068))

◆ WTIMER4_TBR_R

#define WTIMER4_TBR_R   (*((volatile u32 *)0x4004E04C))

◆ WTIMER4_TBV_R

#define WTIMER4_TBV_R   (*((volatile u32 *)0x4004E054))

◆ WTIMER5_CFG_R

#define WTIMER5_CFG_R   (*((volatile u32 *)0x4004F000))

◆ WTIMER5_CTL_R

#define WTIMER5_CTL_R   (*((volatile u32 *)0x4004F00C))

◆ WTIMER5_ICR_R

#define WTIMER5_ICR_R   (*((volatile u32 *)0x4004F024))

◆ WTIMER5_IMR_R

#define WTIMER5_IMR_R   (*((volatile u32 *)0x4004F018))

◆ WTIMER5_MIS_R

#define WTIMER5_MIS_R   (*((volatile u32 *)0x4004F020))

◆ WTIMER5_PP_R

#define WTIMER5_PP_R   (*((volatile u32 *)0x4004FFC0))

◆ WTIMER5_RIS_R

#define WTIMER5_RIS_R   (*((volatile u32 *)0x4004F01C))

◆ WTIMER5_RTCPD_R

#define WTIMER5_RTCPD_R   (*((volatile u32 *)0x4004F058))

◆ WTIMER5_SYNC_R

#define WTIMER5_SYNC_R   (*((volatile u32 *)0x4004F010))

◆ WTIMER5_TAILR_R

#define WTIMER5_TAILR_R   (*((volatile u32 *)0x4004F028))

◆ WTIMER5_TAMATCHR_R

#define WTIMER5_TAMATCHR_R   (*((volatile u32 *)0x4004F030))

◆ WTIMER5_TAMR_R

#define WTIMER5_TAMR_R   (*((volatile u32 *)0x4004F004))

◆ WTIMER5_TAPMR_R

#define WTIMER5_TAPMR_R   (*((volatile u32 *)0x4004F040))

◆ WTIMER5_TAPR_R

#define WTIMER5_TAPR_R   (*((volatile u32 *)0x4004F038))

◆ WTIMER5_TAPS_R

#define WTIMER5_TAPS_R   (*((volatile u32 *)0x4004F05C))

◆ WTIMER5_TAPV_R

#define WTIMER5_TAPV_R   (*((volatile u32 *)0x4004F064))

◆ WTIMER5_TAR_R

#define WTIMER5_TAR_R   (*((volatile u32 *)0x4004F048))

◆ WTIMER5_TAV_R

#define WTIMER5_TAV_R   (*((volatile u32 *)0x4004F050))

◆ WTIMER5_TBILR_R

#define WTIMER5_TBILR_R   (*((volatile u32 *)0x4004F02C))

◆ WTIMER5_TBMATCHR_R

#define WTIMER5_TBMATCHR_R   (*((volatile u32 *)0x4004F034))

◆ WTIMER5_TBMR_R

#define WTIMER5_TBMR_R   (*((volatile u32 *)0x4004F008))

◆ WTIMER5_TBPMR_R

#define WTIMER5_TBPMR_R   (*((volatile u32 *)0x4004F044))

◆ WTIMER5_TBPR_R

#define WTIMER5_TBPR_R   (*((volatile u32 *)0x4004F03C))

◆ WTIMER5_TBPS_R

#define WTIMER5_TBPS_R   (*((volatile u32 *)0x4004F060))

◆ WTIMER5_TBPV_R

#define WTIMER5_TBPV_R   (*((volatile u32 *)0x4004F068))

◆ WTIMER5_TBR_R

#define WTIMER5_TBR_R   (*((volatile u32 *)0x4004F04C))

◆ WTIMER5_TBV_R

#define WTIMER5_TBV_R   (*((volatile u32 *)0x4004F054))